A Family of Zero-Voltage-Transition Magnetic Coupling Bidirectional DC/DC Converters ^†

Abstract

In this paper, a family of zero-voltage-transition (ZVT) magnetic coupling bidirectional DC/DC converters (BDCs) is proposed. The coupling inductor has two functions: to serve as a filter; and to provide the auxiliary current. In addition, the phase-shifting control method is used to reduce the conduction loss of the auxiliary circuit. The auxiliary switches are all working under zero-current-switching (ZCS) conditions; thus, all the switches have no switching loss. Furthermore, compared with the traditional ZVT implementation method based on the coupled inductor, this topology avoids the input source current notch and has a smaller ripple. Finally, a prototype of 800 W BDC is built to verify the feasibility of the proposed topology.

1. Introduction

With the continuous growth of systems with energy storage devices, research on bidirectional DC–DC converters has been greatly promoted. Bidirectional DC–DC converters are widely used in photovoltaic and energy storage systems [1,2], electric/hybrid vehicles [3,4], uninterrupted power supply systems [5], fuel cell power systems [6,7], etc. In these applications, converters are required to have low current ripple requirements at the energy storage port. If electrical isolation is not required between the high-voltage port and low-voltage port, the BDC topology is usually chosen due to its low cost and simple structure. For BDC, switching loss is the main reason for limiting frequency increases. Therefore, in order to achieve a high-efficiency and high-frequency power conversion of BDC, it is necessary to introduce soft-switching technology.

One effective method to achieve the purpose of soft-switching is to make the BDC work in near-critical conduction modes [8,9,10]. However, the input current has a larger ripple, which leads to a high conduction loss and easy core saturation.

Quasi-resonant technology realizes the zero-voltage-switching (ZVS) of the main switch by using LC resonance to generate zero voltage when the main switch is turned on [11,12]. However, a large circulating current exists in the circuit, which leads to an increase in conduction loss. In addition, the switching frequency changes in a wide range when the load changes greatly, which will make the design of passive devices more difficult.

Active clamp ZVS technology also needs to add a resonant inductor in the main circuit to realize the ZVS of the main switch [13,14]. The circulating current of the auxiliary circuit is large, which increases the conduction loss. Moreover, the main switch has high voltage stress.

As the auxiliary circuit is removed from the main circuit and the auxiliary switch operates only during the period before and after the main switch is turned on, the conduction loss in the ZVT converter is reduced, while the voltage stress of the main switch is lower than that of the quasi-resonant converter and active clamp converter [15,16,17,18]. These ZVT converters all need additional inductors as resonant inductors, which are disadvantageous to the improvement of power density because of the large volume and weight of magnetic components. Several soft-switching technologies based on coupled inductors have been proposed in [19,20,21,22,23,24,25,26,27,28].

In [19], a coupled winding is added to the same core of the main inductor to realize the soft switching of the main switch. In the ZVT BDC proposed in [20], a coupled inductor and two unidirectional auxiliary switches are used in the auxiliary circuit. A ZVT BDC is described in [21], while the auxiliary circuit consists of a coupled inductor and two auxiliary switches. A family of ZVS Buck, ZVS Boost, and ZVS BDC topologies is presented in [22], and the auxiliary circuit consists of a coupled inductor and a diode. In [23], a family of ZVS magnetic coupling BDC topologies is proposed. In those BDCs, the additional circuits contain two auxiliary switches. Two auxiliary voltage sources composed of passive components are used in the auxiliary circuit of the ZVS BDC in [24]. A ZVT BDC is proposed in [25], in which the auxiliary circuit consists of a coupled inductor, two unidirectional switches, and an auxiliary capacitor. In [26], a ZVT BDC is studied, in which all the switches implement ZVS or ZCS conditions. In [27], several ZVS DC–DC converters based on coupled inductors are proposed by changing the connection position of the coupling branch. A ZVS magnetic coupling BDC with no current notch at the low-voltage port is proposed in [28]. In [29], a ZVT PWM BDC based on coupled inductors is proposed. This topology needs two cores, increasing the complexity of the system. An overview of soft-switching technologies for BDC is given in [30].

As shown in Figure 1, there is an input current notch in the ZVS BDCs proposed in [20,21,23,24,26], which would hurt the life of storage equipment. In this paper, a family of ZVT magnetic coupling BDCs is proposed. The coupling inductor not only serves as a filter but also provides the auxiliary current. Compared with the traditional ZVS implementation method, this topology avoids the input source current notch and has a smaller ripple.

Figure 1. General circuit of ZVS BDCs with coupled filter inductors in [20,21,23,24,26]. (a) General circuit; (b) key waveforms of the input currents.

In Section 2, the topologies and operation process are demonstrated. In Section 3, the ZVT conditions of the main switches, the loss analysis, and the comparison between the proposed ZVT BDCs and the existing ZVT BDCs are given in detail. Moreover, the current frequency spectrum of the low-voltage port comparison between the proposed ZVT BDC and the traditional ZVT BDC is provided. In Section 4, the experimental results verify the validity of the topology. Finally, the conclusions are summarized.

2. Operation Process Analysis

2.1. Proposed ZVT BDCs

The ZVT magnetic coupling BDCs are shown in Figure 2. S₁ and S₂ are the switches of the main power circuit. S_SS1 and S_SS2 are the switches of the auxiliary circuit. C_S1, C_S2, and C_a are the three auxiliary capacitors. The coupled inductor is equivalent to an ideal transformer T, L_m (the excitation inductor), and L_r (the leakage inductor). C₁ and C₂ are filter capacitors of Port 1 and Port 2. The difference between Topology 1 (as shown in Figure 2a) and Topology 2 (as shown in Figure 2b) is that the auxiliary circuit of Topology 1 is connected between Port 2 and the ground, and the auxiliary circuit of Topology 2 is connected between Port 1 and Port 2.

Figure 2. The proposed ZVS BDCs. (a) Topology 1; (b) Topology 2.

2.2. Operation Analysis of the Proposed ZVS BDCs

2.2.1. Operation Analysis of Topology 1

In Topology 1, as shown in Figure 2a, the switching process of each switch is shown in Figure 3. Taking the ZVS implementation of S₂ as an example, the switching process is analyzed, and the equivalent circuit of each stage is shown in Figure 4.

Figure 3. ZVS implementation of the main switch for topology 1. (a) ZVS implementation of S₁; (b) ZVS implementation of S₂.

Figure 4. The equivalent circuit for each stage of Topology 1. (a) t₀–t₁; (b) t₁–t₂; (c) t₂–t₄; (d) t₄–t₅; (e) t₅–t₆; (f) t₆–t₇; (g) t₇–t₉; (h) t₉–t₁₀.

Interval 1 [t₀–t₁]: At t₀, S_SS2 is turned under the ZCS condition. The current i_SS increases because of the voltage clamp action of C_a, and the equivalent circuit is shown in Figure 4a.

Interval 2 [t₁–t₂]: At t₁, S₂ is turned off under the ZVS condition because of C_S1 and C_S2. During this interval, v_S1 decreases, v_S2 increases, C_S1 discharges, C_S2 charges, and the equivalent circuit is shown in Figure 4b. The current i_SS at the resonance stage is:

$$i_{\mathrm{SS}}=i_{\mathrm{L}}(t_1)+2A_{11}{C}_{\mathrm{S}}{\omega }_{11}\sin ({\omega }_{11}(t-t_1)+{\theta }_{11})$$

(1)

$${\omega }_{11}=\frac{1}{\sqrt{2L_{\mathrm{r}}{C}_{\mathrm{S}}}}$$

(2)

$$A_{11}=\sqrt{{V_{\mathrm{ca}}}^2+{\left[\frac{i_{\mathrm{SS}}(t_1)-i_{\mathrm{L}}(t_1)}{2C_{\mathrm{S}}{\omega }_{11}}\right]}^2}$$

(3)

$${\theta }_{11}=\arctan \frac{i_{\mathrm{SS}}(t_1)-i_{\mathrm{L}}(t_1)}{-2C_{\mathrm{S}}{\omega }_{11}{V}_{\mathrm{ca}}}+\pi$$

(4)

Interval 3 [t₂–t₃]: At t₂, v_S1 decreases to 0, v_S2 increases to V₁, and i_S1 is a negative value, the equivalent circuit for this stage is shown in Figure 4c.

Interval 4 [t₃–t₄]: At t₃, S₁ is turned on under the ZVS condition.

Interval 5 [t₄–t₅]: The current i_SS is reduced to 0 at t₄, and the equivalent circuit for this stage is shown in Figure 4d.

Interval 6 [t₅–t₆]: S_SS1 is turned on at t₅. The current i_SS increases because of the voltage clamp action of the capacitor C_a, and the equivalent circuit is shown in Figure 4e.

Interval 7 [t₆–t₇]: S₁ is turned off under ZVS condition at t₆ because of C_S1 and C_S2. During this period, v_S1 increases, v_S2 decreases, C_S1 charges, C_S2 discharges, and the equivalent circuit is shown in Figure 4f. The auxiliary current i_SS at the resonance stage is:

$$i_{\mathrm{SS}}=i_{\mathrm{L}}(t_6)+2A_{12}{C}_{\mathrm{S}}{\omega }_{12}\sin ({\omega }_{12}(t-t_6)+{\theta }_{12})$$

(5)

$${\omega }_{12}=\frac{1}{\sqrt{2L_{\mathrm{r}}{C}_{\mathrm{S}}}}$$

(6)

$$A_{12}=\sqrt{{\left(V_1-V_{\mathrm{ca}}\right)}^2+{\left[\frac{i_{\mathrm{SS}}(t_6)-i_{\mathrm{L}}(t_6)}{2C_{\mathrm{S}}{\omega }_{12}}\right]}^2}$$

(7)

$${\theta }_{12}=\arctan \frac{i_{\mathrm{SS}}(t_6)-i_{\mathrm{L}}(t_6)}{2C_{\mathrm{S}}{\omega }_{12}(V_1-V_{\mathrm{ca}})}$$

(8)

Interval 8 [t₇–t₈]: At t₇, v_S1 increases to V₁, v_S2 decreases to 0, and i_S2 is a negative value. The equivalent circuit for this stage is shown in Figure 4g.

Interval 9 [t₈–t₉]: S₂ is turned on under the ZVS condition at t₈.

Interval 10 [t₉–t₁₀]: The current i_SS is reduced to 0 at t₉, and the equivalent circuit for this stage is shown in Figure 4h.

2.2.2. Operation Analysis of Topology 2

In Topology 2, as shown in Figure 2b, the switching process of each switch is shown in Figure 5. The switching process of S₁ is analyzed, and the equivalent circuit of each stage is shown in Figure 6.

Figure 5. ZVS implementation of the main switch for Topology 2. (a) ZVS implementation of S₁; (b) ZVS implementation of S₂.

Figure 6. The equivalent circuit for each stage of Topology 2. (a) t₀–t₁; (b) t₁–t₂; (c) t₂–t₄; (d) t₄–t₅; (e) t₅–t₆; (f) t₆–t₇; (g) t₇–t₉; (h) t₉–t₁₀.

Interval 1 [t₀–t₁]: At t₀, S_SS2 is turned on under the ZCS condition.

Interval 2 [t₁–t₂]: At t₁, S₂ is turned off under the ZVS condition. The current i_SS at the resonance stage is:

$$i_{\mathrm{SS}}=i_{\mathrm{L}}(t_1)+2A_{21}{C}_{\mathrm{S}}{\omega }_{21}\sin ({\omega }_{21}(t-t_1)+{\theta }_{21})$$

(9)

$${\omega }_{21}=\frac{1}{\sqrt{2L_{\mathrm{r}}{C}_{\mathrm{S}}}}$$

(10)

$$A_{21}=\sqrt{{\left(V_1+V_{\mathrm{ca}}\right)}^2+{\left[\frac{i_{\mathrm{SS}}(t_1)-i_{\mathrm{L}}(t_1)}{2C_{\mathrm{S}}{\omega }_{21}}\right]}^2}$$

(11)

$${\theta }_{21}=\arctan \frac{i_{\mathrm{SS}}(t_1)-i_{\mathrm{L}}(t_1)}{2C_{\mathrm{S}}{\omega }_{21}(-V_1-V_{\mathrm{ca}})}+\pi$$

(12)

Interval 3 [t₂–t₃]: At t₂, v_S1 decreases to 0, v_S2 increases to V₁, and i_S1 is a negative value.

Interval 4 [t₃–t₄]: At t₃, S₁ is turned on under the ZVS condition.

Interval 5 [t₄–t₅]: S₁ is on during this period.

Interval 6 [t₅–t₆]: S_SS1 is turned on under the ZCS condition at t₅.

Interval 7 [t₆–t₇]: S₁ is turned off under the ZVS condition at t₆. The current i_SS at the resonance stage is:

$$i_{\mathrm{SS}}=i_{\mathrm{L}}(t_6)+2A_{22}{C}_{\mathrm{S}}{\omega }_{22}\sin ({\omega }_{22}(t-t_6)+{\theta }_{22})$$

(13)

$${\omega }_{22}=\frac{1}{\sqrt{2L_{\mathrm{r}}{C}_{\mathrm{S}}}}$$

(14)

$$A_{22}=\sqrt{{V_{\mathrm{ca}}}^2+{\left[\frac{i_{\mathrm{SS}}(t_6)-i_{\mathrm{L}}(t_6)}{2C_{\mathrm{S}}{\omega }_{22}}\right]}^2}$$

(15)

$${\theta }_{22}=\arctan \frac{i_{\mathrm{SS}}(t_6)-i_{\mathrm{L}}(t_6)}{-2C_{\mathrm{S}}{\omega }_{22}{V}_{\mathrm{ca}}}$$

(16)

Interval 8 [t₇–t₈]: At t₇, i_S2 is a negative value.

Interval 9 [t₈–t₉]: S₂ is turned on under the ZVS condition at t₈.

Interval 10 [t₉–t₁₀]: S₂ is on during this period.

2.3. Other ZVT BDC Topologies

In addition to the topologies shown in Figure 2, other ZVT BDCs based on coupled inductor are shown in Figure 7.

Figure 7. Other ZVT BDCs. (a) Topology 1; (b) Topology 2.

3. Performance Analysis

3.1. Analysis of Input Current Ripple

As shown in Figure 3 and Figure 5, i_L is nearly constant during the resonance stage (t₁–t₂) and (t₆–t₇), and the ripple of i_L is:

$$\Delta I_{\mathrm{L}}\approx \frac{V_2}{L_{\mathrm{m}}}{d}_2{T}_{\mathrm{S}}$$

(17)

To further illustrate the advantages of the proposed ZVT BDCs, the harmonic comparison of i_L is compared between the ZVT BDC (shown in Figure 2a) and the traditional ZVS BDC (represented in [23]). Those two simulation models are built, with the simulation performed at the same voltage and power levels.

The simulation results are shown in Figure 8 and Figure 9. Figure 8 shows the simulation results in Boost mode and Figure 9 in Buck mode. Figure 8a,b show the current i₂ and its harmonic analysis of ZVS BDC in [23], and when P₁ = 800 W, the harmonic amplitude of i₂ is 3.12 dBA (100 kHz). Figure 8c,d present the simulation results of the proposed ZVT BDC; the harmonic amplitude of i₂ is 0.63 dBA (100 kHz). As shown in Figure 9, when P₂ = 800 W, the proposed ZVT BDC has a 1.89 dBA (100 kHz) decrease in the harmonic amplitude of i₂ compared to ZVS BDC in [23].

Figure 8. Harmonic comparison in Boost mode. (a) Input current of ZVS BDC in [23]; (b) harmonic analysis of input current of ZVS BDC in [23]; (c) input current of ZVT BDC (shown in Figure 2a); (d) harmonic analysis of input current of ZVT BDC (shown in Figure 2a).

Figure 9. Harmonic comparison in Buck mode. (a) Output current of ZVS BDC in [23]; (b) harmonic analysis of output current of ZVS BDC in [23]; (c) output current of ZVT BDC (shown in Figure 2a); (d) harmonic analysis of output current of ZVT BDC (shown in Figure 2a).

3.2. Loss Analysis

In order to theoretically analyze the loss comparison between the traditional BDC and the proposed ZVT BDC, two simulation models are established. These work at 100 kHz and 500 kHz, respectively. The parameters are shown in Table 1, the proposed ZVT BDC is shown in Figure 2a, and the loss estimation is shown in Table 2.

Table 1. Detail parameters of 800 W ZVS Boost converter.

fS = 100 kHz				fS = 500 kHz
Parameter	Value	Parameter	Value	Parameter	Value	Parameter	Value
V2/V	50	V1/V	100	V2/V	50	V1/V	100
P1max/W	800	n	1	P1max/W	800	n	1
Lc/μH	3.8	Lm/μH	130	Lc/μH	0.85	Lm/μH	160
C1/μF	1000	C2/μF	1000	C1/μF	1000	C2/μF	1000
CS/nF	2.2	Ca/μF	200	CS/nF	1	Ca/μF	80

Table 2. Loss comparison.

Loss Source	fS = 100 kHz		fS = 500 kHz
	Traditional BDC	Proposed BDC	Traditional BDC	Proposed BDC
Pc_S	2.1 W	2.5 W	2.1 W	3.1 W
Pc_SS	---	5.4 W	---	10.4 W
Ps_S	19.1 W	---	95.5 W	---
PRR	---	0.8 W	---	4.2 W
Core loss	1.9 W	2.1 W	0.3 W	0.4 W
Copper loss	2.7 W	3.3 W	2.9 W	4.3 W

For the proposed ZVT BDC, MOSFET IRFP4668 is applied as the main switch, and MOSFET SUP90142E is utilized as the auxiliary switch, respectively. The on-resistance of the main switch is 0.008 Ω, the on-resistance of the auxiliary switch is 0.017 Ω, and the diode forward voltage of the auxiliary switch is 0.85 V (the junction temperature (Tj) is 75°). The core of the coupled inductor is E220–18. In the traditional BDC model, the filter inductor adopts the magnetic core KS25060A, and the main switch adopts MOSFET IRFP4668.

For the traditional BDC, the main loss includes P_{c_S} (conduction loss of S₁ and S₂), P_{s_S} (switching loss of S₁ and S₂), core loss, and copper loss. For the proposed ZVS BDC, the main loss includes P_{c_S} (conduction loss of S₁ and S₂), P_{c_SS} (conduction loss of S_SS1 and S_SS2), P_RR (Reverse recovery loss of S_SS1 and S_SS2), core loss, and copper loss.

When the switching frequency of the converter is increased to more than 500 kHz, the switching loss of the conventional BDC will greatly reduce the efficiency of the converter; the introduction of soft-switching measures is especially necessary.

3.3. Topology Comparison

The ZVS conditions can be realized when the circuit is operating under Buck mode or Boost mode in the ZVS BDC in [19,22,27]. Table 3 shows the topology comparison between the ZVS BDC in the existing literature and the proposed ZVS BDC (as shown in Figure 2a).

Table 3. Topology comparison.

Topology	Number of Auxiliary Switches	Number of Auxiliary Diodes	Current Notch	Voltage Stress of Auxiliary Switches
ZVT BDC [17]	2	2	exist	max{DV1, (1 − D)V1}
ZVS BDC [18]	2	0	exist	Buck: V2 Boost: V1 − V2
ZVT BDC [20]	2	2	exist	(1 + nD)V2
ZVT BDC [21]	2	0	exist	nDV1
ZVS BDC [23]	2	0	exist	Sa1: (n + 1)V2 Sa2: (n + 1)( V1 − V2)
ZVS BDC [24]	2	2	exist	Buck: max{|(n − 1)(V1 − V2)|, V2 + n(V1 − V2)} Boost: max{|(n − 1)V2|, V1 + (n − 1)V2}
ZVT BDC [25]	2	2	no	Buck: >0.5 V2 Boost: >0.5 V2
ZVT BDC [26]	2	0	exist	Sa1: (n + 1)(V1 − V2) Sa2: (n + 1)V2
ZVS BDC [28]	2	2	no	SSS1: $\frac{2}{3}\left[\frac{L_1\left(V_1-V_2\right)}{L_1+L_{\mathrm{c}}-2M}+V_2\right]-\frac{1}{3}{V}_1$ SSS2: $-\frac{2}{3}\frac{\left(L_{\mathrm{c}}-M\right)V_2}{L_1+L_{\mathrm{c}}-2M}+\frac{1}{3}{V}_1$
Proposed ZVT BDCs	2	0	no	SSS1: V1 − Vca SSS2: Vca

The topologies in [17,18] construct auxiliary circuits by adding auxiliary inductors, and the topology in [24] constitutes an auxiliary circuit by adding an auxiliary inductor and introducing a coupling inductor. The topologies in [19,20,21,22,23,25,26,27,28] and this paper use coupling inductors to construct auxiliary branches, which reduce the number of inductors. In order to realize soft switching in both operating modes (Buck and Boost), two auxiliary switches are required. To reduce the loss of auxiliary circuits, the diodes in [20,25,28] need to have good reverse recovery characteristics and low–forward voltage drops, which will increase the cost. In the topologies in [17,18,19,20,21,22,23,24,26], to realize the ZVT of main switches, notches exist in the current at Port 2. When Port 2 is connected to a battery, the current notch can adversely affect the battery life. However, the proposed ZVT BDC can avoid this notch phenomenon. For the topologies with no current notch in [25,28] and the proposed ZVT BDC, the current stress of the auxiliary switch depends on the current and ripple at Port 2, and the current stress is similar when the power and voltage levels are the same. In terms of voltage stress, the topology of the proposed ZVT BDC is less than that of [25].

4. System Design

4.1. Design of Initial Value V_ca

4.1.1. Design of Initial Value V_ca in Topology 1

For Topology 1, shown in Figure 2a, in the switching process shown in Figure 3, the resonance process should be ignored to simplify the analysis. The voltage V_ca of the auxiliary capacitor C_a during the period (t₀–t₁) is:

$$V_{\mathrm{ca}}=\frac{I_{\mathrm{SS}}{L}_{\mathrm{r}}}{t_1-t_0}$$

(18)

During the period (t₅–t₆), the voltage V_ca of C_a is:

$$V_{\mathrm{ca}}=V_1-\frac{I_{\mathrm{SS}}{L}_{\mathrm{r}}}{t_6-t_5}$$

(19)

When the period (t₀–t₁) and (t₅–t₆) are the same, the phase-shifting duty cycles of the auxiliary switch S_SS1 and S_SS2 are the same. According to (18) and (19), the initial value V_ca = 0.5 V₁ can be obtained. Considering the resonant process in the dead time, the actual V_ca is different from 0.5 V₁.

4.1.2. Design of Initial Value V_ca in Topology 2

For Topology 2, shown in Figure 2b, the switching process is shown in Figure 5. During the period (t₀–t₁), V_ca is:

$$V_{\mathrm{ca}}=-V_1+\frac{I_{\mathrm{SS}}{L}_{\mathrm{r}}}{t_1-t_2}$$

(20)

During the period (t₅–t₆), V_ca is:

$$V_{\mathrm{ca}}=-\frac{I_{\mathrm{SS}}{L}_{\mathrm{r}}}{t_6-t_5}$$

(21)

When the periods (t₀–t₁) and (t₅–t₆) are the same, the initial value V_ca = −0.5 V₁ can be obtained according to (20) and (21). Considering the resonant process in the dead time, the actual V_ca is different from −0.5 V₁.

4.2. Design of the Coupled Inductor

In the topology shown in Figure 2, the turn ratio of transformer T is n, the primary side is connected to the main circuit, the excitation inductor acts as a filter, and the secondary side is connected to the auxiliary circuit. i_L is the current flowing through the excitation inductor, i_SS is the current of the auxiliary circuit, i_SS′ is the current converted to the primary side, and i_SS′ = i_SS/n. The current of Port 2 is:

$$i_2=i_{\mathrm{SS}}+i_{\mathrm{c}}$$

(22)

The current i_c is:

$$i_{\mathrm{c}}=i_{\mathrm{L}}-{i_{\mathrm{SS}}}^{\prime }$$

(23)

According to (22) and (23), the current of port 2 is i₂ = i_SS + i_L − i_SS′. Therefore, when n = 1, i₂ = i_L.

In the topology shown in Figure 2, L_m is the filter inductor for the BDC, duty cycle d₂ is (1 − V₂/V₁), and the current ripple for i_L is:

$$\Delta i_L\approx \frac{V_2}{L_{\mathrm{m}}}{d}_2{T}_{\mathrm{S}}$$

(24)

The ripple Δi₂ = Δi_L, taking Δi_L = x₁i_L, x₁ is the ripple coefficient, and the value of L_m can be obtained according to the requirement of ripple.

4.2.1. Design of L_r in Topology 1

In Topology 1, the maximum value of auxiliary current i_SS is:

$$\Delta i_{\mathrm{SSmax}\_1}=\frac{V_1-V_{\mathrm{ca}}}{L_{\mathrm{r}}}{T}_{\mathrm{S}}{d}_{\mathrm{SS}1}$$

(25)

For Buck mode, the following condition should be met to realize the ZVS of S₁:

$$I_{\mathrm{L}}+\frac{1}{2}\Delta i_{\mathrm{L}}+\Delta i_{\mathrm{SSmax}\_1}>0$$

(26)

For Boost mode, the following condition should be met:

$$I_{\mathrm{L}}-\frac{1}{2}\Delta i_{\mathrm{L}}-\Delta i_{\mathrm{SSmax}\_1}<0$$

(27)

From (26) and (27), the value of L_r can be obtained.

4.2.2. Design of L_r in Topology 2

In topology 2, the maximum value of auxiliary current i_SS is:

$$\Delta i_{\mathrm{SSmax}\_2}=\frac{-V_{\mathrm{ca}}}{L_{\mathrm{r}}}{T}_{\mathrm{S}}{d}_{\mathrm{SS}2}$$

(28)

To realize the ZVS of S₁ and S₂, the following conditions should be satisfied:

$$I_{\mathrm{L}}+\frac{1}{2}\Delta i_{\mathrm{L}}+\Delta i_{\mathrm{SSmax}\_2}>0$$

(29)

$$I_{\mathrm{L}}-\frac{1}{2}\Delta i_{\mathrm{L}}-\Delta i_{\mathrm{SSmax}\_2}<0$$

(30)

From (29) and (30), the value of L_r can be obtained.

4.3. Design of C_S

4.3.1. Design of C_S in Topology 1

For Topology 1, according to the ZVS implementation process as shown in Figure 3b, dead time needs to satisfy:

$$\Delta t_{12}=t_2-t_1=\frac{1}{{\omega }_{11}}(\arccos \frac{-V_{\mathrm{ca}}}{A_{11}}-\arccos \frac{V_1-V_{\mathrm{ca}}}{A_{11}})<t_{\mathrm{D}}$$

(31)

$$\Delta t_{67}=t_7-t_6=\frac{1}{{\omega }_{12}}(\arccos \frac{-V_{\mathrm{ca}}}{A_{12}}-\arccos \frac{V_1-V_{\mathrm{ca}}}{A_{12}})<t_{\mathrm{D}}$$

(32)

At time t₇, the values of i_c and i_S2 are:

$$i_{\mathrm{c}}(t_7)=-2A_{12}{C}_{\mathrm{S}}{\omega }_{12}\sin ({\omega }_{12}(t_7-t_6)+{\theta }_{12})$$

(33)

$$i_{\mathrm{S}2}(t_7)=-A_{12}{C}_{\mathrm{S}}{\omega }_{12}\sin ({\omega }_{12}(t_7-t_6)+{\theta }_{12})$$

(34)

When S₂ is turned on, i_S2 needs to meet:

$$i_{\mathrm{S}2}(t_{\mathrm{S}2\_\mathrm{on}})=i_{\mathrm{S}2}(t_7)+\left(\frac{V_{\mathrm{ca}}}{L_{\mathrm{r}}}+\frac{V_2}{L_{\mathrm{m}}}\right)\times \left(t_{\mathrm{D}}-\Delta t_{67}\right)<0$$

(35)

According to (31)–(35),the value of C_S can be obtained.

4.3.2. Design of C_S in Topology 2

For Topology 2, according to the ZVS implementation process as shown in Figure 5a, in order to realize the ZVS of S₁, the following conditions should be met:

$$\Delta t_{12}=t_2-t_1=\frac{1}{{\omega }_{21}}(\arccos \frac{-V_1-V_{\mathrm{ca}}}{A_{21}}-\arccos \frac{-V_{\mathrm{ca}}}{A_{21}})<t_{\mathrm{D}}$$

(36)

$$\Delta t_{67}=t_7-t_6=\frac{1}{{\omega }_{22}}(\arccos \frac{-V_1-V_{\mathrm{ca}}}{A_{22}}-\arccos \frac{-V_{\mathrm{ca}}}{A_{22}})<t_{\mathrm{D}}$$

(37)

$$i_{\mathrm{S}1}(t_{\mathrm{S}1\_\mathrm{on}})=i_{\mathrm{S}1}(t_2)+\left(\frac{-V_{\mathrm{ca}}}{L_{\mathrm{r}}}+\frac{V_1-V_2}{L_{\mathrm{m}}}\right)\times \left(t_{\mathrm{D}}-\Delta t_{12}\right)<0$$

(38)

According to (36)–(38), the value of C_S can be obtained.

4.4. Design of C_a

4.4.1. Design of C_a in Topology 1

As the voltage source of the auxiliary circuit, the voltage V_ca of the auxiliary capacitor C_a can be determined according to the duration of (t₀–t₁) and (t₅–t₆), and the voltage ripple ΔV_ca is:

$$\Delta V_{\mathrm{ca}}=\frac{1}{C_{\mathrm{a}}}{\displaystyle {\int }_{t_0}^{\frac{T_{\mathrm{s}}}{2}}{i}_{\mathrm{SS}}(t)}dt$$

(39)

In order to simplify the analysis, ignoring the resonance process and according to (39) and Figure 3, ΔV_ca can be obtained:

$$\Delta V_{\mathrm{ca}}\approx \frac{V_1{V}_{\mathrm{ca}}{T}_{\mathrm{S}}^2{d}_{\mathrm{SS}2}^2}{2C_{\mathrm{a}}{L}_{\mathrm{r}}(V_1-V_{\mathrm{ca}})}$$

(40)

Taking ΔV_ca = x₂V_ca, x₂ is the voltage ripple coefficient, and the value of auxiliary capacitance C_a can be obtained according to the requirement of voltage ripple.

4.4.2. Design of C_a in Topology 2

According to (39), and Figure 5, ΔV_ca can be obtained:

$$\Delta V_{\mathrm{ca}}\approx -\frac{V_1\left(V_1+V_{\mathrm{ca}}\right)T_{\mathrm{S}}^2{d}_{\mathrm{SS}2}^2}{2C_{\mathrm{a}}{L}_{\mathrm{r}}{V}_{\mathrm{ca}}}$$

(41)

Similarly, according to the ripple requirements, the value of the auxiliary capacitor C_a can be obtained.

Taking the ZVT BDC (as shown in Figure 2a) design process as an example, a step-by-step design methodology working in Boost mode is given in Table 4. The other topologies and the design process in Buck mode are similar and will not be repeated.

Table 4. Step-by-step design methodology.

Step 1	Determine the voltages (V1 and V2) and power level according to the system requirements.
Step 2	Ignore the resonance process and select initial value of Vca, Vca = 0.5V1.
Step 3	Design Lm of T according to the requirements of current ripple, and $L_{\mathrm{m}}\ge \frac{V_2{d}_2{T}_{\mathrm{S}}}{x_1{I}_L}$.
Step 4	Select n = 1.
Step 5	Design Lr of T according to IL − 0.5ΔiL − ΔiSS < 0, in which $\Delta i_{\mathrm{SS}}=\frac{V_1-V_{\mathrm{ca}}}{L_{\mathrm{r}}}{T}_{\mathrm{S}}{d}_{\mathrm{SS}1}$.
Step 6	Determine value range of (CS, td) according to $\{\begin{array}{l}{t}_{12}<t_{\mathrm{d}}\\ t_{67}<t_{\mathrm{d}}\\ i_{\mathrm{S}2}(t_{\mathrm{S}2\_\mathrm{on}})<0\end{array}$, and select CS and td.
Step 7	Design Ca according to the requirements of voltage ripple, and $C_{\mathrm{a}}\ge \frac{1}{x_2{V}_{\mathrm{ca}}}{\displaystyle {\int }_{t_0}^{\frac{T_{\mathrm{s}}}{2}}{i}_{\mathrm{SS}}(t)}dt$.
Step 8	Simulation and experimental verification.

4.5. Design of the Control Method

Figure 10 shows the implementation of the control method, which is divided into two cases (Buck mode and Boost mode). The PI regulator of the output voltage (V₂ under Buck, V₁ in Boost) generates the modulation signal v_ctrl, and the phase difference between the carrier signals v_triS1 and v_triS2 is 180°, generating the drive signals of S₁ and S₂ by comparators. To obtain the driving signals of S_SS1 and S_SS2, firstly, judge the working mode of the system (Buck mode or Boost mode) according to the voltages and currents of Ports 1 and 2. The phase-shifting duty cycles d_SS1 and d_SS2 are calculated according to the working mode. In order to ensure that the auxiliary current is large enough, d_SS1 and d_SS2 require a certain amount of margin Δd. The phase-shifting controller shifts the carrier signals v_triS1 and v_triS2 according to d_SS1 and d_SS2, and the carrier signals of S_SS1 and S_SS2, v_triSS1 and v_triSS2, are obtained. The driving signals of S_SS1 and S_SS2 are generated by comparators.

Figure 10. Control schematic diagram.

5. Experimental Verification

Using DSP TMS320F28377SPTPT as the controller, MOSFET IRFP4668 as the main switch, and MOSFET SUP90142E as the auxiliary switch, a BDC prototype is built, as shown in Figure 11. Detailed experimental parameters are shown in Table 5.

Figure 11. Experimental platform.

Table 5. Detail parameters of experimental platform.

Parameter	Value	Parameter	Value
V2/V	40~60	V1/V	100
fS/kHz	100	n	1
Lc/μH	3.8	Lm/μH	130
C1 and C2/μF	1000	CS/nF	2.2
P1max and P2max/W	800	Ca/μF	200

To verify the validity of the two ZVT BDCs shown in Figure 2, two sets of experiments were conducted, in each set of experiments; the power level is 800 W. The experimental waveforms of these two topologies operating in two modes (Buck and Boost) and two duty cycles (d₁ = 0.4 and d₁ = 0.6) are given. The control method utilized in the experiments is shown in Figure 10.

Figure 12, Figure 13, Figure 14 and Figure 15 show the experimental waveforms of the topology shown in Figure 2a.

Figure 12. Experimental waveforms of BDC Topology 1 when P₁ = 800 W, V₁ = 100 V, d₁ = 0.4 (t − 2 μs/div). (a) v_DS2, v_GS2, and i_c; (b) v_DS1, v_GS1, and i₂; (c) v_GSS1, v_GS2, and i_SS; (d) V₁, V₂, and V_ca.

Figure 13. Experimental waveforms of BDC Topology 1 when P₁ = 800 W, V₁ = 100 V, d₁ = 0.6 (t − 2 μs/div). (a) v_DS2, v_GS2, and i_c; (b) v_DS1, v_GS1, and i₂; (c) v_GSS1, v_GS2, and i_SS; (d) V₁, V₂, and V_ca.

Figure 14. Experimental waveforms of BDC Topology 1 when P₂ = 800 W, V₁ = 100 V, d₁ = 0.4 (t − 2 μs/div). (a) v_DS1, v_GS1, and i_c; (b) v_DS2, v_GS2, and i₂; (c) v_GSS2, v_GS1, and i_SS; (d) V₁, V₂, and V_ca.

Figure 15. Experimental waveforms of BDC Topology 1 when P₂ = 800 W, V₁ = 100 V, d₁ = 0.6 (t − 2 μs/div). (a) v_DS1, v_GS1, and i_c; (b) v_DS2, v_GS2, and i₂; (c) v_GSS2, v_GS1, and i_SS; (d) V₁, V₂, and V_ca.

When ZVS BDC operates in Boost mode, P₁ = 800 W, V₁ = 100 V, Figure 12 and Figure 13 are the experimental waveforms under the condition of V₂ = 40 V and V₂ = 60 V, respectively. The main switches S₁ and S₂ are turned on and off under ZVS conditions, and the auxiliary switches S_SS1 and S_SS2 are turned on and off under ZCS conditions. When V₂ is 40 V and 60 V, in order to achieve the ZVS of S₂, the phase shift angles between the drive signals v_GSS1 and v_G2 can be 60° and 45°, respectively.

When ZVS BDC operates in Buck mode, P₂ = 800 W, V₁ = 100 V, Figure 14 and Figure 15 are the experimental waveforms under the condition of V₂ = 40 V and V₂ = 60 V, respectively. The main switches S₁ and S₂, are turned on and off under ZVS conditions, and the auxiliary switches S_SS1 and S_SS2 are turned on and off under ZCS conditions. When V₂ is 40 V and 60 V, in order to achieve the ZVS of S₁, the phase shift angles between the drive signals v_GSS2 and v_G1 can be 60° and 45°, respectively.

Figure 16, Figure 17, Figure 18 and Figure 19 show the experimental waveforms of the topology shown in Figure 2b.

Figure 16. Experimental waveforms of BDC Topology 2 when P₁ = 800 W, V₁ = 100 V, d₁ = 0.4 (t – 2 μs/div). (a) v_DS2, v_GS2, and i_c; (b) v_DS1, v_GS1, and i₂; (c) v_GSS1, v_GS2, and i_SS; (d) V₁, V₂, and V_ca.

Figure 17. Experimental waveforms of BDC Topology 2 when P₁ = 800 W, V₁ = 100 V, d₁ = 0.6 (t – 2 μs/div). (a) v_DS2, v_GS2, and i_c; (b) v_DS1, v_GS1, and i₂; (c) v_GSS1, v_GS2, and i_SS; (d) V₁, V₂, and V_ca.

Figure 18. Experimental waveforms of BDC Topology 2 when P₂ = 800 W, V₁ = 100 V, d₁ = 0.4 (t – 2 μs/div). (a) v_DS1, v_GS1, and i_c; (b) v_DS2, v_GS2, and i₂; (c) v_GSS2, v_GS1, and i_SS; (d) V₁, V₂, and V_ca.

Figure 19. Experimental waveforms of BDC Topology 2 when P₂ = 800 W, V₁ = 100 V, d₁ = 0.6 (t – 2 μs/div). (a) v_DS1, v_GS1, and i_c; (b) v_DS2, v_GS2, and i₂; (c) v_GSS2, v_GS1, and i_SS; (d) V₁, V₂, and V_ca.

When ZVS BDC operates in Boost mode, P₁ = 800 W, V₁ = 100 V, Figure 16 and Figure 17 are the experimental waveforms under the condition of V₂ = 40 V and V₂ = 60 V, respectively. The main switches S₁ and S₂ are turned on and off under ZVS conditions, and the auxiliary switches S_SS1 and S_SS2 are turned on and off under ZCS conditions. When V₂ is 40 V and 60 V, in order to achieve the ZVS of S₂, the phase shift angles between the drive signals v_GSS1 and v_G2 can be 60° and 45°, respectively.

When ZVS BDC operates in Buck mode, P₂ = 800 W, V₁ = 100 V, Figure 18 and Figure 19 are the experimental waveforms under the condition of V₂ = 40 V and V₂ = 60 V, respectively. The main switches S₁ and S₂ are turned on and off under ZVS conditions, and the auxiliary switches S_SS1 and S_SS2 are turned on and off under ZCS conditions. When V₂ is 40 V and 60 V, in order to achieve the ZVS of S₁, the phase shift angles between the drive signals v_GSS2 and v_G1 can be 60° and 45°, respectively.

As shown in Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18 and Figure 19, the current at Port 2 has no notch when these two proposed ZVT BDCs operate in both two modes (Buck and Boost). In Topology 1, V_ca > 0, and in Topology 2, V_ca < 0. When the power circuit operates in Buck mode, the current i_c flowing through the bridge arm (S₁ and S₂) changes from negative to positive before S₁ is turned on due to the auxiliary current. When the power circuit operates in Boost mode, i_c changes from positive to negative before S₂ is turned on, realizing ZVT conditions for S₁ and S₂. When the average value of i₂ changes, the peak of i_SS has different requirements. Thus, d_SS1 and d_SS2 need to be adjusted. In addition, auxiliary switches are turned on and off under ZCS conditions.

As shown in Figure 20, the main loss sources of a traditional BDC include conduction loss of the main switch, switching loss of the main switch, copper loss and core loss of the inductor. The main loss sources of the proposed ZVS BDC include the conduction loss of the main switch, conduction loss of the auxiliary switch, RR loss of the auxiliary switch, copper loss, and core loss of inductor. For the traditional BDC topology, switching loss accounts for the largest proportion of the total loss, while for the proposed BDC, the largest source is conduction loss. As shown in Figure 21, compared to the traditional BDC, the maximum efficiency of the proposed BDC (shown in Figure 2a) can be improved by 1.2%.

Figure 20. Loss analysis.

Figure 21. Efficiency curves with and without auxiliary circuit. (a) Boost; (b) Buck.

Through the theoretical analysis of the loss of traditional BDC, when the switching frequency is increased to more than 500 kHz, it is necessary to introduce the ZVT implementation measures. According to the efficiency curve of the existing topology, the loss analysis is carried out when the switching frequency is greater than 500 kHz, and the comparison of the theoretical efficiency values among different topologies under full load when the switching frequency f_S ≥ 500 kHz is shown in Table 6.

Table 6. Efficiency comparison when the switching frequency f_S ≥ 500 kHz.

Topology	Boost	Buck
ZVS BDC [17]	96.7%	95.2%
ZVS BDC [18]	97.2%	96.5%
ZVT BDC [20]	95.7%	95.6%
ZVT BDC [21]	97.7%	97.2%
ZVS BDC [23]	97.5%	97.5%
ZVS BDC [24]	96.3%	96.5%
ZVT BDC [25]	95.3%	95.4%
ZVT BDC [26]	92.2%	93.3%
ZVS BDC [28]	96.4%	96.2%
The proposed ZVT BDCs	96.7%	96.7%

6. Conclusions

In this paper, several ZVT magnetic coupling BDCs are proposed. In these topologies, the excitation inductor of the transformer acts as a filter, and the leakage inductor is used to generate auxiliary current. When the turn ratio is 1:1, the current of the original side and the secondary side is the same but in the opposite direction. Thus, the current notch at the low voltage port can be eliminated. The main switches can achieve ZVT conditions, and the auxiliary switches can achieve ZCS conditions. In order to verify the feasibility of these ZVT BDCs, 100-kHz and 800-W prototypes are built, and the experimental results of two working modes (Boost and Buck) are shown. Through detailed theoretical analysis and experimental verification, all switches of the converter realize soft switching, and no current notch exists at the low-voltage port. Compared with the traditional BDC, the maximum efficiency can be increased by 1.2%.