Switched Inductor DC–DC Boost Regulator Using Voltage-to-Time Controller for TEG Applications

Abstract

This paper presents a switched inductor (SI) DC–DC boost regulator designed for thermoelectric generator (TEG) applications. To boost and regulate the output voltage, two feedback loops are implemented which control the duty cycle of the SI clock. The first loop consists of a pulse skip modulation (PSM) controller that compares the load voltage and reference voltage. Based on the comparison output, the PSM will either pass or bypass the modulated pulse width signal generated from the second loop. The second loop replaces the conventional circuit design of the pulse width modulation (PWM) with a voltage-to-time converter (VTC). The VTC converts the difference between load and supply voltage to time delay resulting in a modulated pulse width. This work is the first to report on utilizing VTC circuit in the SI boost regulator. The proposed SI boost regulator is designed using 65 nm CMOS technology which converts the TEG voltage of 50 mV to support dynamic voltage scaling in the range of 0.6 V to 0.8 V. The PSM and PWM controller loops can tune the duty cycle of the clock in the range of 0 to 70%. It achieves a peak efficiency of 60.9% at 30 μW load power. Comparing the proposed single-stage SI boost regulator with the conventional two cascaded stages of switched-inductor boost converter followed by switched capacitor regulator, the area is reduced by 9.6× and power efficiency is increased by 1.35×.

1. Introduction

Thermal energy harvesting has gainedmuch attention in wearable electronics for realizing autonomous operations and miniaturized devices. Due to the temperature difference between the human body and ambient air, a potential difference $V_{TEG}$ is generated based on the Seebeck effect using thermoelectric generator (TEG). For a temperature gradient of 1 ${}^{\circ }$C, the commercial TEG generates a small voltage level $V_{TEG}$ between 10 mV and 30 mV [1]. With such a low voltage level, powering up the system-on-chip (SoC) is challenging. Therefore, a startup circuit is needed to start the system [2,3,4,5]. In addition, the boost DC–DC converter is required to convert the low $V_{TEG}$ to a higher value in the range of hundreds of millivolts [6,7]. Since the $V_{TEG}$ value is variable and depends on the availability of the ambient energy, a voltage regulator is required to support a steady and regulated voltage level $V_L$ and provide dynamic voltage scaling (DVS) to run SoCs at the optimum operating point. This paper will focus on the circuit design of a power management unit (PMU) that boosts, regulates and supports DVS from the TEG to SoC. To achieve such a design, a DC–DC boost converter and a voltage regulator should be built. There are two main types of DC–DC boost converters: charge pump [8] and switched-inductor converter [9,10,11]. The charge pump consists of diodes and capacitors to transfer the charges through charging and discharging phases. The output voltage is proportional to the number of stages; however, it is reduced by the voltage drop across the switches. In addition, the charge pump has inherent energy losses due to the charge distribution between the capacitors. On the other hand, switched-inductor (SI) DC–DC boost converter provides higher power efficiency but at the cost of a monolithic chip due to the usage of the inductor [12]. The SI output voltage depends on the duty cycle of the clock, which enables a high voltage conversion ratio. Hence, the switched-inductor boost converter is widely utilized in wearable devices [13].

To regulate the voltage and provide DVS through PMU, three main typologies are reported in the literature: low dropout (LDO) regulator [14,15], switched inductor (SI) [16,17] and switched capacitor (SC) [18] regulators. The output voltage level of the LDO depends on the voltage drop across the pass transistor resulting in low power efficiency at a high voltage conversion ratio. However, LDO’s output voltage has a low ripple (less than 10 mV) and it can be completely integrated on-chip with a small area. The SC output voltage relies on the capacitors’ configuration that produces various voltage gains such as but not limited to 1/2, 2/3 and 3/4. To achieve high power efficiency at different input/output voltage levels, it is essential to set the SC to its corresponding voltage gain. This requires more voltage gains in a single circuit over a wide range of input and output voltage. On the other hand, the SI regulator allows more flexibility while achieving high power efficiency because the output voltage is controlled by the clock duty cycle, unlike the configuration as in the SC regulator. However, SI regulator requires off-chip inductor. The selection of the voltage regulator depends on the design requirements of each block in the SoC, such as area, integration, power efficiency, and voltage ripple.

Figure 1a shows the block diagram of the conventional PMU that interfaces between the TEG energy source and the SoC for a wearable electronic device [19]. To startup the system, an additional energy harvesting source such as piezoelectric generator has been utilized [20] that initially powers up the device. The PMU consists of two circuits: SI DC–DC boost converter and voltage regulator. The SI converter boosts the $V_{TEG}$ and generates unregulated output voltage, whereas the voltage regulator generates a regulated and constant load voltage $V_L$ for the SoC. Such PMU design consumes higher power consumption and requires a larger area to accommodate the two blocks of the boost converter and voltage regulator. One possible way to reduce the PMU’s area and increase power efficiency is to utilize the SI boost regulator that boosts $V_{TEG}$ and regulates $V_L$, simultaneously, as shown in Figure 1b.

To achieve regulation against the change in input voltage and/or load current, a control feedback loop is required. Pulse width modulation (PWM) is a common control technique that regulates the output voltage in SI converter [21]. Conventional PWM consists of an error amplifier, a ramp generator, and a comparator. The error amplifier generates a voltage that is compared with a ramp generator by a comparator and produces a modulated pulse width signal with a duty cycle. This requires to carefully design a linear rise/fall output in respect to time. Sliding mode controller are deployed to control the regulation. It provides various advantages such as stability over wide line and load ranges, robustness, and good dynamic response [22]. The work in [23] reported a sliding mode control technique and dynamic prescribe performance function to track the output voltage error of the DC–DC converter caused by outside interference or uncertainty and improve the transient performance. PMW can also be implemented using digital logic gates such as an inverters chain or an RC time-constant circuit [24,25]. The delay, in this case, depends on the RC time constant of the inverter and can be controlled by digital bits. A bank of capacitors and resistors is added to further increase the delay. The work in [1] generates 16 possible pulse width signals based on a 4-bit controller by varying the time delay using a series of current starved inverters. However, the delay in the starved inverter relies on the amount of current discharged through a MOS transistor. Depending on the input voltage value, the transistor cannot be maintained in linear mode over a wide range of input voltage. The work in [26] also implements a current starved inverter as part of a time-based comparator to convert the difference between reference and load voltage into modulated pulse width signal. The conversion from voltage to time is implemented using current starved inverter which has a linearity issue as mentioned previously. The work in [7] utilizes one-shot pulse generator along with zero current switching (ZCS) and voltage monitor. The ZCS detects the inductor current when it reaches zero to improve the power efficiency. The ZCS utilized a comparator to compare between the load and intermediate voltage. If the load voltage is smaller than the intermediate node voltage, the comparator will generate a signal to the one-shot pulse generator to decrease the charging current and increase the pulse width. On the other hand, if the load current is greater than the intermediate load voltage, the on-shot pulse generator reduces pulse width of the controlled signal. The work in [2] implements a hysteretic on-off voltage regulation scheme to enable/disable the switching clock and regulate the load voltage. The voltage regulation is enabled once the load voltage reaches a specific value and detected by a power-on-reset signal. A switched capacitor voltage divider is utilized to divide the boosted voltage and compare it to reference voltages. Based on the comparison, the pulse width is modulated. The work in [12] regulates the output voltage to 1 V by dividing it using a voltage divider and comparing it to a reference voltage. The pulse width signals $t_1$ and $t_2$ that control the switches of the boost regulator are dynamically varied according to input and output voltages. The pulse width $t_1$ is generated using a current source and a capacitor. It is determined by the time required to discharge the current into a capacitor with respect to the input voltage. To regulate the output voltage to 1 V, $t_2$ is adjusted using a cascaded circuit of the one used for generating $t_1$. The capacitance is tuned based on the input voltage since the value of $t_2$ depends on the input voltage.

In this paper, the SI boost regulator is designed, implemented, and simulated in 65 nm CMOS technology node. The regulation is deployed using voltage-to-time converter (VTC) control technique that converts linearly the difference between supply and load voltage to modulated pulse width signal. The advantage of the VTC is that it provides high linearity and conversion gain across a wide range of voltage levels. High linearity is employed by charging a capacitor to the input voltage and then discharging it through a current source. The amount of charges Q stored in the capacitor C varies linearly with the input voltage $V_{in}$ ($Q=C{V}_{in}$). The time it takes to discharge the capacitor is linearly proportional to Q. This way, time delay has a linear relationship with the input voltage. The main contributions of this paper can be summarized as follows:

• A 6.5 $\mathsf{\mu }$W VTC circuit design that linearly converts a wide range of input voltage range between 0 to 1 V to a time delay. This design eliminates the non-linearity issue that exists in the conventional current-starved inverter delay unit. Two capacitors have been added in order to generate a linear time delay at much wider input voltage. The two capacitors act as a reservoir for charge and the delay is direct function of this charge. The capacitors’ values are selected in such a way to minimize the nonlinear effect on the delay.
• The VTC is utilized as pulse width modulation control technique in the SI regulator to boost and regulate the voltage simultaneously.

The rest of the paper is organized as follows. Section 2 explains the circuit design of the proposed VTC presenting detailed simulation results in 65 nm CMOS technology. Section 3 discusses the circuit design of the SI boost regulator using VTC. Section 4 presents the simulation results of the proposed regulator in 65 nm CMOS technology. Section 5 concludes the paper.

2. Voltage-to-Time Converter (VTC) Circuit Design

Figure 2 shows the VTC circuit design that is described in detail in [27]. To achive the conversion from voltage tot time domain, the VTC operates in two modes: sampling and evaluation. During the sampling mode, when the clock signals $V_{clk}$ = 0 and $V_{clkb}$ = 1, $M_3$ is off, and $M_7$ is on to charge the capacitor $C_2$ with $V_x$ = $V_{dd}$ resulting in an output voltage $V_{out}$ = 0. The pass gate ($M_1$, $M_2$) turns on to precharge $C_1$ with $V_c$ = $V_{in}$. On the other hand, the pass gate ($M_5$, $M_6$) is off to separate $V_x$ from $V_c$ in order to eliminate the short circuit current on the delay chain at low voltage levels of $V_{in}$. During the evaluation mode, when $V_{clk}$ = 1 and $V_{clkb}$ = 0, the pass gate ($M_5$, $M_6$) and $M_3$ turn on, whereas the pass gate ($M_1$, $M_2$) and $M_7$ turn off. In this mode, $V_c$ is shorted to $V_x$. Initially, if $V_{in}<V_{dd}$, then $V_c<V_x$ resulting in a reverse current flow from $C_2$ to $C_1$, as shown in Figure 3 (see gray waveform when $V_{in}$ = 0.1 V). On the other hand, if $V_{in}$ = $V_{dd}$, then $V_c$ follows $V_x$ as shown in Figure 3 when $V_{in}$ = 1 V. The capacitor current starts discharging through $M_4$. Hence, $V_x$ decreases and once it reaches $V_{sp}$ value, the inverter pulls up $V_{out}$ that is connected to another inverter to generate $V_{out-b}$. The $V_{out-b}$ is ANDED with $V_{clkb}$ to generate $V_{pw}$. Figure 3 depicts the waveform of the proposed VTC. This time delay, given in Equation (1), depends on four main parameters: $V_{dd}$ and $V_{in}$ voltage values, $V_{sp}$ voltage value, capacitors’ size of $C_1$ and $C_2$, and current I. The $V_{sp}$, given in Equation (2), relies on the aspect ratio of pmos and nmos transistors of the inverter ($\frac{{\beta }_n}{{\beta }_p}$). The I value depends on the amount of charges stored in the capacitors, which varies linearly with $V_{in}$, given that $V_{dd}$ is fixed. Thus, $t_d$ has a linear relationship with $V_{in}$.

$$t_d=\frac{C_1{V}_{in}+C_2{V}_{dd}-V_{sp}(C_1+C_2)}{I}$$

(1)

$$V_{sp}=\frac{V_{dd}-\left|V_{thp}\right|+\sqrt{\frac{{\beta }_n}{{\beta }_p}}{V}_{thn}}{1+\sqrt{\frac{{\beta }_n}{{\beta }_p}}}$$

(2)

The VTC circuit has been designed, implemented, and simulated in 65 nm CMOS technology. The input voltage range is from 0 V to 1 V at $V_{dd}$ = 1.2 V and a clock frequency of 30 kHz so that linear voltage-to-time conversion is achieved. Both capacitors $C_{1,2}$ and transistor $M_4$ sizes are selected to support a minimum duty cycle of 0.15 at the minimum $V_{in}$ of 0 V. A metal insulator metal (MIM) capacitors of $C_1$ = 200 pF and $C_2$ = 100 pF are utilized. The $M_4$ size of 500 nm/140 nm controlled by its gate voltage of $V_b$ = 0.6 V provides a current source of 17 $\mathsf{\mu }$A. The inverter is carefully sized to provide the desired $V_{sp}$. Hence, the aspect ratio of $M_9$ is 5× the aspect ratio of $M_8$ such that $V_{sp}$ = 0.35 V.

Table 1. VTC’s design parameters.

$V_{dd}$ (V)	1.2
$V_{in}$ (V)	0–1
$C_1$ (fF)	200
$C_2$ (fF)	100
$W_{1,2,5,6}/L_{1,2,5,6}$ (nm/nm)	600/60
$W_{3,7}/L_{3,7}$ (nm/nm)	200/60
$W_4/L_4$ (nm/nm)	250/140
$W_8/L_8$ (nm/nm)	200/60
$W_9/L_9$ ($\mathsf{\mu }$m/nm)	1/60
$V_b$ (V)	0.6
$V_{sp}$ (V)	0.35

summarizes the parameters of the proposed VTC design.

Figure 4 depicts the modulated pulse width signal $V_{pw}$ at different $V_{in}$ values. As shown from the figure, the pulse width varies from 5.21 $\mathsf{\mu }$s at $V_{in}$ = 0 V to 16.66 $\mathsf{\mu }$s at $V_{in}$ = 1 V, resulting in a conversion gain of 11.5 $\mathsf{\mu }$s/V. The VTC has a power consumption of 6.7 $\mathsf{\mu }$W, including the clock buffers, and occupies an area of 0.2 mm${}^2$. The designed VTC has a duty cycle range of 0.15 to 0.5. The duty cycle is calculated as the ratio of the pulse width to the period.

Table 2. Comparison between proposed and prior work.

Work	[30]	[28]	[29]	Proposed
Technique	constant slope	super MOS	starved inverter	sampling circuit
Technology (nm)	65	45	65	65
$V_{dd}$ (V)	1	0.5	1	1.2
$V_{in}$ (V)	0–1	0.1–0.5	0.2–0.35	0–1
Linearity range	high 0–1	low 0.2–0.4	low 0.2–0.35	high 0–1
Gain (ns/V)	0.144	101.43	3.47	11,500
Power ($\mathsf{\mu }$W)	8300	-	-	6.7
MSE (s)	-	-	-	2.04 × ${10}^{-6}$

shows the comparison between the proposed design and prior works. The linearity range across $V_{in}$ is improved by 4× and 5.33× compared to [28,29], respectively.

3. Switched Inductor DC–DC Boost Converter Using the Proposed VTC Circuit

The proposed VTC circuit in Section 2 is employed in the SI boost regulator as a PWM control circuit, as shown in Figure 5a. The SI boost regulator can be utilized in any self-powered electronic devices. In this paper, the proposed SI boost regulator is designed for a wearable biomedical device that is powered by a TEG. The circuit consists of a TEG model, SI boost regulator controlled by two feedback loops: loop 1 of pulse skip modulation (PSM) and loop 2 of PWM. The TEG is modeled as a voltage source $V_{TEG}$ connected in series with a resistor $R_{TEG}$. The SI boost regulator has an inductor L, an nmos transistor $M_n$ controlled by a signal $cl{k}_n$, a pmos active diode $M_p$ controlled by $cl{k}_p$, and a load capacitor $C_L$. Both $cl{k}_n$ and $cl{k}_p$ signals are synchronized to avoid reverse current flow and maintain high power efficiency. When the inductor current $I_{in}$ crosses zero, $M_p$ should turn off. The zero current switching is implemented using a comparator that turns off $M_p$ based on the potential difference between $V_d$ and $V_L$. When $V_L>V_d$, the comparator output $cl{k}_p$ is high. As a result, $M_p$ turns off and operates as a reverse bias diode. The opposite happens when $V_L<V_d$ where $cl{k}_p$ becomes low and $M_p$ acts in forward bias. When $cl{k}_n$ is high, $M_n$ turns on, and $M_p$ is in reverse bias. The current flows from the voltage source to the inductor where the energy is stored. When $cl{k}_n$ is off, $M_n$ turns off, and $M_p$ conducts electrical current so that the inductor discharges the current into the load. Once $V_L$ becomes higher than $V_d$, $M_p$ turns off. The time domain waveform of the SI boost regulator is shown in Figure 5b. The load voltage, given in Equation (3), depends on the duty cycle $D_n$ of $M_n$. As the load current $I_L$ increases, the pulse width of $cl{k}_n$ increases to support the desired $V_L$. A detailed discussion of the SI DC–DC boost converter that generates unregulated output voltage is presented in [11].

The PSM consists of a latched amplifier that compares $V_L$ and $V_{ref}$ and produces $V_{cmp}$ signal. If $V_L>V_{ref}$, $V_{cmp}$ is low, and the PWM control is bypassed. Hence, the pulse is skipped causing $cl{k}_n$ to be logic low. If $V_L<V_{ref}$, $V_{cmp}$ becomes high, and the output pulse signal from PWM $V_{pwn}$ is passed to $M_n$. This way, the circuit boosts the $V_{TEG}$ voltage to a high value of $V_L$. The PWM control loop consists of an error amplifier followed by two parallel VTC circuits. The error amplifier generates a signal $V_{er}$, which is the difference between $V_L$ and $V_{dd}$. The reason behind the selection of $V_{dd}$ instead of $V_{ref}$ is to generate a higher value of $V_{er}$, which is translated into a higher $D_n$ that is capable of supporting a wider load current, unlike the work in [27]. The difference between $V_{ref}$ and $V_L$ in the steady state response is small (less than 10 mV) resulting in a low duty cycle [27] (less than 20%). This limits the current capability, especially at a heavy load range. Hence, in this work, the PWM control circuit is improved by increasing the value of $V_{er}$ and $D_n$. Further excess in the $D_n$ percentage is achieved by ORing the pulse width signals $V_{pw1}$ and $V_{pw2}$ generated by two VTC circuits based on the $V_{er}$ value. This is implemented by delaying the clock signal of the VTC 2. VTC 1 is fed by $V_{clk1}$, and VTC 2 is fed by $V_{clk2}$, which is a delayed signal of the former. As a consequence, $V_{pw2}$ will always be behind $V_{pw1}$, and by ORing the two signals, the total pulse width of $V_{pwn}$ is increased. The amount of the clock delay depends on the load current value that the SI boost regulator requires. Figure 5c shows the output waveform of the PWM and PSM.

$$V_L=\frac{V_{TEG}}{1-D_n}$$

(3)

4. Simulation and Analysis in 65 nm CMOS Technology

The SI boost regulator is implemented and simulated in 65 nm CMOS technology node. The TEG has been characterized to harvest the energy from the temperature difference between the human body and ambient [31]. Based on the power and voltage level obtained from the TEG characterization, the TEG is emulated using DC power supply with $V_{TEG}$ = 50 mV and $R_{TEG}$ = 7 $\Omega$. The SI boost regulator generates a $V_L$ of 0.6 V, and 0.8 V for $I_L$ range from 10 $\mathsf{\mu }$A to 50 $\mathsf{\mu }$A. The inductor value is chosen to be 47 $\mathsf{\mu }$H and $C_L$ is equal to 50 nF with the clock frequency =30 kHz. The size of $M_n$ and $M_p$ is $\frac{5\mathrm{mm}}{60\mathrm{nm}}$. Figure 6 shows the simulation results of the boost regulator when $V_L<V_{ref}$ during the transient response. In this case, $V_{comp}$ = 1.2 V and $V_{pw1}$ and $V_{pw2}$ have the maximum pulse width value resulting in a maximum $D_n$ of 70%. As $V_L$ increases, $V_{er}$ decreases gradually, and so the pulse width of the $V_{pw1}$ and $V_{pw2}$. Once $V_L$ reaches $V_{ref}$, as shown in Figure 7, $V_{cmp}$ switches between 0 V and 1.2 V. When $V_{cmp}$ = 0 V, $cl{k}_n$ = 0 V whereas, when $V_{cmp}$ = 1.2 V, $cl{k}_n$ is generated with a lower pulse width of $V_{pw1}$ and $V_{pw2}$ because $V_{er}$ is reduced compared to the $V_{er}$ value in the transient response.

Figure 8 and Figure 9 show the transient response of the SI boost regulator when $I_L$ changes switches between 10 $\mathsf{\mu }$A and 50 $\mathsf{\mu }$A at $V_L$ of 0.6 V and 0.8 V, respectively. As shown in Figure 8, the $D_n$ fluctuates between 0% and 66%.

Figure 10 shows the power efficiency of the SI boost converter at $V_L$ of 0.6 V and 0.8 V for $I_L$ range of 10 $\mathsf{\mu }$A to 50 $\mathsf{\mu }$A. The power efficiency achieves the peak of 60.9% at load power of 50 $\mathsf{\mu }$W. Figure 11 depicts the power efficiency of the SI boost regulator versus $V_{TEG}$ at $I_L$ = 10 $\mathsf{\mu }$A. At $V_L$ = 0.6 V, the power efficiency increases with $V_{TEG}$ because the switching of $cl{k}_n$ decreases. AT $V_{TEG}$ = 65 mV, the power efficiency is 62% at $V_L$ = 0.6 V.

Figure 12 shows the load regulation of SI boost regulator at $V_{TEG}$ = 65 mV. The load regulations at $V_L$ = 0.8 V and $V_L$ = 0.6 V are 110 $\mathsf{\mu }$V/$\mathsf{\mu }$A and 340 $\mathsf{\mu }$V/$\mathsf{\mu }$A, respectively. The line regulation of the SI boost regulator is shown in Figure 13 and reports values of 486 $\mathsf{\mu }$V/mV at $V_L$ = 0.8 V and 593 $\mathsf{\mu }$V/mV at $V_L$ = 0.6 V.

The proposed single stage SI boost regulator is compared with the conventional two cascaded regulators designed and characterized in our previous work [19]. The two cascaded stage is formed of SI boost converter followed by either SC or LDO regulator as shown in Figure 14.

Table 3. Comparison between single and two stages PMU.

Topology	SI + SC	SI + LDO	SI Regulator *
Technology (nm)	65	65	65
$V_{TEG}$ (mV)	50–65	50–65	50
$V_L$ (V)	0.6–0.8	0.6–0.8	0.6–0.8
Voltage ripple (mV)	35	12	25
Efficiency (%) @ $I_L$ = 10 $\mathsf{\mu }$A $V_L$ = 0.6 V	10	9	27
Efficiency (%) @ $I_L$ = 50 $\mathsf{\mu }$A $V_L$ = 0.6 V	45	48	60.9
Area (mm${}^2$)	0.531	0.0717	0.055

* simulation.

shows the comparison with our prior work in 65 nm CMOS technology node. The proposed SI boost regulator achieves higher power efficiency of 60.9% at $I_L$ = 50 $\mathsf{\mu }$A and smallest area of 0.055 mm${}^2$ excluding the off-chip inductor.

5. Conclusions

A switched inductor DC–DC boost regulator is presented for thermoelectric applications. The regulator is controlled by a voltage-to-time converter that converts the difference between load and supply voltage into modulated pulse width signal. This signal controls the drive switches of the regulator. Once the desired load voltage is achieved, the modulated pulse width signal is skipped to maintain the voltage regulation. The VTC achieves high linearity with a low mean square error of 2.04 × ${10}^{-6}$ s. The switched inductor boost regulated is designed in 65 nm CMOS technology. It has a TEG input voltage of 50 mV to support two load voltages of 0.6 V and 0.8 V. The regulator achieves the peak efficiency of 54% at 8 $\mathsf{\mu }$W load power. Compared to two stages PMU design that consists of switched inductor converter followed by a switched capacitor regulator switched, it achieves smaller area by 9.6× and higher power efficiency by 4.7×.