A Resistor-Network Model of Dickson Charge Pump Using Steady-State Analysis

Abstract

This paper presents a new average behavioral model, named a resistor-network (RN) model, that accurately predicts the electrical characteristics of the Dickson charge pump (DCP) circuit in the slow-switching limit and the fast-switching limit regions based on steady-state analysis. The RN model describes the steady-state behavior of a single-stage DCP using a network of resistors, which can then be cascaded to model N-stage DCP, taking into account the top- and bottom-plate parasitic capacitances. The RN model provides a comprehensive insight into various design parameters of the DCP, including the input/output current, output voltage, load characteristics, losses caused by parasitics, and power efficiency. Simulation results show that the proposed RN model accurately predicts the output voltage and power efficiency of the DCP over a wide range of switching frequencies, from 0.1 Hz to 1 GHz, with an error of less than 2% at the maximum power efficiency. The RN model provides designers with a simple and effective model to design DCP quickly and efficiently for a broad spectrum of applications, including energy harvesting and flash memory applications.

1. Introduction

Dickson charge pump (DCP) circuits are widely used to boost an input DC voltage and support a high-voltage conversion ratio (VCR) for various applications, such as flash memory [1] and energy harvesting systems [2,3]. Unlike inductor-based boost converters [4,5], DCP can be integrated on-chip since it consists of switches and capacitors, as shown in Figure 1. The output voltage of N-stage DCP is illustrated in Equation (1) [6]:

$$V_o=V_{in}+N{V}_{\mathsf{\Phi }}-N{I}_L{R}_{out},$$

(1)

where $R_{out}$ is the output resistance of the DCP, $V_{in}$ is the input DC voltage, N is the number of stages which is equal to the number of fly capacitors (C), $I_L$ is the load current, and $V_{\varphi }$ is the high-voltage level of the clock, which typically has a voltage amplitude of $V_{in}$. A DCP circuit operates in two regions, slow-switching limit (SSL) or fast-switching limit (FSL). SSL occurs when the switching frequency, $f_s$, is low, causing the amount of charge transferred by the capacitors to dominate the power losses of the DCP. In contrast, FSL occurs when $f_s$ is high, causing the switch ON-resistance to prevent the capacitors from completely transferring their charge each period, and thus dominating the power losses of the DCP [7].

Various models are reported in the literature that describe the behavior of the DCP in the SSL and FSL regions, [8,9,10,11,12,13], including the transformer model [9,11,12,14,15,16], the RC model [10,17,18,19], and the discrete-time model [13,20,21]. Figure 2a shows the transformer model, where G is the conductance that represents the losses from the top and bottom parasitic capacitances, (N + 1) is the VCR of the DCP at no-load, $R_{pmp}$ is the output resistance which represents the conduction and the charge transfer losses of the DCP, and $C_{pmp}$ is the self-capacitance of the DCP [11,14,15,16]. The transformer model can predict the electrical characteristics of the DCP, including input/output current and output voltage at low- and mid-frequency ranges [15,16]. However, the transformer model has multiple drawbacks; first, it fails to predict the behavior of the DCP at high frequencies due to inaccurate modeling of the losses caused by the bottom-plate parasitic capacitances. To explain, the value of G becomes large at high frequencies and, thus, the resistance ($1/G$) becomes low, which accurately predicts larger losses at high frequencies. However, as shown in Figure 2a, the model predicts that the VCR of the DCP remains (N + 1) at high frequencies, which is not true since the VCR starts to decrease due to large losses caused by the parasitics, eventually becoming unity. Second, the transformer model assumes the clock voltage level is equal to the input voltage level, lumped at the input terminal, $V_{in}$. Hence, the model does not support a different clock voltage level than the input voltage level. Further, implementing a feedback loop using the transformer model is not a straightforward task since the clock port does not exist in the model. Third, the transformer model does not provide an insight into the behavior of a single-stage DCP but rather models the overall N-stage DCP.

Figure 2b shows the RC model, where $V_m=1+[N/(1+a_1)]V_{in}$, $C_{pmp}=(1+a_1)C{f}_s/3$, $R_{pmp}=T/\left[C(1+a_1)\right]$, and $a_1$ is the top parasitic capacitance ratio [17]. The RC model is originally designed to study the DCP dynamics, including rise time, and the effects of the parasitic capacitances on the output voltage and the load characteristics [22,23]. The RC model can only be used for the low-frequency range since the relationship between $R_{pmp}$ and $f_s$ takes a different approach at high frequencies, due to the effects of ON-resistances of the switches in the DCP. Moreover, the RC model cannot be used for maximum power transfer estimations since it only models the output side of the DCP. Finally, the voltage ($V_m$) is modeled as a dependent voltage source and, thus, the RC model cannot be utilized to model a single-stage DCP but rather models the overall N-stage DCP [24].

On the other hand, the discrete-time model can accurately predict the output voltage of the DCP by modeling it in the z-domain [13,20,21]. The discrete-time model is commonly used for closed-loop regulation, system stability, and feedback control, which can be optimally designed and simulated in a shorter time than the actual switching circuit. However, the transfer function in the z-domain becomes complex as the number of stages in the DCP increases. Additionally, it does not take into account the effects of switches’ internal resistances. In other words, it reflects the behavior of DCP accurately in the low-frequency range.

In this paper, we present a new and simple resistor-network ($RN$) average behavioral model that accurately predicts the electrical characteristics of the DCP, including the input/output current, output voltage, load characteristics, losses caused by the top- and bottom-plate capacitances, and power efficiency. The proposed RN model inherits power conversion properties, as in the transformer model, and exhibits an accurate behavior in the transient and steady-state response, as in the RC model. Unlike the reported models, the RN model describes the behavior of a single-stage DCP and can be generalized to N-stage DCP. The RN model provides a comprehensive insight into various design parameters of the DCP, which will be useful for a broad spectrum of applications.

The following points summarize the novelty of the proposed RN model compared to the reported models in the literature:

• Unlike the reported models, the RN model can describe the electrical characteristics of the DCP over the whole frequency range in the SSL and the FSL regions;
• Unlike the reported models, the proposed model provides access to clock levels, switching frequency, and internal nodes between charge pump stages by modeling each stage individually and then cascading them to model N-stage DCP. Thus, the proposed model assists with studying the voltages and currents for each stage as well as the losses caused by the parasitic capacitances. Further, the model helps with exploring the impact of the feedback network on the behavior of the DCP, including stage modulation for maximum power transfer, and pulse frequency modulation;
• Since the proposed model uses a linear resistive network, the computation speed is inevitably enhanced without extra complications;
• The proposed model highlights the effects of both top- and bottom-plate parasitic capacitances and how they impact the power performance and the maximum power transfer of the DCP over the entire frequency range.

The remainder of the paper is organized as follows. Section 2 demonstrates the RN model derivations with a detailed analysis of the effects of switch ON-resistance and parasitic capacitances. Simulation results are presented in Section 3 to validate the RN model. Finally, Section 4 concludes the paper.

2. RN Model Derivation and Analysis

2.1. Single-Stage DCP Model Derivation

A single-stage DCP can be represented as a switching circuit, as in Figure 3, which consists of four switches with a fixed ON-resistance ($R_{on}$) and a fly capacitor (C), where the nodes $V_1$, $V_2$, $V_3$, and $V_4$ reflect the input, output, and the clock high- and low-voltage levels, respectively.

Before modeling the DCP, it is essential to understand that the proposed model assumes the input variations are very slow compared to $f_s$, the duty cycle of the clock is 50%, and all components (such as $R_{on}$) in DCP are roughly fixed. We start modeling the DCP by analyzing a single-stage DCP, which can be replicated to model N-stage DCP. Figure 3 shows a single-stage DCP, which indicates the direction of the input and output currents.

To better analyze the DCP, Figure 4 shows a generic single-stage DCP. The average current, $\overline{I_1}$, that flows through the voltage source ($V_1$) equals the total charge transferred to the fly capacitor, C, divided by the period, T, as shown in Equation (2a), and Equation (2b):

$$\overline{I_1}={\displaystyle \frac{Q_n-Q_{(n-0.5)}}{T}}={\displaystyle \frac{C(V_1-V_4)-C(V_2-V_3)}{T}},$$

(2a)

$$\overline{I_1}={\displaystyle \frac{C}{T}}(V_1-V_2+V_3-V_4).$$

(2b)

During ${\mathsf{\Phi }}_1$, both $V_1$ and $V_4$ are in series; thus:

$$\begin{array}{ll}\overline{I_4}& =-\overline{I_1}=-{\displaystyle \frac{C(V_1-V_4)-C(V_2-V_3)}{T}}\\ & ={\displaystyle \frac{C}{T}}(-V_1+V_2-V_3+V_4).\end{array}$$

(3)

During ${\mathsf{\Phi }}_2$, $V_2$ and $V_3$ are in series; thus:

$$\begin{array}{ll}\overline{I_2}& =-\overline{I_3}=-{\displaystyle \frac{C(V_2-V_3)-C(V_1-V_4)}{T}}\\ & ={\displaystyle \frac{C}{T}}(V_1-V_2+V_3-V_4).\end{array}$$

(4)

$\overline{I_1}$ can be rewritten as a function of the terminal-to-terminal potential differences, such that:

$$\begin{array}{cc}\hfill \overline{I_1}& \hfill ={\displaystyle \frac{V_1-V_2}{T/C}}+{\displaystyle \frac{V_1-V_3}{-T/C}}+{\displaystyle \frac{V_1-V_4}{T/C}}\hfill \\ \hfill & \hfill ={\displaystyle \frac{V_1-V_2}{R}}+{\displaystyle \frac{V_1-V_3}{-R}}+{\displaystyle \frac{V_1-V_4}{R}}.\hfill \end{array}$$

(5)

The term ($T/C$) is defined as the equivalent switching resistance, R, which represents the energy loss that occurs every charge cycle, as shown in Equation (6):

$$R={\displaystyle \frac{T}{C}}.$$

(6)

$\overline{I_2}$, $\overline{I_3}$, and $\overline{I_4}$ can be analyzed similarly, as shown in Equations (7)–(9), respectively:

$$\overline{I_2}={\displaystyle \frac{V_2-V_1}{R}}+{\displaystyle \frac{V_2-V_4}{-R}}+{\displaystyle \frac{V_2-V_3}{R}}=-\overline{I_1},$$

(7)

$$\overline{I_3}={\displaystyle \frac{V_3-V_1}{-R}}+{\displaystyle \frac{V_3-V_2}{R}}+{\displaystyle \frac{V_3-V_4}{R}},$$

(8)

$$\overline{I_4}={\displaystyle \frac{V_4-V_1}{R}}+{\displaystyle \frac{V_4-V_3}{R}}+{\displaystyle \frac{V_4-V_2}{-R}}=-\overline{I_3}.$$

(9)

2.2. Proposed RN Model

Figure 5 presents the proposed RN model for a single-stage DCP, which consists of linear resistors connected between each terminal in the DCP according to Equations (5) and (7)–(9). All the resistances in Figure 5 are essential to describe the behavior of the DCP operation. The RN model in Figure 5 reveals key information regarding the behavior of a single-stage DCP. Namely, the resistor network, including the negative and positive resistances, entails two properties; voltage gain and power conversion. Furthermore, the RN model is symmetrical between the input and the output; however, the connection of input voltage sources on the left side in the actual circuit forces the power flow in a uni-directional path (from left to right). In addition, the RN model in Figure 5 describes the switching behavior of the DCP during SSL, when $f_s$ is low. Moreover, the equivalent output resistance seen between nodes 2 and 4 when $V_1$ and $V_3$ are zero is equal to R, which agrees with the equivalent switching resistance of a single-stage DCP shown in Equation (6). The resistor network in Figure 5 can be replicated N times in series to model N-stage DCP. As will be shown in Section 3, the RN model can be simulated using SPICE to characterize N-stage DCP, which will help researchers study various parameters of the DCP in a fast and accurate manner. The RN model in Figure 5 does not yet account for the switch ON-resistance and the parasitic capacitances and only accounts for the switching resistance of the DCP. As will be seen in the following subsections, when accounting for various parasitics, the RN model in Figure 5 stays the same; however, the value of R in the resistor network will be different to account for those parasitics. Note that there might be different circuit interpretations of Equations (5) and (7)–(9). However, we chose the circuit interpretation in Figure 5 for simplicity.

There is a key difference between the actual voltage and currents in the DCP circuit, as in Figure 3, compared to the calculated voltage and currents in the RN model, as in Figure 5. The voltage node in the DCP circuit alternates between two levels due to the charging and discharging of the flying capacitors. However, the voltage level estimated by the RN model is the average voltage of two consecutive nodes in the switching DCP. In contrast, the current estimated by the model at a certain time ($t_0$) represents the average value of the corresponding current in the switching DCP during a time interval of (T) around $t_0$.

Comparing the circuit in Figure 3 to the model in Figure 5, we have $V_1=V_{in},$$V_3=V_{\mathsf{\Phi }},V_2=V_o$, and $V_4=0$, while $I_1=I_{in},I_2=-I_{out},$ and $I_3=I_{\mathsf{\Phi }}$. To calculate the power dissipation for a single-stage DCP, we first calculate the average input current based on Figure 3. The average input current ($\overline{I_{in}}$),

$$\overline{I_{in}}=\overline{I_{out}}=\overline{I_1}=-\overline{I_2}={\displaystyle \frac{1}{R}}(V_{in}-V_o+V_{\mathsf{\Phi }}).$$

Since ($V_4=0$), the output voltage is described as in Equation (10):

$$V_o=V_2=V_{in}+V_{\mathsf{\Phi }}-\overline{I_{out}}R.$$

(10)

The term ($V_{in}+V_{\mathsf{\Phi }}$) represents the maximum available output voltage when the output current is zero (at the no-load condition).

The voltage ripple is considered an essential part of the output voltage. The ripple at high-frequency ranges $(f_s>>{\left(R_L{C}_L\right)}^{-1})$ is negligible compared to the output voltage level. In contrast, at low- to mid-frequencies, the ripple can be derived by analyzing the last stage of the DCP at steady-state. Hence, the average charge delivered to the output capacitor, $C_L$, equals to the average current flows through the load resistance, $R_L$:

$$\overline{I_L}=C{\displaystyle \frac{\Delta V_o}{T}}={\displaystyle \frac{V_o}{R_L}}.$$

Thus,

$$\Delta V_o={\displaystyle \frac{V_o}{f_s{R}_L{C}_L}}.$$

(11)

The average power dissipated, $P_D$, due to charge transfer losses in a single-stage DCP is shown in Equation (12):

$$\begin{array}{ll}{P}_D& =V_1\overline{I_1}+V_2\overline{I_2}+V_3\overline{I_3}+V_4\overline{I_4}\\ & =V_1\overline{I_1}+(V_1+V_3+\overline{I_2}R)\overline{I_2}+V_3\overline{I_3}+0\\ & ={\overline{I_2}}^{2}R={\overline{I_{out}}}^{2}R,\end{array}$$

(12)

where $P_D$ can be minimized by having a large fly capacitor or by increasing the switching frequency. However, as the switching frequency increases, the effects of $R_{on}$ become dominant, as explained in the following subsection, and the resistance/frequency dependency takes a different approach.

2.3. The Effect of Switch ON-Resistance ($R_{on}$)

The analysis in the previous subsection is valid during low-frequency ranges, i.e., the time constant of the charging/discharging paths, including $R_{on}$; ($\tau \propto R_{on}C$) is very small compared to the half-cycle ($T/2$). Such preconditions guarantee that the fly capacitor will charge to ($V_H=V_1-V_4$) and discharge to ($V_L=V_2-V_3$). However, when $f_s$ increases, the time constant becomes comparable to the half-cycle and, thus, the DCP operates in the FSL. Therefore, the model and Equation (6) need to be modified to capture the effect of $R_{on}$, which can be achieved by using the same RN model in Figure 5 but deriving a different value for R. During SSL and based on Appendix A, which provides details on the steady-state analysis of a single-pole system, the fly capacitor will charge to ($V_{max}$) and discharge to ($V_{min}$), such that:

$$V_{max}-V_{min}=(V_H-V_L)tanh\left({\displaystyle \frac{T}{4\tau }}\right).$$

The average charge transfer to C is:

$$\begin{array}{ll}\overline{I_1}& ={\displaystyle \frac{C(V_{max}-V_{min})}{T}}={\displaystyle \frac{Ctanh\left({\displaystyle \frac{T}{4\tau }}\right)(V_H-V_L)}{T}}\\ & ={\displaystyle \frac{C}{T}}tanh\left({\displaystyle \frac{T}{4\tau }}\right)(V_1-V_4-V_2+V_3).\end{array}$$

Thereby, the switching resistance, including the effect of $R_{on}$, is expressed in Equation (13):

$$R={\displaystyle \frac{1}{C{f}_s}}coth\left({\displaystyle \frac{1}{4\tau f_s}}\right),$$

(13)

where $\tau =2R_{on}C$ is the time constant of the charging/discharging paths. If $f_s$ is low, then the power loss is due to the charge transfer loss that happens due to the abrupt transition of the capacitors’ voltage levels [25], and the resistance curve is above the $SSL$ asymptote line. Hence, as shown in Figure 6, the switching resistance is:

$$R={\displaystyle \frac{1}{C{f}_s}}coth\left({\displaystyle \frac{1}{4\tau f_s}}\right)\approx {\displaystyle \frac{1}{C{f}_s}}.$$

In contrast, when $f_s$ is high, the power loss is due to the conduction losses in $R_{on}$, and the resistance curve is above the $FSL$ asymptote line. Thus:

$$R={\displaystyle \frac{T}{C}}coth\left({\displaystyle \frac{1}{4\tau f_s}}\right)\approx {\displaystyle \frac{T}{C}}\times 4\tau f_s={\displaystyle \frac{4\tau }{C}}.$$

(14)

The corner frequency, $f_c$, between the $SSL$ and $FSL$ frequencies is defined as the frequency at which the SSL and FSL asymptotes intersect, as demonstrated in Figure 6; thus:

$$f_c={\displaystyle \frac{1}{4\tau }}.$$

(15)

Finally, the resistance estimated in Equation (13) describes the losses when the fly capacitor is charging and discharging through an ideal source, with symmetrical charge/discharge paths. In the first stage of the DCP, the charging path time constant is ($2R_{on}C$), while the discharging path is ($1.5R_{on}C$). For intermediate stages, both the charging time constant (${\tau }_c$) and discharging time constant (${\tau }_d$) are ($1.5R_{on}C$), and for the last stage, the time constants are ($1.5R_{on}C$) and ($2R_{on}C{C}_L/(C+C_L)$). In such a case, and as shown in Appendix B, the equivalent resistance of the DCP when considering non-symmetrical charging/discharging paths is:

$$R={\displaystyle \frac{\left(1-e^{-{\displaystyle \frac{T}{2{\tau }_c}}}{e}^{-{\displaystyle \frac{T}{2{\tau }_d}}}\right)}{1-\left(e^{-{\displaystyle \frac{T}{2{\tau }_c}}}+e^{-{\displaystyle \frac{T}{2{\tau }_d}}}+\right)+e^{-{\displaystyle \frac{T}{2{\tau }_c}}}{e}^{-{\displaystyle \frac{T}{2{\tau }_d}}}}}\times {\displaystyle \frac{T}{C}},$$

(16)

where Equation (16) shows that the resistance in the SSL range stays the same ($T/C$). This is expected since the resistance value of the charging and discharging paths does not impact the amount of losses due to charge sharing. In contrast, Equation (16) shows that the resistance in the FSL range is:

$$R\approx 4\left({\displaystyle \frac{{\tau }_c+{\tau }_d}{2C}}\right)={\displaystyle \frac{4{\tau }_{avg}}{C}}=2R_T,$$

(17)

where $R_T$ is the sum of all $R_{on}$ in a single DCP stage (i.e., $R_T$ = 4$R_{on}$), which is consistent with the result presented in [26]. In this case, we can approximate the effective time constant to be the average of the charging and discharging time constants. For instance, ignoring the series resistance of the input source ($R_s$), in the first stage, the effective time constant is $0.5(2R_{on}C+1.5R_{on}C)=1.75R_{on}C$. Equation (16) reveals that the capacitance is not scaled to ($C/2$). Intuitively, even though the capacitance value is reduced by half, the equivalent resistance is doubled. However, the ripple on the fly capacitor shrinks with the same factor due to capacitance–voltage division. Thus, the charging and discharging from and into a capacitive load does not impact the equivalent resistance of the switching circuit unit in both SSL and FSL ranges. However, there is some error around the corner frequency which depends on the ${\tau }_d/{\tau }_c$.

For simplicity, Equation (13) can be still utilized, instead of Equation (16), by setting the time constant to be the effective time constant ${\tau }_{avg}$, and keeping R and C the same. For example, when (${\tau }_d=0.75{\tau }_c$), such approximation can yield a maximum error of 0.4% in resistance value, as shown in Figure 7. Therefore, the effect of $R_{on}$ can be captured in the RN model by using the same resistor network in Figure 5, but using the equation of R in Equation (13).

2.4. The Effect of Parasitic Capacitance ($C_p$)

In this subsection, we will modify the RN model to include the effect of the parasitic capacitances and, thus, capture the behavior of the DCP during SSL and mid-frequency in the FSL. Again, the same RN model in Figure 5 will be used while deriving different values for the resistors. We will denote this model as the RN model with parasitic, or the RN-P model.

As $f_s$ increases, parasitic capacitors dominate the power losses in the DCP. As shown in Figure 8, two main parasitic capacitors, $C_{p_1}$ and $C_{p_2}$, exist in a single-stage DCP. To include the impacts of $C_{p_1}$ and $C_{p_2}$, we perform a similar analysis in Section 2.1 on the DCP shown in Figure 8. We define $C_{p1}$ and $C_{p2}$ as a percentage of the fly capacitor, C, such that $C_{p_1}$=$a_{1}C$ and $C_{p_2}$=$a_{2}C$, where $a_1$ and $a_2$ are less than 1 and they depend on the CMOS technology node, the area of the fly capacitor, the metal layers used, the type of the capacitor (MIM, MOS, and MOM), and the layout design. To estimate $a_1$ and $a_2$, a post-layout simulation can be used to extract the parasitic at each node. Experimentally, we can estimate the average value of $a_1$ and $a_2$ by measuring the input current and the output voltage at zero-load current, as will be shown in the next subsections.

During ${\mathsf{\Phi }}_1$, the charge rate transferred through $S_1$ is:

$$\begin{array}{ll}\overline{I_1}& ={\displaystyle \frac{C}{T}}((V_1-V_4)-(V_2-V_3))+{\displaystyle \frac{C_{p_1}}{T}}(V_1-V_2)\\ & ={\displaystyle \frac{C}{T}}((1+a_1)V_1-(1+a_1)V_2+V_3-V_4)\\ & ={\displaystyle \frac{C}{T}}((1+a_1)(V_1-V_2)-(V_1-V_3)+(V_1-V_4)).\end{array}$$

(18)

Similarly, during ${\mathsf{\Phi }}_2$, the charge rate transferred through $S_3$ is:

$$\begin{array}{ll}\overline{I_3}& ={\displaystyle \frac{C}{T}}((V_3-V_2)-(V_1-V_4))+{\displaystyle \frac{C_{p_2}}{T}}{V}_3\\ & ={\displaystyle \frac{C}{T}}(-V_1-V_2+(1+a_2)V_3+V_4).\end{array}$$

(19)

Based on Equations (18) and (19), Figure 9 shows the RN-P model with amended $R_{12}$ and $R_{34}$, which includes the effect of $C_{p1}$ and $C_{p2}$, respectively, such that:

$$\begin{array}{cc}\hfill R_{12}={\displaystyle \frac{R}{1+a_1}}& \hfill =R\left|\right|\left({\displaystyle \frac{R}{a_1}}\right)\hfill \\ \hfill R_{34}={\displaystyle \frac{R}{1+a_2}}& \hfill =R\left|\right|\left({\displaystyle \frac{R}{a_2}}\right),\hfill \end{array}$$

(20)

where R is the same as was shown in Equation (13). As depicted in Figure 9, the effect of the $C_{p1}$ and $C_{p2}$ is reflected on $R_{12}$ and $R_{34}$, respectively. Since $R_{12}$ and $R_{34}$ can be each seen as two parallel resistors, the RN-P model can be drawn as in Figure 10, which reveals key information regarding the effect of $C_{p1}$ and $C_{p2}$. As depicted in Figure 10, as $f_s$ increases, the output voltage due to $C_{p1}$ decreases. However, since the term ($R/a_1$) decreases, the total output resistance decreases. In contrast, as $f_s$ increases, the effect of $C_{p2}$ increases the power losses and does not affect the output voltage or the output current of the DCP. The impact of $C_{p1}$ and $C_{p2}$ in Figure 10 can be intuitively confirmed using Figure 8 as follows. During ${\mathsf{\Phi }}_1$, $C_{p1}$ is charged to $V_1$, while in ${\mathsf{\Phi }}_2$, $C_{p1}$ is discharged to the output load, which confirms the direct contribution of $C_{p1}$ on the output voltage. In contrast, during ${\mathsf{\Phi }}_2$, $C_{p2}$ is charged to $V_3$, while in ${\mathsf{\Phi }}_1$, $C_{p2}$ is discharged through $V_4$, which is ground, and thus $C_{p2}$ does not impact the output voltage but rather the power losses. Note that the new represented form of the RN-P model in Figure 9 and Figure 10 makes the analysis of power loss, output resistance, and voltage level a straightforward task.

Based on Figure 10, the output voltage under zero load condition, ${\overline{I}}_L=0A⟶{\overline{I}}_C={\overline{I}}_{f1}$:

$$\begin{array}{l}{V}_o(I_L=0)=V_{in}+V_{\mathsf{\Phi }}-I_{C}R\\ =V_{in}+V_{\mathsf{\Phi }}-\left({\displaystyle \frac{V_o-V_{in}}{R/a_1}}\right)R,\end{array}$$

$$V_o(I_L=0)=V_{in}+{\displaystyle \frac{V_{\mathsf{\Phi }}}{1+a_1}}.$$

(21)

The equivalent output resistance, $R_{out}$, can be derived from the load characteristics equation:

$$\begin{array}{c}{V}_o=V_{in}+V_{\mathsf{\Phi }}-\left(I_L+{\displaystyle \frac{V_o-V_{in}}{R/a_1}}\right)R\hfill \\ =V_{in}+V_{\mathsf{\Phi }}-a_1\left(V_o-V_{in}\right)+I_{L}R\hfill \\ \hfill \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}⟹V_o=V_{in}+{\displaystyle \frac{V_{\mathsf{\Phi }}}{1+a_1}}-{\displaystyle \frac{R}{1+a_1}}{I}_L,\end{array}$$

$$R_{out}=R_{12}={\displaystyle \frac{R}{1+a_1}}.$$

(22)

The feedback current $I_{f1}$ can be calculated as:

$$\begin{array}{r}{I}_{f_1}={\displaystyle \frac{V_o-V_{in}}{R/a_1}}\\ ={\displaystyle \frac{V_{in}+{\displaystyle \frac{V_{\mathsf{\Phi }}}{1+a_1}}-{\displaystyle \frac{R}{1+a_1}}{I}_L-V_{in}}{R/a_1}},\hfill \end{array}$$

$$⟹I_{f_1}={\displaystyle \frac{a_1}{1+a_1}}\left({\displaystyle \frac{V_{\mathsf{\Phi }}}{R}}-I_L\right).$$

(23)

The feedback current $I_{f2}$ can be calculated as:

$$I_{f_2}={\displaystyle \frac{a_2{V}_{\mathsf{\Phi }}}{R}}.$$

(24)

The charge pump current $I_C$, at any $I_L$, can be calculated as:

$$\begin{array}{c}\hfill I_C=I_L+{\displaystyle \frac{a_1}{1+a_1}}\left({\displaystyle \frac{V_{\mathsf{\Phi }}}{R}}-I_L\right)\\ \hfill ={\displaystyle \frac{a_1}{1+a_1}}\left({\displaystyle \frac{V_{\mathsf{\Phi }}}{R}}+{\displaystyle \frac{I_L}{a_1}}\right).\end{array}$$

(25)

The power losses are equal to:

$$P_D={\displaystyle \frac{I_{f_1}^{2}R}{a_1}}+{(I_L+I_{f_1})}^{2}R+{\displaystyle \frac{a_2{V}_{\mathsf{\Phi }}^2}{R}}.$$

(26)

Figure 11 shows the RN-P model, as in Figure 10, when cascaded N times to model the behavior of a N-stage DCP. As shown in Figure 11, the RN-P model for a single-stage DCP can be extended to N-stage DCP, which helps with having better insight on individual stages. Furthermore, since the RN-P model consists of only resistors, the simulation of DCP will be much faster than the switching DCP circuit, which will help designers optimize their circuits quickly.

Now, the DCP in Figure 11 can be analyzed, where the output voltage at no-load condition, ($I_L=0\mathrm{A}$) is:

$$V_{o1}=V_1+{\displaystyle \frac{V_1}{1+a_1}}=\left(1+{\displaystyle \frac{1}{1+a_1}}\right)V_{in},$$

$$V_{o2}=V_{o1}+{\displaystyle \frac{V_1}{1+a_1}}=\left(1+{\displaystyle \frac{2}{1+a_1}}\right)V_{in}.$$

Thus,

$$V_{oN}=\left(1+{\displaystyle \frac{N}{1+a_1}}\right)V_{in}.$$

(27)

The output resistance of the DCP can be derived as:

$$R_{out}={\displaystyle \frac{NR}{1+a_1}}.$$

(28)

The result in Equations (27) and (28) are consistent with the equations first derived by Dickson ($V_D=0$ volt, $I_{out}=0$ A, and $a_1=C_s/C$) [27] and other work reported in the literature [7,26].

2.5. Maximum Power Transfer Methodologies

In energy harvesting applications, maximum power transfer is essential to maximize the extracted power and deliver the maximum power to the load [28,29,30,31]. The proposed RN model helps with deriving the output resistance of the DCP to achieve maximum power at the load for an input source, $V_s$, with a source resistance $R_s$. Equation (28) does not consider the effect of $R_s$. Thus, the output resistance of the DCP, when including $R_s$, can be expressed as [29]:

$$\begin{array}{cc}\hfill R_{out}& \hfill ={\left({\displaystyle \frac{N+1+a_1}{1+a_1}}\right)}^2\left(R_s\left|\right|{\displaystyle \frac{(1+a_1)R}{(a_1+a_2+a_1{a}_2)N}}\right)+{\displaystyle \frac{NR}{1+a_1}}.\hfill \end{array}$$

(29)

If the load voltage is unregulated, then the optimum DCP resistance associated with maximum power delivered to a distinct N can be expressed as [29]:

$$R=\sqrt{(a_1+a_2+a_1{a}_2)R_s{R}_L},$$

(30)

where ($R_s>0$). The optimum resistance shown in Equation (30) is independent of N since it is defined as the resistance for the maximum power at the load and not the maximum available power delivered from the source. Note that, for $a_1=0,a_2=0$, the input impedance $R_{IN}=\infty$ and $R_{out}=R=T/C$. In this case, as R approaches zero, the power delivered to the load increases since the load voltage increases.

For regulated output voltage, the optimum DCP resistance can be expressed as [29]:

$$\begin{array}{c}\hfill R\approx R_s\left({\displaystyle \frac{N{V}_o(a_1+a_2)}{V_s(N+1)-V_o}}+{\displaystyle \frac{(N+1)\sqrt{V_o(a_1+a_2)(V_s(N+1)-V_o)}}{V_s(N+1)-V_o}}\right),\end{array}$$

(31)

where ($R_s>0$). Equations (30) and (31) reveal key information regarding maximum power transfer methodologies in the DCP circuit. When the output voltage is not regulated, the optimum resistance of the DCP is independent of N, as in Equation (30), and thus, stage modulation can be used to change N such that the input voltage of the DCP is equal to $V_s/2$. For regulated output voltage, the optimum resistance of the DCP is a function of N, as in Equation (31). Therefore, both R and N need to be changed iteratively until reaching the optimum set of $N_{opt},R_{opt}$.

2.6. Generalization of RN Model

The RN-P model demonstrated in Figure 9 provides an accurate description of DCP at low frequencies (SSL) and the beginning of FSL, which is helpful for describing DCP in most applications. However, when the frequency becomes very high in FSL, the RN-P model does not capture the increase of the output resistance and the switching losses. Therefore, to have a complete insight into the behavior of DCP at the whole range of $f_s$, an exact analysis of the RC circuit should be performed to understand the effects of parasitic losses. Thus, we denote this general model as the RN-G model. All details about the RN-G model analysis are included in Appendix C. The final RN-G model is shown in Figure 12, and the derivations are summarized in the following equations:

• The circuit in Figure 8 has two distinct real poles:

  $${\tau }_1\approx \left(2+{\displaystyle \frac{a_1+a_2}{2}}\right)R_{on}C,{\tau }_2\approx \left({\displaystyle \frac{a_1+a_2}{2}}\right)R_{on}C.$$

  (32)
  Note that ${\tau }_2$ is much smaller than ${\tau }_1$, and therefore, the second corner frequency, $f_{c2}$, is much larger than the first corner frequency, $f_{c1}$;
• The resistor between terminals 1 and 2, $R_{12}$, can be expressed as a combination of two parallel resistors $R_{12,1}$, and $R_{12,2}$:

  $$R_{12}=R_{12,1}\left|\right|R_{12,2}={\displaystyle \frac{1}{G_{12,1}+G_{12,2}}},$$

  (33)

  where:

  $$G_{12,1}={\displaystyle \frac{{\tau }_1-(1+a_2)R_{on}C}{{\tau }_1-{\tau }_2}}{\displaystyle \frac{{\tau }_1}{T{R}_{on}}}tanh\left({\displaystyle \frac{T}{4{\tau }_1}}\right),G_{12,2}={\displaystyle \frac{(1+a_2)R_{on}C-{\tau }_2}{{\tau }_1-{\tau }_2}}{\displaystyle \frac{{\tau }_2}{T{R}_{on}}}tanh\left({\displaystyle \frac{T}{4{\tau }_2}}\right);$$

  (34)
• Similarly, the resistor between terminals 3 and 4, $R_{34}$, is a combination of two parallel resistors ($R_{34,1}$ and $R_{34,2}$):

  $$R_{34}=R_{34,1}\left|\right|R_{34,2}={\displaystyle \frac{1}{G_{34,1}+G_{34,2}}},$$

  (35)

  where:

  $$G_{34,1}={\displaystyle \frac{{\tau }_1-(1+a_1)R_{on}C}{{\tau }_1-{\tau }_2}}{\displaystyle \frac{{\tau }_1}{T{R}_{on}}}tanh\left({\displaystyle \frac{T}{4{\tau }_1}}\right),G_{34,2}={\displaystyle \frac{(1+a_1)R_{on}C-{\tau }_2}{{\tau }_1-{\tau }_2}}{\displaystyle \frac{{\tau }_2}{T{R}_{on}}}tanh\left({\displaystyle \frac{T}{4{\tau }_2}}\right);$$

  (36)
• The other four resistors, denoted as $R_{ch}$ in the RN-G model, can be calculated as:

  $$R_{ch}=R_{14}=R_{23}=-R_{13}=-R_{24}={\displaystyle \frac{1}{G_1+G_2}},$$

  (37)

  where:

  $$G_1={\displaystyle \frac{{\tau }_1}{({\tau }_1-{\tau }_2)}}{\displaystyle \frac{C}{T}}tanh\left({\displaystyle \frac{T}{4{\tau }_1}}\right),G_2={\displaystyle \frac{-{\tau }_2}{({\tau }_1-{\tau }_2)}}{\displaystyle \frac{C}{T}}tanh\left({\displaystyle \frac{T}{4{\tau }_2}}\right).$$

  (38)

At low-frequency ranges in the RN-G model, $G_1+G_2\approx C/T$, $R_{12}=T/\left((1+a_1)C\right)$, and $R_{34}=T/\left((1+a_2)C\right)$, which matches the RN-P model in Figure 10. At high-frequency ranges, $R_{ch}=R_{14}=R_{23}=-R_{13}=-R_{24}=\infty$, and $R_{12}\approx R_{34}\approx 4R_{on}$.

Figure 12 and Figure 13 exhibit the RN-G schematic and summarize the model equivalent characteristics of a single-stage DCP at low-, mid-, and high-frequency ranges, where $R_{12}$, $R_{34}$, and $R_{ch}$ are plotted. The R graph, as in Equation (13), which includes the effect of $R_{on}$, is plotted for reference. At low frequencies, $f<1/4{\tau }_1$, the curve, R, follows the asymptotic lines, $R=1/\left(f_{s}C\right)$, which demonstrates the equivalent resistance of a single-stage DCP with no parasitic effect. However, the curve, R, becomes equal to $8R_{on}$ at high-frequency ranges where the ON-resistance effects are predominant. The curves $R_{12},R_{34},$ and $R_{ch}$ have a second corner frequency at ($1/4{\tau }_2$) due to parasitic effects. At high-frequency ranges, $R_{12}\approx R_{34}\approx 4R_{on}$, and $R_{ch}=R_{14}=R_{32}=-R_{13}=-R_{24}$ increase in proportion to $f^2$.

Finally, the time constants estimated in Equation (32) are based on symmetrical charging/discharging paths and assume a time constant of 2$R_{on}C$. This assumption is not valid for our case of DCP. For instance, the charging path for the intermediate stages includes three resistors and two fly capacitors, as illustrated in Figure 14.

Where the first path ($p_1$) has a time constant:

$${\tau }_1\approx {\displaystyle \frac{3}{2}}{R}_{on}C,$$

(39)

and the second time constant is obtained by shortening the fly capacitors and estimating the poles from the admittance formula. Thus:

$${\tau }_2\approx {\displaystyle \frac{4(a_1+a_2)}{3}}{R}_{on}C.$$

(40)

Similar formulas are valid for the discharging phase of the first stage and the charging phase of the last stage. However, for the first stage, and during the charging phase:

$${\tau }_1\approx \left(2R_{on}+R_s\right)C,{\tau }_2\approx \left({\displaystyle \frac{a_1+a_2}{2}}\right)R_{on}C,$$

(41)

and for the last stage, during the discharging phase:

$${\tau }_1\approx 2R_{on}\left({\displaystyle \frac{C{C}_L}{C+C_L}}\right)\approx 2R_{on}C,{\tau }_2\approx \left({\displaystyle \frac{a_1+a_2}{2}}\right)R_{on}C.$$

(42)

As a final step, we model each stage based on the average values of ${\tau }_1$ and ${\tau }_2$ during the charging and discharging phases.

3. Simulation Results

This section provides simulation results using SPICE in Cadence tool to validate the RN model against an actual switching DCP. Three circuits are designed: (i) an 8-stage switching DCP, as in Figure 1; (ii) an 8-stage cascaded RN-P model, as in Figure 11; (iii) an 8-stage RN-G-based model, as in Figure 12. The default design parameters of the circuits are summarized in

Table 1. Simulation Parameters.

Parameter	Value
N	8
$f_s$	10 MHz
C	50 pF
$C_L$	500 pF
$a_1$	5%
$a_2$	5%
$R_{on}$	500 ${\Omega }$
$R_L$	50 k${\Omega }$
$V_{in}$	1 volt
$Duty$$Cycle$	50%

.

Figure 15 shows the transient simulation of the output voltage for the switching DCP circuit and the RN-G model at different frequencies. Other parameters are set to default, as in Table 1. As depicted in the figure, the proposed model shows excellent transient and steady-state estimations of the output voltage compared to the switching DCP. For example, at 10 MHz, the error is minimum since the switching frequency is in the mid-range, between ($f_{c1}=6.4$ MHz) and ($f_{c2}=256$ MHz). In contrast, there is a slight difference as we cone closer to ($f_{c2}$), where the DCP shows an output voltage of 3.2 V, while the proposed model predicts 3.4 V. At very high frequencies (1 GHz), the charge pump resistor decreases to the minimum, and the output is less than ($V_{in}$) due to the extreme effects of the parasitics.

Figure 16 demonstrates the average steady-state output voltage of the switching DCP circuit, RN-G model, and RN-P model at loads of 100-k${\Omega }$, 50-k${\Omega }$, and 5-k${\Omega }$, and different switching frequencies. As shown in Figure 16, the RN-G model accurately predicts the DCP behavior over the whole range of $f_s$ since it includes the effects of both the $R_{on}$ and the parasitic capacitances. In particular, Figure 16 shows the output voltage using the RN-P model, which accounts for the impact of $R_{on}$ and the parasitic capacitances during SSL and part of the FSL, until $f_{c1}$. The RN-P model accurately predicts the output voltage until $f_{c1}$ only, since the RN-P model does not account for the second pole at $f_{c2}$, and the output resistances, $R_{12}$, in Figure 9 stay at $\tau /c=6R_{on}$ after $f_{c1}$.

Figure 17 shows the simulation of the power efficiency at loads of 100-k${\Omega }$, 50-k${\Omega }$ and 5-k${\Omega }$ for the switching DCP, RN-P model, and RN-G model. As indicated in the figure, the proposed RN-G model predicts the efficiency accurately over the entire range of frequencies, with a $2\%$ error at the maximum efficiency. Moreover, the RN-P model predicts the efficiency accurately until $f_{c1}$. Note that, in practical applications, DCP usually operates at a frequency much less than $f_{c2}$ since the VCR of the DCP degrades substantially and has high losses when $f_s>f_{c2}$. Therefore, the RN-P model could be used to predict the behavior of the DCP for most applications due to the simple design equations compared to the RN-G model. Finally, both the RN-G and RN-P models provide a fast way to estimate the behavior of DCP approximately 170× faster than the switching DCP circuit when both models and the DCP run on the same CAD tool.

The results shown in Figure 16 and Figure 17 indicate that the proposed RN-G model accurately predicts the output voltage and power efficiency of the DCP over the entire frequency range. Unlike the reported models, the RN-G model accurately predicts the drop of the output voltage in Figure 16, as the frequency increases due to the losses caused by the parasitic capacitances, reflected by the increase in $R_{ch}$, as was shown in Figure 13. In particular, the proposed model predicts that the output voltage at 1 GHz becomes equal or less than the input at which the DCP is not operating properly. In contrast, the transformer model inaccurately predicts that the VCR of the DCP remains (N + 1) over the entire frequency range, as was explained in Figure 2a. The RC model describes the DCP circuit for low-frequency ranges, and thus does not capture the losses at higher frequencies.

4. Conclusions

We presented a new and simple RN model that accurately describes the electrical characteristics of the DCP. The proposed RN model inherits power conversion properties, as in the transformer model, and exhibits an accurate behavior in the transient and steady-state response, as in the RC model. Unlike the reported models, the RN model describes the behavior of a single-stage DCP, and can be extended to N-stage DCP. The RN model provides a comprehensive insight on various design parameters of the DCP, such as the input/output current, output voltage, load characteristics, power losses, and power efficiency. The RN model provides designers with a simple and effective model to design DCP in a fast and efficient manner for a broad spectrum of applications.