# Multi-Stacked Superbuck Converter-Based Single-Switch Charger Integrating Cell Voltage Equalizer for Series-Connected Energy Storage Cells

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Proposed Integrated Chargers

#### 2.1. PWM Converters

#### 2.2. Single-Switch Integrated Chargers

_{o1}–C

_{o4}are connected in parallel with energy storage cells B

_{1}–B

_{4}. The string voltage, V

_{st}, is regulated by a constant-voltage (CV) charging scheme, whereas voltages of C

_{o1}–C

_{o4}, V

_{1}–V

_{4}, are automatically equalized even without feedback control, which is detailed in Section 3.

#### 2.3. Benefits and Drawbacks

#### 2.4. Comparison

_{in}is the input voltage, d is the duty cycle, V

_{e}is the equalized cell voltage (V

_{1}= V

_{2}= … = V

_{e}), and n is the number of cells in series; equations for the superbuck-based topology will be mathematically derived in Section 3.

_{e}/V

_{in}decreases. The DCM region of the superbuck topology is larger than that of the buck-boost topologies, though its operational region is nV

_{e}/V

_{in}≤ 1.0. Since the proposed integrated chargers are supposed to operate in DCM, the superbuck topology would be advantageous as long as nV

_{e}/V

_{in}≤ 1.0 is satisfied.

## 3. Operation Analysis

#### 3.1. Voltage Equalization Mechanism

_{1}–C

_{4}, are connected to the switching node generating an ac voltage and hence, the stacked CLD circuits are ac-coupled. Thus, respective CLD circuits, as well as smoothing capacitors and energy storage cells, can be equivalently separated and grounded, as shown in Figure 5. All the CLD circuits and energy storage cells are connected in parallel and are driven by the square-wave voltage generator. This equivalent circuit suggests that a current from the square-wave voltage generator preferentially flows toward the least charged cell(s) with the lowest voltage in the string, and all the cell voltages eventually become uniform as the charging progresses.

#### 3.2. Operation under Voltage-Imbalanced Condition

_{1}, V

_{1}, is the lowest in the string. All circuit elements are assumed ideal. Theoretical operation waveforms and current flow directions in DCM are shown in Figure 6 and Figure 7.

_{1}) (Figure 7a): The switch Q is turned on. All inductors are charged, and their currents increase linearly. The voltage applied to L

_{in}and L

_{i}(i = 1…4), v

_{Lin}and v

_{Li}, in Mode 1 are given by

_{k}is the voltage of B

_{k}and V

_{Ci}is the voltage of C

_{i}that is expressed as

_{Lin}and v

_{Li}are identical.

_{in}and L

_{i}, i

_{Lin}and i

_{Li}, are

_{Lin.DCM}and I

_{Li.DCM}are the initial values of i

_{Lin}and i

_{Li}in Mode 3, as designated in Figure 6. i

_{Lin}and i

_{Li}peak at the end of this mode as

_{DS}, is the sum of all the inductor currents of i

_{Lin}and i

_{Li}, and it can be yielded from (5) and (6). The sum of I

_{Lin.DCM}and I

_{Li.DCM}is zero [see (19)] and therefore,

_{DS}, I

_{DS.peak}, is

_{1}≤ t < T

_{2}) (Figure 7b): Q is turned off and D

_{1}starts to conduct. All inductors start discharging. v

_{Lin}in Mode 2 is

_{f}is the diode forward voltage drop. Meanwhile, v

_{Li}in this mode is expressed as

_{Lin}and v

_{Li}are identical in this mode.

_{Lin}and i

_{Li}in Mode 2 are expressed as

_{1}, i

_{D}

_{1}, is the sum of all the inductor currents, as can be seen from Figure 7b. From (10), (14) and (15),

_{D.peak}is the peak of the diode current and

_{D}

_{1}declines to zero. Hence, from (10) and (17), the mode length can be yielded as

_{a}is the duty cycle of Mode 2.

_{2}≤ t < T

_{s}) (Figure 7c): Both v

_{Lin}and v

_{Li}are zero and therefore, i

_{Lin}and i

_{Li}are constant. Kirchhoff’s current law at node A yields

_{in}from (1) and (11) or L

_{1}of (4) and (13), as

_{1}, which is connected to the least charged cell B

_{1}, conducts, whereas the others are off for the entire period. An average current of D

_{1}, I

_{D}

_{1.ave}, flows toward B

_{1}as an equalization current is equal to an average current of i

_{L}

_{1}, I

_{L}

_{1}, because an average current of C

_{1}must be zero under steady-state conditions. I

_{D}

_{1.ave}and I

_{L}

_{1}are yielded from (10), (17) and (20), as

_{X}is the combined inductance given by

_{Lin}, I

_{Lin}, must be equal to an average switch current, I

_{Q.ave}, because average currents of C

_{1}–C

_{4}connected to the switching node A are zero under steady-state conditions. I

_{Lin}or I

_{Q.ave}flowing toward the string is expressed as

_{Q.ave}and I

_{D}

_{1.ave}under the voltage-imbalanced condition where B

_{1}is the least charged cell. Both I

_{Lin}and I

_{L}

_{1}are dependent on d

_{2}T

_{s}and L

_{x}. Hence, a string charging current (I

_{Lin}) and equalization current (I

_{L}

_{1}) can be limited within the desired level by properly determining these parameters.

#### 3.3. Operation under Voltage-Balanced Condition

_{Li}and the diode current i

_{Di}are assumed to be uniform.

_{1}) (Figure 9a): Current flow directions under the voltage-balanced condition are identical to those in the voltage-imbalanced condition (see Figure 7a), and therefore, voltages and currents of L

_{in}, L

_{i}, and D

_{i}are expressed identically to those shown in Section 3.2.

_{1}≤ t < T

_{2}) (Figure 9b): i

_{Lin}is equally distributed to C

_{1}–C

_{4}and flows through D

_{1}–D

_{4}. v

_{Lin}and v

_{Li}are

_{Lin}and i

_{Li}are

_{i}is the sum of i

_{Li}and i

_{Lin}/4 and therefore,

_{Di.peak}is the peak of the diode current, calculated as

_{Di}in the voltage-balanced condition is one-fourth of (17). As i

_{Di}reaches zero, the operation shifts to the next mode.

_{2}≤ t < T

_{s}) (Figure 9c): Similar to the voltage-imbalanced condition, inductor voltages are zero and inductor currents are constant.

_{st}= 4V

_{i}into (20) leads to (29), indicating that the voltage conversion ratios under the voltage-imbalanced and -balanced conditions are seamless and consistent.

_{i}, I

_{Di.ave}, that is equal to an average of i

_{Li}, I

_{Li}, is expressed as

_{Di.ave}or I

_{Li}under the voltage-balanced condition is a quarter of (21). The comparison between (21) and (30) suggests that the sum of I

_{D}

_{1}–I

_{D}

_{4}or I

_{L}

_{1}–I

_{L}

_{4}is independent of whether the cell voltages are balanced. I

_{Lin}or I

_{Q.ave}are also independent of voltage imbalance as (23) does not contain individual cell voltages, V

_{i}.

#### 3.4. DCM Boundary

_{a}< 1. The DCM boundary can be obtained from (18) with the relationship of d + d

_{a}< 1, expressed as

#### 3.5. Impact of Component Tolerance on Voltage Equalization Performance

_{1}− v

_{2})/v

_{1}was performed. The percentage impacts of ±10% component tolerance were investigated based on both the state−space equation and the simulation analysis. Results are shown in the form of a tornado diagram in Figure 11 and typical values and analysis conditions are listed in the inset. The theoretical and simulation results were in good agreement, verifying the derived state−space equation. The results indicated the diode forward voltage drops of V

_{f}

_{1}and V

_{f}

_{2}were the largest source of the voltage error. If V

_{f}

_{1}increased by 10%, for example, the voltage error would be −1.8%. The impact of the component tolerance of inductances and capacitances was minor because cell voltages are theoretically independent of these parameters, as indicated by (20) and (29). In summary, component tolerances showed a minor impact on the voltage error, suggesting that cell voltages can be equalized well by the proposed integrated charger even without carefully screening circuit components.

## 4. Design Example

_{in}= 19.5 V is exemplified in this section. The design target is P

_{in}= 12 W (i.e., I

_{Lin}< 0.62 A), V

_{st}> 6 V, V

_{i}= 1.2–2.5 V, and f

_{s}= 50 kHz (T

_{s}= 20 µs).

_{x}can be determined from (23), as

_{in}= L

_{i}for the sake of design simplicity, (22) yields

_{i}needs to be sufficiently large to ensure that the resonance between L

_{i}and C

_{i}does not occur. To this end, C

_{i}is determined such that the resonant frequency is lower than one-fifth of f

_{s}.

## 5. DC Equivalent Circuit and Its Simulation Results

#### 5.1. Derivation of DC Equivalent Circuit

_{L}

_{1}–I

_{L}

_{4}is independent of whether the cell voltages are balanced or imbalanced. A dc equivalent circuit of the superbuck-based integrated charger can be derived by expressing inductors as a constant current source, as shown in Figure 12. Current sources of I

_{Lin}and I

_{L}

_{1}–I

_{L}

_{4}obey (23) and (30), respectively. To generate a seamless transition between (21) and (30), I

_{L}

_{1}–I

_{L}

_{4}are connected in parallel through an ideal multi-winding transformer. Under voltage-balanced conditions, I

_{L}

_{1}–I

_{L}

_{4}flow toward B

_{1}–B

_{4}through their respective diodes. On the other hand, under voltage-imbalanced conditions, all of I

_{L}

_{1}–I

_{L}

_{4}go to the least charged cell via the multi-winding transformer.

#### 5.2. Simulation-Based Equalization

_{Lin}and I

_{L}

_{1}–I

_{L}

_{4}were programmed to obey (23) and (30), respectively, and component values for an experimental prototype (see Table 2) at a switching frequency of 50 kHz with d = 0.1 were used for the simulation. The series-connected cells were charged to be a CV of 10.0 V (2.5 V/cell).

_{in}steadily decreased as V

_{st}increased [see (23)]. Equalization currents, or I

_{L}

_{1}–I

_{L}

_{4}, flowed toward cells, but their magnitudes were dependent on cell voltages. At the beginning of the charging, B

_{4}received the largest equalization current in the form of I

_{L}

_{4}, and V

_{4}increased faster than others. The voltage imbalance was gradually eliminated as the charging progressed, and all the cells were uniformly charged to 2.5 V after V

_{st}reached the CV charging level of 10.0 V.

## 6. Experimental Results

#### 6.1. Prototype and Its Characteristics

#### 6.2. Characteristics of Integrated Charger Alone

_{1}is the lowest—Tap 1 emulates the operation modes in Figure 7. The CV load is set at 7.5 V (2.5 V/cell), and the VV load is swept in the range of 1.2–2.5 V. Tap 2, on the other hand, emulates the case in which both V

_{1}and V

_{2}are the lowest. The CV load voltage is fixed at 5.0 V (2.5 V/cell) while sweeping the VV load in the range of 2.4–5.0 V (1.2–2.5 V/cell). The operation modes under the voltage-balanced condition (see Figure 9) can be emulated by selecting Tap 4, through which the CV load is short-circuited, and the entire string is connected to the VV load.

_{1}= 1.2 V are shown in Figure 16, where v

_{GS}is the gate-source voltage. Oscillations in v

_{DS}were due to the parasitic capacitance of the MOSFET. When Tap 1 was selected (Figure 16a), the average of i

_{L}

_{1}was substantial, whereas those of i

_{L}

_{2}–i

_{L}

_{4}were uniform and zero. These measured waveforms agreed well with the theoretical ones shown in Figure 6. In the cases where Taps 2 and 3 were selected (see Figure 16b,c), i

_{L}

_{1}and i

_{L}

_{2}were uniform and their averages were greater than zero, whereas the averages of the other inductor currents were zero. When Tap 4 was selected to emulate the voltage-balanced condition, i

_{L}

_{1}–i

_{L}

_{4}were uniform.

_{1}are shown in Figure 17—V

_{1}corresponds to the least charged voltage in practical use. Measured efficiencies monotonically increased with V

_{1}as the portion of the output voltage taken by the diode voltage drops decreased. Since the output voltage was low (<2.6 V), diode forward voltage drops took a significant portion of the output voltage V

_{1}, resulting in poor power conversion efficiencies of <90%. The efficiencies varied depending on the selected tap, probably because the number of conducting diodes differed depending on whether cell voltages were balanced—only one diode conducts in the case of tap 1 (see Figure 7b), whereas all diodes conduct in the case of tap 4 (Figure 9b). These results suggest that the proposed integrated charger is not suited for high-power applications where efficiency maximization is prioritized over the circuit simplification, as mentioned in Section 2.3.

#### 6.3. Charging Test for EDLCs

_{1}was replaced with the one with V

_{f}= 0.4 V in order to investigate the impact of component tolerance on the voltage equalization performance—The V

_{f}of other diodes was 0.35 V, as shown in Table 2. The results of the charging test are shown in Figure 18b. Even with the mismatched V

_{f}of D

_{1}, the voltage imbalance adequately disappeared, and all the cells were uniformly charged to 2.5 V in the CV charging period. The SD at the end of the CV charging was 25 mV, which was slightly larger than the case shown in Figure 18a. Although slightly increased, the results demonstrated the minor impact of the component tolerance on the equalization performance.

## 7. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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**Figure 1.**Energy storage systems based on (

**a**) charger with equalizer, (

**b**) individual chargers, and (

**c**) integrated charger.

**Figure 2.**PWM converter with two inductors and one energy transfer capacitor: (

**a**) Superbuck converter, (

**b**) SEPIC, (

**c**) Zeta converter, (

**d**) Ćuk converter.

**Figure 3.**Proposed integrated chargers based on (

**a**) superbuck converter, (

**b**) SEPIC, (

**c**) Zeta converter, (

**d**) Ćuk converter.

**Figure 7.**Operation modes under voltage-imbalanced condition in (

**a**) Mode 1, (

**b**) Mode 2, and (

**c**) Mode 3.

**Figure 9.**Operation modes under voltage-imbalanced condition in (

**a**) Mode 1, (

**b**) Mode 2, and (

**c**) Mode 3.

**Figure 18.**Resultant charging profiles of EDLCs with (

**a**) uniform circuit elements and (

**b**) mismatched circuit elements.

Topology | DCM Boundary | Current Ripple | Voltage Stress of Q and D | Capacitor Voltage V_{Ck} (k = 1…n) | |
---|---|---|---|---|---|

Input | Output | ||||

Superbuck | $\frac{d}{1+d\left(n-1\right)}$ | Low | Low | ${V}_{in}-\left(n-1\right){V}_{e}$ | ${V}_{in}-{\displaystyle {\displaystyle \sum}_{k=1}^{n-1}}{V}_{k}$ |

SEPIC | $\frac{d}{1-d}$ | Low | High | ${V}_{in}+{V}_{e}$ | ${V}_{in}-{\displaystyle {\displaystyle \sum}_{k=1}^{n-1}}{V}_{k}$ |

Zeta | $\frac{d}{1-d}$ | High | Low | ${V}_{in}+{V}_{e}$ | ${\displaystyle \sum}_{k=1}^{n}}{V}_{k$ |

Ćuk | $\frac{d}{1-d}$ | Low | Low | ${V}_{in}+{V}_{e}$ | ${V}_{in}+{\displaystyle {\displaystyle \sum}_{k=1}^{n}}{V}_{k}$ |

Component | Value, Part Number |
---|---|

Q | N-Ch MOSFET, ZXMN4A06GTA, R_{on} = 75 mΩ |

L_{in}, L_{1}–L_{4} | 10 µH, 33 mΩ |

C_{in} | Aluminum Electrolytic Capacitor, 330 µF |

C_{1}–C_{4} | Ceramic Capacitor, 36 µF |

D_{1}–D_{4} | Schottky Barrier Diode, SL44, V_{f} = 0.35 V |

C_{o1}–C_{o4} | Ceramic Capacitor, 300 µF |

Gate Driver | L6741 |

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**MDPI and ACS Style**

Uno, M.; Xu, Q.; Sato, Y. Multi-Stacked Superbuck Converter-Based Single-Switch Charger Integrating Cell Voltage Equalizer for Series-Connected Energy Storage Cells. *Energies* **2022**, *15*, 3619.
https://doi.org/10.3390/en15103619

**AMA Style**

Uno M, Xu Q, Sato Y. Multi-Stacked Superbuck Converter-Based Single-Switch Charger Integrating Cell Voltage Equalizer for Series-Connected Energy Storage Cells. *Energies*. 2022; 15(10):3619.
https://doi.org/10.3390/en15103619

**Chicago/Turabian Style**

Uno, Masatoshi, Qi Xu, and Yusuke Sato. 2022. "Multi-Stacked Superbuck Converter-Based Single-Switch Charger Integrating Cell Voltage Equalizer for Series-Connected Energy Storage Cells" *Energies* 15, no. 10: 3619.
https://doi.org/10.3390/en15103619