Multi-Stacked Superbuck Converter-Based Single-Switch Charger Integrating Cell Voltage Equalizer for Series-Connected Energy Storage Cells

Abstract

Voltages of series-connected energy storage cells, such as electric double-layer capacitors (EDLCs) and lithium-ion batteries, need to be equalized to ensure years of safe operation. However, to this end, a voltage equalizer is necessary in addition to a charger, increasing the system complexity and cost. This paper proposes a family of transformerless single-switch integrated chargers that merge a charger and equalizer into a single unit, achieving a simplified system and circuit. Proposed integrated chargers are derived by stacking multiple conventional pulse width modulation (PWM) converters, such as a superbuck converter, that contain two inductors and one energy transfer capacitor. Detailed operation analyses, including an investigation on the impact of component tolerance on voltage equalization performance, are also performed. Experimental charging tests using a 12-W prototype were performed for four EDLC cells. All cells were charged with eliminating voltage imbalance and demonstrating the charging and equalization performance of the proposed integrated charger.

1. Introduction

Energy storage cells, such as electric double-layer capacitors (EDLCs) and lithium-ion battery cells, are connected in series to form a string to meet the voltage requirements of loads and systems. Individual cell characteristics are not uniform in practical use due to manufacturing tolerance, uneven aging, and ambient temperature conditions. As all cells in a string are charged in series, some cells with higher voltages might be over-charged during a charging process, potentially triggering a hazardous consequence. Even a minor characteristic mismatch eventually results in premature deterioration and reduced capacity, as reported in [1,2]. Thus, cell voltage equalization is mandatory to ensure years of safe operations and to maximize the chargeable/dischargeable energies of cells.

Extensive research and development efforts on cell equalizers have been underway since the advent of EDLCs and lithium-ion batteries. Various types of equalizers, also called balancers, have been proposed and developed. Conventional equalizers based on bidirectional converters, such as pulse width modulation (PWM) converters [3,4,5] and switched capacitor converters [6,7,8,9], transfer energies between neighboring cells or two arbitrary cells to achieve equalization. However, these equalizers are prone to complexity as the switch count necessary is proportional to the number of cells connected in series. With single-input–multi-output converter-based equalizers [10,11,12,13,14,15,16], the switch count can be drastically reduced, contributing to the simplified system. Cell equalizers using selection switches, which have been intensively developed for lithium-ion batteries in electric vehicles, can dramatically reduce the passive component count [17,18,19,20,21,22,23]. However, these equalizers require numerous bidirectional switches in proportion to the cell count, resulting in increased circuit complexity and cost.

The common drawback of these equalizers is that, in addition to the equalizer, an external converter is necessary for battery regulation. Figure 1a, for example, illustrates an energy storage system based on so-called unregulated bus architecture where the battery is directly connected to a load. This system boasts its simplicity as the battery directly discharges to the load, though the load voltage varies with the battery. Obviously, two separate converters are necessary to perform the two functions of battery charging and cell equalization, thus increasing the system complexity.

An alternative solution is the use of individual cell chargers, as shown in Figure 1b. All cells can be individually charged to a uniform voltage level by individual chargers. Although cell equalizers are no longer necessary, the charging system apparently tends to be complex as n individual chargers are necessary for n cells connected in series. A multi-output charger based on a multi-winding flyback converter has been proposed [24,25], but the design difficulty of the multi-winding transformer is cited as a top concern—parameters of multiple secondary windings, such as leakage inductance, resistance, and turns ratio, must be strictly matched to achieve an adequate equalization performance.

In previous works [26,27,28], converters integrating voltage equalizers have been proposed, as shown in Figure 1c. Since a converter (or a charger) and equalizer are integrated through the sharing of some circuit elements, both the system and circuit can be simplified to a greater extent than ordinary systems. Integrated converters would be an appealing topology for low-cost, low-power energy storage systems. However, a transformer is necessary to integrate a converter and equalizer regardless of isolation requirements, increasing the circuit volume and cost. Furthermore, the conventional integrated converters suffer from poor extendibility (or modularity) because redesigning transformers is mandatory in cases where the cell count changes—transformers’ turn ratios need to be properly determined based on the number of series-connected cells.

This paper proposes a family of transformerless single-switch integrated chargers that merge a charger and equalizer into a single unit. The proposed integrated chargers can be derived by stacking multiple conventional PWM converters, each having two inductors and one energy transfer capacitor. In addition to the integration, the switch count can be reduced to one, achieving a simplified system, design, and circuit.

This paper is organized as follows. Section 2 presents the circuit derivation, features, and comparison among four integrated charger topologies. Among these is the superbuck converter that is considered best suited for energy storage applications. Detailed operation analyses, including an investigation on the impact of component tolerance on voltage equalization performance, are performed on a superbuck converter-based integrated charger in Section 3. A circuit design for the 12-W prototype is exemplified in Section 4. A dc equivalent circuit of the proposed integrated charger is derived and verified by simulation analysis in Section 5. Finally, Section 6 presents experimental results of the designed 12-W prototype and equalization charging of four EDLCs connected in series.

2. Proposed Integrated Chargers

2.1. PWM Converters

The proposed integrated chargers are derived from PWM converters as a foundation. PWM converters with two inductors and one energy transfer capacitor, as shown in Figure 2, can be a foundation circuit. A superbuck converter is a step-down converter with low current ripples at both its input and output ports. A single-ended primary inductor converter (SEPIC) and Zeta converters are non-inverting buck-boost converters and are often used as battery chargers for low-power applications. A Ćuk converter is an inverting buck-boost converter.

All topologies in Figure 2 contain an energy transfer capacitor followed by an inductor and a diode, as highlighted with dashed lines. Switching nodes (designated as A) produce a square-wave voltage and therefore, the energy transfer capacitors in these topologies behave as an ac-coupling capacitor.

2.2. Single-Switch Integrated Chargers

By stacking capacitor−inductor−diode (CLD) circuits on the switching node in respective PWM converters, single-switch integrated chargers can be derived. Derived chargers for four cells connected in series are shown in Figure 3. Smoothing capacitors C_o1–C_o4 are connected in parallel with energy storage cells B₁–B₄. The string voltage, V_st, is regulated by a constant-voltage (CV) charging scheme, whereas voltages of C_o1–C_o4, V₁–V₄, are automatically equalized even without feedback control, which is detailed in Section 3.

2.3. Benefits and Drawbacks

As mentioned in Section 1, the charger and voltage equalizer are integrated into a single unit with a reduction in circuit components, hence realizing a simplified system and circuit. In general, a switch count is a metric of circuit complexity, as each switch requires not only a gate driver circuit but also an auxiliary power supply. Regardless of the cell count, all of the derived integrated chargers contain only one switch, achieving the simplified circuit.

From the viewpoint of power conversion efficiency, the proposed integrated chargers are not a good solution. The integrated chargers contain n diodes (where n is the cell count) and their output voltages are as low as cell voltages. Diode forward voltage drops take significant portions of output voltages, unavoidably lowering power conversion efficiencies. Hence, the proposed integrated chargers would be suitable for low-power applications where circuit simplification and cost reduction are prioritized over efficiency maximization.

The number of cells can be arbitrarily extended by stacking CLD circuits, offering good extendibility. However, voltage conversion ratios depend on topologies and the number of cells (see Section 2.4 for details) and hence, a proper topology needs to be selected when considering applications and requirements.

A charging current for series-connected cells must be properly limited to avoid damage. A constant-current (CC) charging scheme is a straightforward approach to limit a charging current, but obtaining current measurement using a current sensor is necessary. By operating the proposed integrated charger in discontinuous conduction mode (DCM), a charging current can be limited within the desired value even without feedback control, allowing a simplified circuit and reduced cost.

The integrated chargers inherit the advantages and drawbacks of respective foundation circuits listed in Figure 2. In the following subsection, four topologies are compared from various viewpoints.

2.4. Comparison

Four integrated chargers are compared from the viewpoint of the DCM boundary condition, current ripple, voltage stress of switches and diodes, and capacitor voltage stress, as shown in

Table 1. Component values used for prototype.

Topology	DCM Boundary	Current Ripple		Voltage Stress of Q and D	Capacitor Voltage VCk (k = 1…n)
		Input	Output
Superbuck	$\frac{d}{1+d\left(n-1\right)}$	Low	Low	$V_{in}-\left(n-1\right)V_e$	$V_{in}-{\displaystyle {\displaystyle \sum }_{k=1}^{n-1}}{V}_k$
SEPIC	$\frac{d}{1-d}$	Low	High	$V_{in}+V_e$	$V_{in}-{\displaystyle {\displaystyle \sum }_{k=1}^{n-1}}{V}_k$
Zeta	$\frac{d}{1-d}$	High	Low	$V_{in}+V_e$	${\displaystyle {\displaystyle \sum }_{k=1}^n}{V}_k$
Ćuk	$\frac{d}{1-d}$	Low	Low	$V_{in}+V_e$	$V_{in}+{\displaystyle {\displaystyle \sum }_{k=1}^n}{V}_k$

. V_in is the input voltage, d is the duty cycle, V_e is the equalized cell voltage (V₁ = V₂ = … = V_e), and n is the number of cells in series; equations for the superbuck-based topology will be mathematically derived in Section 3.

DCM boundaries are shown and compared in Figure 4. Boundary conditions of the buck-boost converter topologies (i.e., SEPIC, Zeta, and Ćuk converters) are identical, whereas characteristics of the superbuck topology are dependent on n. This figure suggests that integrated chargers are prone to operate in continuous conduction mode (CCM) as V_e/V_in decreases. The DCM region of the superbuck topology is larger than that of the buck-boost topologies, though its operational region is nV_e/V_in ≤ 1.0. Since the proposed integrated chargers are supposed to operate in DCM, the superbuck topology would be advantageous as long as nV_e/V_in ≤ 1.0 is satisfied.

The superbuck-based topology is also superior to other buck-boost topologies in terms of current ripple and voltage stresses. Thus, the following sections focus on the superbuck-based integrated charger.

3. Operation Analysis

3.1. Voltage Equalization Mechanism

All the energy transfer capacitors, C₁–C₄, are connected to the switching node generating an ac voltage and hence, the stacked CLD circuits are ac-coupled. Thus, respective CLD circuits, as well as smoothing capacitors and energy storage cells, can be equivalently separated and grounded, as shown in Figure 5. All the CLD circuits and energy storage cells are connected in parallel and are driven by the square-wave voltage generator. This equivalent circuit suggests that a current from the square-wave voltage generator preferentially flows toward the least charged cell(s) with the lowest voltage in the string, and all the cell voltages eventually become uniform as the charging progresses.

3.2. Operation under Voltage-Imbalanced Condition

This subsection deals with the voltage-imbalanced condition where the voltage of B₁, V₁, is the lowest in the string. All circuit elements are assumed ideal. Theoretical operation waveforms and current flow directions in DCM are shown in Figure 6 and Figure 7.

Mode 1 (0 ≤ t < T₁) (Figure 7a): The switch Q is turned on. All inductors are charged, and their currents increase linearly. The voltage applied to L_in and L_i (i = 1…4), v_Lin and v_Li, in Mode 1 are given by

$$v_{Lin}=V_{in}-V_{st}$$

(1)

$$v_{Li}=V_{Ci}-{\displaystyle \sum }_{k=i}^4{V}_k$$

(2)

where V_k is the voltage of B_k and V_Ci is the voltage of C_i that is expressed as

$$V_{Ci}=V_{in}-{\displaystyle \sum }_{k=1}^{i-1}{V}_k$$

(3)

This equation can be obtained by assuming average inductor voltages are zero under steady-state conditions. The substitution of (3) into (2) produced

$$v_{Li}=V_{in}-V_{st}$$

(4)

Thus, from (1) and (4), v_Lin and v_Li are identical.

Currents of L_in and L_i, i_Lin and i_Li, are

$$i_{Lin}=\frac{V_{in}-V_{st}}{L_{in}}t+I_{Lin.DCM}$$

(5)

$$i_{Li}=\frac{V_{in}-V_{st}}{L_i}t+I_{Li.DCM}$$

(6)

where I_Lin.DCM and I_Li.DCM are the initial values of i_Lin and i_Li in Mode 3, as designated in Figure 6. i_Lin and i_Li peak at the end of this mode as

$$I_{Lin.peak}=\frac{V_{in}-V_{st}}{L_{in}}d{T}_s+I_{Lin.DCM}$$

(7)

$$I_{Li.peak}=\frac{V_{in}-V_{st}}{L_i}d{T}_s+I_{Li.DCM}$$

(8)

The current of Q, i_DS, is the sum of all the inductor currents of i_Lin and i_Li, and it can be yielded from (5) and (6). The sum of I_Lin.DCM and I_Li.DCM is zero [see (19)] and therefore,

$$i_{DS}=\left(V_{in}-V_{st}\right)\left(\frac{1}{L_{in}}+{\displaystyle \sum }_{k=1}^4\frac{1}{L_k}\right)t$$

(9)

The peak value of i_DS, I_DS.peak, is

$$I_{DS.peak}=I_{Lin.peak}+{\displaystyle \sum }_{k=1}^4{I}_{Lk.peak}=\left(V_{in}-V_{st}\right)\left(\frac{1}{L_{in}}+{\displaystyle \sum }_{k=1}^4\frac{1}{L_k}\right)d{T}_s$$

(10)

Mode 2 (T₁ ≤ t < T₂) (Figure 7b): Q is turned off and D₁ starts to conduct. All inductors start discharging. v_Lin in Mode 2 is

$$v_{Lin}=V_{in}-V_{C1}-V_1-V_f=-\left(V_1+V_f\right)$$

(11)

where V_f is the diode forward voltage drop. Meanwhile, v_Li in this mode is expressed as

$$\{\begin{array}{c}{v}_{L1}=-\left(V_1+V_f\right)\\ v_{L2}=-V_{C1}+V_{C2}-V_f\\ v_{L3}=V_2-V_{C1}+V_{C3}-V_f\\ v_{L4}=V_2+V_3-V_{C1}+V_{C4}-V_f\end{array}$$

(12)

Substituting (3) into (12) yields

$$v_{Li}=-\left(V_1+V_f\right)$$

(13)

Similar to Mode 1, v_Lin and v_Li are identical in this mode.

i_Lin and i_Li in Mode 2 are expressed as

$$i_{Lin}=-\frac{V_1+V_f}{L_{in}}\left(t-T_1\right)+I_{Lin.peak}$$

(14)

$$i_{Li}=-\frac{V_1+V_f}{L_i}\left(t-T_1\right)+I_{Li.peak}$$

(15)

The current of D₁, i_D1, is the sum of all the inductor currents, as can be seen from Figure 7b. From (10), (14) and (15),

$$i_{D1}=i_{Lin}+{\displaystyle \sum }_{k=1}^4{i}_{Lk}=I_{D.peak}-\left(V_1+V_f\right)\left(\frac{1}{L_{in}}+{\displaystyle \sum }_{k=1}^4\frac{1}{L_k}\right)\left(t-T_1\right)$$

(16)

where I_D.peak is the peak of the diode current and

$$I_{D.peak}=I_{Lin.peak}+{\displaystyle \sum }_{k=1}^4{I}_{Lk.peak}=I_{DS.peak}$$

(17)

This operation mode ends as i_D1 declines to zero. Hence, from (10) and (17), the mode length can be yielded as

$$d_a{T}_s=\frac{V_{in}-V_{st}}{V_1+V_f}d{T}_s$$

(18)

where d_a is the duty cycle of Mode 2.

Mode 3 (T₂ ≤ t < T_s) (Figure 7c): Both v_Lin and v_Li are zero and therefore, i_Lin and i_Li are constant. Kirchhoff’s current law at node A yields

$$0=I_{Lin.DCM}+{\displaystyle \sum }_{k=1}^4{I}_{Lk.DCM}$$

(19)

The voltage conversion ratio under the voltage-imbalanced condition can be yielded from the volt-sec balance of L_in from (1) and (11) or L₁ of (4) and (13), as

$$V_1=\frac{d\left(V_{in}-V_{st}\right)}{d_a}-V_f$$

(20)

In summary, the diode D₁, which is connected to the least charged cell B₁, conducts, whereas the others are off for the entire period. An average current of D₁, I_D1.ave, flows toward B₁ as an equalization current is equal to an average current of i_L1, I_L1, because an average current of C₁ must be zero under steady-state conditions. I_D1.ave and I_L1 are yielded from (10), (17) and (20), as

$$I_{D1.ave}=I_{L1}=\frac{1}{2}{d}_a{I}_{D.peak}=\frac{d^2{T}_s{\left(V_{in}-V_{st}\right)}^2}{2L_X\left(V_1+V_f\right)}$$

(21)

where L_X is the combined inductance given by

$$\frac{1}{L_X}=\frac{1}{L_{in}}+{\displaystyle \sum }_{k=1}^4\frac{1}{L_k}$$

(22)

Meanwhile, an average current of i_Lin, I_Lin, must be equal to an average switch current, I_Q.ave, because average currents of C₁–C₄ connected to the switching node A are zero under steady-state conditions. I_Lin or I_Q.ave flowing toward the string is expressed as

$$I_{Lin}=I_{Q.ave}=\frac{1}{2}d{I}_{DS.peak}=\frac{d^2{T}_s\left(V_{in}-V_{st}\right)}{2L_X}$$

(23)

Thus, cells are charged with I_Q.ave and I_D1.ave under the voltage-imbalanced condition where B₁ is the least charged cell. Both I_Lin and I_L1 are dependent on d₂T_s and L_x. Hence, a string charging current (I_Lin) and equalization current (I_L1) can be limited within the desired level by properly determining these parameters.

3.3. Operation under Voltage-Balanced Condition

Theoretical waveforms and operation modes under the voltage-balanced condition are shown in Figure 8 and Figure 9, respectively. All the inductor currents i_Li and the diode current i_Di are assumed to be uniform.

Mode 1 (0 ≤ t < T₁) (Figure 9a): Current flow directions under the voltage-balanced condition are identical to those in the voltage-imbalanced condition (see Figure 7a), and therefore, voltages and currents of L_in, L_i, and D_i are expressed identically to those shown in Section 3.2.

Mode 2 (T₁ ≤ t < T₂) (Figure 9b): i_Lin is equally distributed to C₁–C₄ and flows through D₁–D₄. v_Lin and v_Li are

$$v_{Lin}=v_{Li}=-\left(V_i+V_f\right)$$

(24)

i_Lin and i_Li are

$$i_{Lin}=-\frac{V_i+V_f}{L_{in}}\left(t-T_1\right)+I_{Lin.peak}$$

(25)

$$i_{Li}=-\frac{V_i+V_f}{L_i}\left(t-T_1\right)+I_{Li.peak}$$

(26)

A current of D_i is the sum of i_Li and i_Lin/4 and therefore,

$$i_{Di}=\frac{i_{Lin}}{4}+i_{Lk}=I_{Di.peak}-\left(V_i+V_f\right)\left(\frac{1}{4L_{in}}+\frac{1}{L_i}\right)\left(t-T_1\right)$$

(27)

where I_Di.peak is the peak of the diode current, calculated as

$$I_{Di.peak}=\frac{I_{Lin.peak}}{4}+I_{Li.peak}=\frac{I_{DS.peak}}{4}$$

(28)

This equation reveals that i_Di in the voltage-balanced condition is one-fourth of (17). As i_Di reaches zero, the operation shifts to the next mode.

Mode 3 (T₂ ≤ t < T_s) (Figure 9c): Similar to the voltage-imbalanced condition, inductor voltages are zero and inductor currents are constant.

The volt-sec balance of inductors based on (1) or (4) and (24) produces the voltage conversion ratio under the voltage-balanced condition as

$$V_i=\frac{d{V}_{in}-d_a{V}_f}{4d+d_a}$$

(29)

Substituting V_st = 4V_i into (20) leads to (29), indicating that the voltage conversion ratios under the voltage-imbalanced and -balanced conditions are seamless and consistent.

In summary, all diodes conduct in Mode 2 under the voltage-balanced condition. An average current of D_i, I_Di.ave, that is equal to an average of i_Li, I_Li, is expressed as

$$I_{Di.ave}=I_{Li}=\frac{1}{2}{d}_a{I}_{Di.peak}=\frac{d^2{T}_s{\left(V_{in}-V_{st}\right)}^2}{8L_X\left(V_i+V_f\right)}$$

(30)

Thus, I_Di.ave or I_Li under the voltage-balanced condition is a quarter of (21). The comparison between (21) and (30) suggests that the sum of I_D1–I_D4 or I_L1–I_L4 is independent of whether the cell voltages are balanced. I_Lin or I_Q.ave are also independent of voltage imbalance as (23) does not contain individual cell voltages, V_i.

3.4. DCM Boundary

In order for the proposed integrated charger to operate in DCM, Mode 3 must exist. In other words, the sum of the lengths of Modes 1 and 2 must be shorter than a switching period, yielding d + d_a < 1. The DCM boundary can be obtained from (18) with the relationship of d + d_a < 1, expressed as

$$d<\frac{V_i+V_f}{V_{in}-V_{st}+V_i+V_f}$$

(31)

3.5. Impact of Component Tolerance on Voltage Equalization Performance

The proposed integrated charger is a single-switch topology and its equalization performance relies on passive components, including capacitors, inductors, and diodes. Hence, component tolerance might impair the voltage equalization performance and its impact should be investigated.

A detailed circuit modeling based on a state−space equation was obtained for the circuit using two cells connected in series (see Figure 10):

$$\{\begin{array}{c}\frac{dx}{dt}=Ax+Bu\\ y=Cx\end{array}$$

(32)

where x is the state variable vector, u is the input vector, and y is the output vector;

$$x={\left[\begin{array}{ccccccc}{i}_{Lin}& i_{L1}& i_{L2}& v_{C1}& v_{C2}& v_1& v_2\end{array}\right]}^T$$

(33)

$$u={\left[\begin{array}{ccccc}{V}_{in}& V_{D1}& V_{D2}& I_1& I_2\end{array}\right]}^T$$

(34)

$$y={\left[\begin{array}{cc}{v}_1& v_2\end{array}\right]}^T$$

(35)

Coefficient matrices A and B are expressed as

$$A=\left[\begin{array}{ccccccc}\frac{\left(R_{Lin}+d{R}_{on}\right)\left(R_{C1}+R_{C2}\right)+\left(1-d\right)R_{C1}{R}_{C2}}{L_{in}}& \frac{d{R}_{on}}{L_{in}}& \frac{d{R}_{on}}{L_{in}}& \frac{R_{C2}\left(1-d\right)}{L_{in}\left(R_{C1}+R_{C2}\right)}& \frac{R_{C1}\left(1-d\right)}{L_{in}\left(R_{C1}+R_{C2}\right)}& \frac{1}{L_{in}}& \frac{R_{C1}+d{R}_{C2}}{L_{in}\left(R_{C1}+R_{C2}\right)}\\ \frac{d{R}_{on}}{L_1}& \frac{d{R}_{on}+d{R}_{C1}+R_{L1}}{L_1}& \frac{d{R}_{on}}{L_1}& -\frac{d}{L_1}& 0& \frac{1}{L_1}& \frac{d}{L_1}\\ \frac{d{R}_{on}}{L_2}& \frac{d{R}_{on}}{L_2}& \frac{d{R}_{on}+d{R}_{C2}+R_{L2}}{L_2}& 0& -\frac{d}{L_2}& 0& \frac{1}{L_2}\\ \frac{-R_{C2}\left(1-d\right)}{C_1\left(R_{C1}+R_{C2}\right)}& \frac{d}{C_1}& 0& \frac{1-d}{C_1\left(R_{C1}+R_{C2}\right)}& \frac{-\left(1-d\right)}{C_1\left(R_{C1}+R_{C2}\right)}& 0& \frac{-\left(1-d\right)}{C_1\left(R_{C1}+R_{C2}\right)}\\ \frac{-R_{C1}\left(1-d\right)}{C_2\left(R_{C1}+R_{C2}\right)}& 0& \frac{d}{C_2}& \frac{-\left(1-d\right)}{C_2\left(R_{C1}+R_{C2}\right)}& \frac{1-d}{C_2\left(R_{C1}+R_{C2}\right)}& 0& \frac{1-d}{C_2\left(R_{C1}+R_{C2}\right)}\\ -\frac{1}{C_{o1}}& -\frac{1}{C_{o1}}& 0& 0& 0& 0& 0\\ -\frac{R_{C1}+d{R}_{C2}}{C_{o2}\left(R_{C1}+R_{C2}\right)}& -\frac{d}{C_{o2}}& -\frac{1}{C_{o2}}& \frac{-\left(1-d\right)}{C_{o2}\left(R_{C1}+R_{C2}\right)}& \frac{1-d}{C_{o2}\left(R_{C1}+R_{C2}\right)}& 0& \frac{1-d}{C_{o2}\left(R_{C1}+R_{C2}\right)}\end{array}\right]$$

(36)

$$B=\left[\begin{array}{ccccc}\frac{-1}{L_{in}}& \frac{R_{C2}\left(1-d\right)}{L_{in}\left(R_{C1}+R_{C2}\right)}& \frac{R_{C1}\left(1-d\right)}{L_{in}\left(R_{C1}+R_{C2}\right)}& 0& 0\\ 0& \frac{1-d}{L_1}& 0& 0& 0\\ 0& 0& \frac{1-d}{L_2}& 0& 0\\ 0& \frac{1-d}{C_1\left(R_{C1}+R_{C2}\right)}& \frac{-\left(1-d\right)}{C_1\left(R_{C1}+R_{C2}\right)}& 0& 0\\ 0& \frac{-\left(1-d\right)}{C_2\left(R_{C1}+R_{C2}\right)}& \frac{1-d}{C_2\left(R_{C1}+R_{C2}\right)}& 0& 0\\ 0& 0& 0& \frac{1}{C_{o1}}& 0\\ 0& \frac{-\left(1-d\right)}{C_{o2}\left(R_{C1}+R_{C2}\right)}& \frac{1-d}{C_{o2}\left(R_{C1}+R_{C2}\right)}& 0& \frac{1}{C_{o2}}\end{array}\right]$$

(37)

Based on the derived state−space equation, the sensitivity analysis for the voltage error of (v₁ − v₂)/v₁ was performed. The percentage impacts of ±10% component tolerance were investigated based on both the state−space equation and the simulation analysis. Results are shown in the form of a tornado diagram in Figure 11 and typical values and analysis conditions are listed in the inset. The theoretical and simulation results were in good agreement, verifying the derived state−space equation. The results indicated the diode forward voltage drops of V_f1 and V_f2 were the largest source of the voltage error. If V_f1 increased by 10%, for example, the voltage error would be −1.8%. The impact of the component tolerance of inductances and capacitances was minor because cell voltages are theoretically independent of these parameters, as indicated by (20) and (29). In summary, component tolerances showed a minor impact on the voltage error, suggesting that cell voltages can be equalized well by the proposed integrated charger even without carefully screening circuit components.

4. Design Example

The proposed integrated charger for four EDLCs and low-power ac adaptors with V_in = 19.5 V is exemplified in this section. The design target is P_in = 12 W (i.e., I_Lin < 0.62 A), V_st > 6 V, V_i = 1.2–2.5 V, and f_s = 50 kHz (T_s = 20 µs).

To ensure DCM operations, (31) must be satisfied, yielding

$$\frac{1.2\mathrm{V}+0.3\mathrm{V}}{19.5\mathrm{V}-6\mathrm{V}+1.2\mathrm{V}+0.3\mathrm{V}}>d=0.1$$

(38)

The combined inductance L_x can be determined from (23), as

$$I_{Lx}=\frac{{0.1}^2\times 20\mathsf{\mu }\mathrm{s}\times \left(19.5\mathrm{V}-6\mathrm{V}\right)}{2\times 0.62\mathrm{A}}\approx 2.2\mathsf{\mu }\mathrm{H}$$

(39)

Given L_in = L_i for the sake of design simplicity, (22) yields

$$L_{in}=L_i=5\times 2.2\mathsf{\mu }\mathrm{H}=11\mathsf{\mu }\mathrm{H}\to 10\mathsf{\mu }\mathrm{H}$$

(40)

C_i needs to be sufficiently large to ensure that the resonance between L_i and C_i does not occur. To this end, C_i is determined such that the resonant frequency is lower than one-fifth of f_s.

$$\frac{f_s}{5}=\frac{1}{2\pi \sqrt{L_i{C}_i}}\to C_i=36\mathsf{\mu }\mathrm{F}$$

(41)

5. DC Equivalent Circuit and Its Simulation Results

5.1. Derivation of DC Equivalent Circuit

The operation analysis in Section 3.2 and Section 3.3 derived the average inductor currents and revealed that the sum of I_L1–I_L4 is independent of whether the cell voltages are balanced or imbalanced. A dc equivalent circuit of the superbuck-based integrated charger can be derived by expressing inductors as a constant current source, as shown in Figure 12. Current sources of I_Lin and I_L1–I_L4 obey (23) and (30), respectively. To generate a seamless transition between (21) and (30), I_L1–I_L4 are connected in parallel through an ideal multi-winding transformer. Under voltage-balanced conditions, I_L1–I_L4 flow toward B₁–B₄ through their respective diodes. On the other hand, under voltage-imbalanced conditions, all of I_L1–I_L4 go to the least charged cell via the multi-winding transformer.

5.2. Simulation-Based Equalization

A simulation-based equalization test using the derived dc equivalent circuit was performed for four cells connected in series. 400-F capacitors were used as cells. I_Lin and I_L1–I_L4 were programmed to obey (23) and (30), respectively, and component values for an experimental prototype (see

Table 2. Component values used for prototype.

Component	Value, Part Number
Q	N-Ch MOSFET, ZXMN4A06GTA, Ron = 75 mΩ
Lin, L1–L4	10 µH, 33 mΩ
Cin	Aluminum Electrolytic Capacitor, 330 µF
C1–C4	Ceramic Capacitor, 36 µF
D1–D4	Schottky Barrier Diode, SL44, Vf = 0.35 V
Co1–Co4	Ceramic Capacitor, 300 µF
Gate Driver	L6741

) at a switching frequency of 50 kHz with d = 0.1 were used for the simulation. The series-connected cells were charged to be a CV of 10.0 V (2.5 V/cell).

The charging profiles are shown in Figure 13. The input current I_in steadily decreased as V_st increased [see (23)]. Equalization currents, or I_L1–I_L4, flowed toward cells, but their magnitudes were dependent on cell voltages. At the beginning of the charging, B₄ received the largest equalization current in the form of I_L4, and V₄ increased faster than others. The voltage imbalance was gradually eliminated as the charging progressed, and all the cells were uniformly charged to 2.5 V after V_st reached the CV charging level of 10.0 V.

6. Experimental Results

6.1. Prototype and Its Characteristics

A 12-W prototype for four cells connected in series was built, as shown in Figure 14. Circuit elements used for the prototype are listed in Table 2. The prototype was driven at f_s = 50 kHz with V_in = 19.5 V and fixed at d = 0.2 to ensure the DCM operations.

6.2. Characteristics of Integrated Charger Alone

Output characteristics of the prototype were measured using the experimental setup shown in Figure 15. Instead of using actual EDLC cells, two voltage loads were used to emulate voltage-imbalanced conditions. The upper load was a CV load, while the lower one was a variable voltage (VV) load to emulate low-voltage cells. For example, Tap 1 emulates the imbalanced case where V₁ is the lowest—Tap 1 emulates the operation modes in Figure 7. The CV load is set at 7.5 V (2.5 V/cell), and the VV load is swept in the range of 1.2–2.5 V. Tap 2, on the other hand, emulates the case in which both V₁ and V₂ are the lowest. The CV load voltage is fixed at 5.0 V (2.5 V/cell) while sweeping the VV load in the range of 2.4–5.0 V (1.2–2.5 V/cell). The operation modes under the voltage-balanced condition (see Figure 9) can be emulated by selecting Tap 4, through which the CV load is short-circuited, and the entire string is connected to the VV load.

The measured key operation waveforms when V₁ = 1.2 V are shown in Figure 16, where v_GS is the gate-source voltage. Oscillations in v_DS were due to the parasitic capacitance of the MOSFET. When Tap 1 was selected (Figure 16a), the average of i_L1 was substantial, whereas those of i_L2–i_L4 were uniform and zero. These measured waveforms agreed well with the theoretical ones shown in Figure 6. In the cases where Taps 2 and 3 were selected (see Figure 16b,c), i_L1 and i_L2 were uniform and their averages were greater than zero, whereas the averages of the other inductor currents were zero. When Tap 4 was selected to emulate the voltage-balanced condition, i_L1–i_L4 were uniform.

Measured power conversion efficiencies as a function of V₁ are shown in Figure 17—V₁ corresponds to the least charged voltage in practical use. Measured efficiencies monotonically increased with V₁ as the portion of the output voltage taken by the diode voltage drops decreased. Since the output voltage was low (<2.6 V), diode forward voltage drops took a significant portion of the output voltage V₁, resulting in poor power conversion efficiencies of <90%. The efficiencies varied depending on the selected tap, probably because the number of conducting diodes differed depending on whether cell voltages were balanced—only one diode conducts in the case of tap 1 (see Figure 7b), whereas all diodes conduct in the case of tap 4 (Figure 9b). These results suggest that the proposed integrated charger is not suited for high-power applications where efficiency maximization is prioritized over the circuit simplification, as mentioned in Section 2.3.

6.3. Charging Test for EDLCs

Four EDLCs, each with a capacitance of 400 F at a rated charging voltage of 2.5 V, were charged using the prototype with d = 0.1. Initial cell voltages were imbalanced between 1.2 and 1.8 V. The CV charging voltage level was set to be 10.0 V (2.5 V/cell).

The resultant charging profiles are shown in Figure 18a. The voltage imbalance was gradually eliminated as the charging progressed, and all the cell voltages were satisfactorily equalized in the CV charging period. The standard deviation (SD) of cell voltages decreased to values as low as 11 mV at the end of the charging test, demonstrating the equalization performance of the proposed integrated charger.

Only the diode D₁ was replaced with the one with V_f = 0.4 V in order to investigate the impact of component tolerance on the voltage equalization performance—The V_f of other diodes was 0.35 V, as shown in Table 2. The results of the charging test are shown in Figure 18b. Even with the mismatched V_f of D₁, the voltage imbalance adequately disappeared, and all the cells were uniformly charged to 2.5 V in the CV charging period. The SD at the end of the CV charging was 25 mV, which was slightly larger than the case shown in Figure 18a. Although slightly increased, the results demonstrated the minor impact of the component tolerance on the equalization performance.

The experimental results agreed very well with the simulation results shown in Figure 13, verifying the derived dc equivalent circuit (see Figure 12).

7. Conclusions

A family of single-switch transformerless integrated chargers have been proposed in this paper. The proposed chargers can be derived from stacking multiple PWM converters that contain two inductors and one energy transfer capacitor. The superbuck converter-based topology, which is considered best suited for energy storage applications, was analyzed under voltage-balanced and -imbalanced conditions.

The impact of component tolerance on voltage equalization performance of the integrated charger for two cells was analyzed based on the state−space modeling. The analytical results revealed that the mismatch in diode forward voltage drop was the most influential factor, but ±10% tolerance results in merely 1.8% voltage error, suggesting no significant impact due to component tolerance on the voltage equalization performance.

The 12-W prototype for four cells connected in series was designed and built for the experimental verification tests. Series-connected EDLCs were charged in voltage-imbalanced conditions. All the cells were charged to uniform voltage levels while eliminating voltage imbalance, demonstrating the voltage equalization performance of the proposed integrated charger.