Self-Balancing Supercapacitor Energy Storage System Based on a Modular Multilevel Converter

Abstract

Energy Storage Systems (ESS) are an attractive solution in environments with a high amount of renewable energy sources, as they can improve the power quality in such places and if required, can extend the integration of more renewable sources of energy. If a large amount of power is needed, then supercapacitors are viable energy storage devices due to their specific power, allowing response times that are in the range of milliseconds to seconds. This paper details the design of an ESS that is based on a modular multilevel converter (MMC) with bidirectional power flow, which reduces the number of cascaded stages and allows the supercapacitors SCs to be connected to the grid to perform high-power transfers. A traditional ESS has four main stages or subsystems: the energy storage device, the balancing system, and the DC/DC and DC/AC converters. The proposed ESS can perform all of those functions in a single circuit by adopting an MMC topology, as each submodule (SM) can self-balance during energy injection or grid absorption. This article analyses the structure in both power flow directions and in the control loops and presents a prototype that is used to validate the design.

1. Introduction

Supercapacitors (SCs) have the highest power density relative to Li-ion batteries, flywheels, fuel cells, and superconducting magnetic energy storage systems [1,2]. Although SC technology is still maturing, this high-power density comes with a cost, namely that SCs are usually low voltage devices, usually around 2.5 V to 3.0 V [3]. This problem can be overcome by using series connections with passive or active balancing systems, the latter being more efficient [4,5]. However, in terms of design, this added circuitry creates a more complex and expensive Energy Storage System (ESS) that is also susceptible to failure because of the many parts that are involved in the system [6,7]. Typical applications of SC-based ESSs are related to fast energy injection or absorption [8,9]. For example, in isolated microgrids with a high penetration of renewables [10], SCs maintain the power balance between consumption and generation because inertia mechanisms are limited. SCs can also be used in conjunction with batteries to create a hybrid ESS, increasing the capabilities of the system [11].

A basic SC-based ESS is composed of a balancing system, SC cells, a DC/DC converter, a DC link capacitor, and a DC/AC converter, as Figure 1 shows [8,12]. An ESS needs to keep energy storage devices balanced, protect them from overvoltage, and create the output voltage using bidirectional DC/DC and DC/AC conversions. The SC voltage changes linearly along with the state of charge, so a DC/DC converter with a wide input voltage range and a constant DC output voltage tends to be needed [13]. A DC link connects the DC/DC converter to a traditional DC/AC converter, which creates an AC signal. In addition, as galvanic isolation is important when the ESS is connected to the grid, a bulky 50Hz transformer must be used if none of the other stages has isolation, which increases the converter’s size. Each of these circuits or stages requires a careful design process in order to accomplish the power budget.

Some authors have been studying different DC/DC converter topologies for ESS that can be used for DC microgrids or for AC grids. In [14,15], the proposed converter lacks isolation, limiting its applications. In [16], an optimized supercapacitor control strategy in combination with a Double Active Bridge (DAB) is proposed, but an active or passive balancing system as well as a DC/AC inverter are still required to interact with the grid. In [17,18], the proposed converters can directly interface the energy storage device with the AC grid; however, it still requires an additional balancing system.

Instead of the traditional approach, a Modular Multilevel Converter (MMC) can be used, which is based on a high-voltage DC source and a series of submodules (SMs). In this system, DC/DC and DC/AC conversions are performed in the SMs, which consist of DC/DC converters. These MMC topologies have been used for high-voltage DC transmission [19,20]. One of the main advantages of MMCs is the simplicity of scaling up the voltage of the system by adding more SMs to the MMC [21], as shown in Figure 2a.

The relevant aspect of this work is the integration of a single SC in each of the SMs, and therefore, no high voltage DC source is needed. In addition, each SM works in a voltage range of 1.5–2.7 V, which allows the use of low-voltage switches with low conduction losses [22] and a low total harmonic distortion (THD) of the AC output voltage and current possible.

Other authors have studied low-voltage MMC [23], for example, for railway traction systems, in which each supercapacitor is integrated in every SM, but these applications have only been studied analytically [22]. Low-voltage MMC was also studied for its potential use in STATCOMs applications by incorporating the ESS into the MMC; however, this was only possible by adding an additional DC/DC converter [24]. The same occurs in power traction converters, where for adding SCs, a DC/DC converter was added [25]. In [26], the proposed MMC integrates the SCs in each SM, and a balancing strategy is presented; however, the ESS requires a bulky transformer if isolation is required.

This paper proposes an SC-based ESS using an MMC in which each SM contains an energy storage device (a single SC) and a bidirectional isolated DC/DC converter. The proposed MMC diagram is shown in Figure 2b. The DC/DC converter acts a controllable DC voltage source. Thus, the MMC becomes a series chain of controllable voltage sources and, with the correct control strategy, the SMs can create an AC output signal: v_MMC(t). Therefore, the main contribution of this research is the development of an ESS that is based on an MMC that can perform the functions of energy storage, voltage balancing, and bidirectional DC/DC and DC/AC conversion with galvanic isolation in a single block (or SM), resulting in a self-balancing MMC that is easily expandable to higher voltages and that is controllable with a central controller. A prototype validates the proposed ESS, and the prototype shows how the circuit works; however, the efficiency is not optimized and can be further improved through the use of GaN or SiC transistors.

This paper is structured as follows. Section 2 presents SM operation in both power flow directions. Section 3 details the MMC operational modes and the self-balancing control that is embedded in each SM. Section 4 presents the simulations of the proposed SC-based MMC, which validates the described operational modes in Section 3. Section 5 describes the experimental tests and a comparison with other converters in terms of efficiency and the stages that are involved. Finally, Section 6 concludes the paper.

2. Submodule Operation

The DC/DC converter in the SM is a bidirectional full-bridge topology with an active clamp and a low pass filter (L₁–C₁), as shown in Figure 3. This topology has ease of control and design as well as galvanic isolation. It allows bidirectional current flow from/to the SC ($V_{SC}$) to/from the load (V_o). This converter offers soft-switching capabilities and uses synchronous rectification and an active clamp (C_c, Q_c) to reduce the voltage stress in the switches. Figure 3a shows that the SC is attached to the 1st bridge (Q₁ to Q₄), isolation is provided by transformer T₁, and Q₅ to Q₈ are used in the boost side (2nd bridge). This topology was first proposed in [27].

2.1. Buck-Mode ($V_{SC}$_C → V_o)

The circuit can be analyzed by taking five-time intervals (from t₁ to t₆) in one half of a switching period ($T_S$). The duty cycle for Q₁, Q₂, Q₃, and Q₄ is fixed at 50%, and the phase shift ($\varphi$) between legs Q₁, Q₃ and Q₂, Q₄ is the control variable.

The main buck-mode waveforms are presented in Figure 4. Before the first-time interval (before $t_1$), Q₁ and Q₂ are on, and Q₃, Q₄, and Q_c are off. This means that the voltage in the transformer’s primary winding is zero (v_tp = 0). The 2nd bridge (Q₅–Q₈) is conducting at the same time. The diodes from Q₅–Q₈ are on, and the synchronous rectifiers (Q₅ and Q₆) are working, so the transformer’s secondary voltage (v_ts) is zero and ${v^{\prime }}_c$ = 0, but $V_{Cc} \approx$ n·$V_{SC}$, where n is the transformer turn ratio. Therefore, there is no energy transfer from the primary to the secondary winding of the transformer. In addition, $i_{L_{lk}}$ = 0 due to the previous cycle. The inductor current ($i_{L1}$) flows through the 2nd bridge and through the load. As ${v^{\prime }}_c$= 0 and $v_{Cc}$ > 0, $i_{Cc}$ = 0 (diode of Q_C is blocking). This initial condition is the final condition in the last time interval of the previous half-cycle.

In the 1st time interval, [$t_1,t_2$], Q₁, and Q₄ are on, Q₃ and Q_c are off, and $v_{L_{lk}}$ = $V_{SC}$. As $i_{L_{lk}}$(t₁) = 0, Q₂ turns off at the zero current and Q₄ also turns on at the zero current. $L_{lk}$ governs the current slope during the transition. Thus, both transitions occur during soft switching.

In the 2nd bridge, $i_{L1}$ is still flowing through the 2nd bridge diodes and synchronized rectifiers (Q₅ and Q₈), so ${v^{\prime }}_c$ = 0. This is equivalent to the off-time in the continuous mode for a buck converter, so the L₁ current follows:

$$i_{L1}(t)=i_{L1}(t_1)-\frac{V_o}{L_1}(t-t_1),$$

(1)

because ${v^{\prime }}_c$ = 0, this is valid from t₁ to t₂. $i_{L_{lk}}$ continues to increase until the current in the secondary winding (i_ts) reaches $i_{L1}$ and the diodes of Q₆ and Q₇ turn off. Therefore, for the 1st time interval, the $i_{L_{lk}}$ current is governed by:

$$V_{SC}=L_{lk}\frac{d{i}_{L_{lk}}}{dt},$$

(2a)

which can be rewritten as:

$$i_{L_{lk}}=\frac{V_{SC}}{L_{lk}}(t-t_1).$$

(2b)

The time interval ends when $i_{L_{lk}}$ (t₂) = n·$i_{L1}$(t₂). At that moment, the 2nd time interval starts [$t_2,t_3$]. Q₂, Q₃, and Q_C are still off and Q₁ and Q₄ are still on (so there are no switching transitions between the 1st and 2nd intervals). Q₆ and Q₇ and their diodes are already off, and Q₅ and Q₈ are on. The diode of Q_C starts conducting, so ${v^{\prime }}_c$ jumps to $v_{Cc}$(t₂), which is a value that is slightly lower than n·$V_{SC}$, resulting in C_C being charged. The equations that govern the 2nd time interval are (considering L_mag >> $L_{lk}$ and n²$L_{lk}$ << L₁); for $i_{L_{lk}}$, we first subtract the charging voltage ${v^{\prime }}_c/n$:

$$V_{SC}-\frac{{v^{\prime }}_c}{n}=L_{lk}\frac{d{i}_{L_{lk}}}{dt},$$

(3a)

then $i_{L1}$ starts to increase following:

$${v^{\prime }}_c-V_o=L_1\frac{d{i}_{L1}}{dt},$$

(3b)

The charging current $i_{Cc}$ is described by:

$$i_{Cc}=C_c\frac{d{v^{\prime }}_c}{dt},$$

(3c)

Hence, the relationship between $i_{lk}, i_{Cc},$and $i_{L1}$ is:

$$\frac{i_{lk}}{n}-i_{Cc}=i_{L1},$$

(3d)

Finally, the solution for $i_{L1}$ can be obtained:

$$i_{L1}\cong i_{L1}(t_2)+\frac{n·V_{SC}-V_o}{L_1}(t-t_2)+\frac{L_{lk}{n}^2}{L_1}.V_o.(t-t_2)-\frac{n·V_{SC}+\frac{L_{lk}{n}^2}{L_1}.V_o-v_{Cc}^{}(t_2)}{{\omega }_0{L}_1}sin({\omega }_0(t-t_2)),$$

(4)

where the resonant frequency is ${\omega }_0={\left[C_c{n}^2{L}_{lk}\right]}^{-1}$. ${v^{\prime }}_c$, i_Cc, and $i_{L_{lk}}$ can be derived from (3) using (4). Notice that if $n·V_{SC}-v_{Cc}^{}(t_2)$ is small, ${\omega }_0(t_3-t_2)<<1$, and considering $n^2{L}_{lk}\ll L_1,$the last two terms of (4) can be neglected. Thus (4) is the same as in the on-time of a buck converter.

This time interval ends when Q₁ is turned off and when the 3rd time interval, [$t_3,t_4$], starts. The $i_{L_{lk}}$ flows through the diode of Q₃ and Q_4, and Q_C is on. Again considering ${\omega }_0(t_4-t_3)<$<1):

$$i_{L1}(t)\cong i_{L1}(t_3)+\frac{v_{Cc}(t_3)-V_o}{L_1}(t-t_3).$$

(5)

As $v_{Cc}(t_3)\approx n·V_{SC}$, (5) follows the on-state of a buck converter. C_C delivers energy to reset $L_{lk}$ ($i_{L_{lk}}$ = 0). Then, C_c should have at least enough energy to reset $L_{lk}$. This puts a lower limit on C_C:

$$\frac{L_{Lk}{i}_{Lk}^2(t_3)}{2}<\frac{C_c(v_{Cc}^2(t_3)-v_{Cc}^2(t_4))}{2},$$

(6a)

which for design purposes is:

$$C_C\gg \frac{L_{Lk}{I}_{0\max }^2}{V_{SC\min }^2},$$

(6b)

where the low current ripple ($I_o$ = $i_{L_{lk}}$(t₃)/n) and $v_{Cc}$(t₃) = n·$V_{SC}$, and min and max are the maximum and minimum design values.

In the 4th time interval, [$t_4,t_5$], Q_C, Q₄ are on but $i_{L_{lk}}$ = 0, so the diode of Q₃ is off, and C_C is feeding L₁. As this interval is short, ${\omega }_0(t_5-t_3)<<1$, so the ${v^{\prime }}_c$ and $i_{L1}$ are:

$${v^{\prime }}_c(t)\cong {v^{\prime }}_c(t_4)-\frac{i_{L1}(t_4)}{C_c}(t-t_4)$$

(7a)

$$i_{L1}(t)\cong i_{L1}(t_4)+\frac{{v^{\prime }}_c(t_4)-V_o}{L_1}(t-t_4).$$

(7b)

Thus, if ${v^{\prime }}_c(t_4)\cong n·V_{SC}$, the buck converter equation remains. To achieve that, C_C should be big enough to not be completely discharged by $L_{lk}$, as proposed by (6).

In the 5th time interval, [$t_5,t_6$], Q_C is turned off, the diodes of Q₅–Q₈ turn on, and right after that, Q₇ turns on at zero voltage. Then, Q₃ can turn on when the current and voltage are zero (soft switching). Thus, ${v^{\prime }}_c$ goes to zero, and $i_{L1}$ behaves as an off-time buck converter.

To summarize, the first-time interval is off-time, the second, third, and fourth are on-time intervals, and the fifth is an off-time interval. The voltage transfer function can be obtained as it was in the buck converter when ${v^{\prime }}_c(t_2)\cong {v^{\prime }}_c(t_3)\cong {v^{\prime }}_c(t_4)\cong {v^{\prime }}_c(t_5)=n{V}_{SC}$:

$$M=\frac{V_o}{V_{SC}}\cong n\frac{t_5-t_2}{\frac{T_S}{2}}\approx n2\varphi$$

(8)

This mode is called buck-mode because M approximately follows the same equation as the buck converter; M varies linearly with the control variable $\varphi$, where controlling $\varphi$ is sufficient to control the amount of energy that is transferred from the supercapacitor to the grid.

In order to control the SM, a small-signal analysis is performed. Let us simplify the time-interval analysis to only two main intervals. One from t₂ to t₅, where ${v^{\prime }}_c$ = $n$ $·V_{SC}$, called on-state, and the other with the rest of the intervals, where ${v^{\prime }}_c$ = 0, which is called the off-state. The state model for the on-state is (t₅ − t₂) = $\varphi$T_S:

$$\frac{d}{dt}\left[\begin{array}{c}{i}_{L1}\\ v_o\end{array}\right]=\left[\begin{array}{cc}0& -1/L_1\\ 1/C_1& -1/(R{C}_1)\end{array}\right]\times \left[\begin{array}{c}{i}_{L1}\\ v_o\end{array}\right]+\left[\begin{array}{c}1/L_1\\ 0\end{array}\right].n\times v_{SC}.$$

(9)

For the off-state, it is (1-$\varphi$)T_S:

$$\frac{d}{dt}\left[\begin{array}{c}{i}_{L1}\\ v_o\end{array}\right]=\left[\begin{array}{cc}0& -1/L_1\\ 1/C_1& -1/(R{C}_1)\end{array}\right]\times \left[\begin{array}{c}{i}_{L1}\\ v_o\end{array}\right]+\left[\begin{array}{c}1/L_1\\ 0\end{array}\right].0.$$

(10)

Therefore, using the averaging approach during T_S/2, the complete model is obtained:

$$\frac{d}{dt}\left[\begin{array}{c}{i}_{L1}\\ v_o\end{array}\right]=\left[\begin{array}{cc}0& \frac{-1}{L_1}\\ \frac{1}{C_1}& \frac{1}{R{C}_1}\end{array}\right]\times \left[\begin{array}{c}{i}_{L1}\\ v_o\end{array}\right]+\left[\begin{array}{c}\frac{1}{L_1}\\ 0\end{array}\right].2\varphi .n\times v_{SC},$$

(11)

where the < > represents the average in one switching period, and $\varphi$ is shown in Figure 4. In addition, to obtain the small signal model, the variables are: $x=X+\widehat{x}$, where X is the average value and $\widehat{x}$ is the small signal perturbation. Thus, the model in (11) becomes:

$$\frac{d}{dt}\left[\begin{array}{c}{I}_{L1}+{\widehat{i}}_{L1}\\ V_o+{\widehat{v}}_o\end{array}\right]=\left[\begin{array}{cc}0& \frac{-1}{L_1}\\ \frac{1}{C_1}& \frac{1}{R{C}_1}\end{array}\right]\times \left[\begin{array}{c}{I}_{L1}+{\widehat{i}}_{L1}\\ V_o+{\widehat{v}}_o\end{array}\right]+\left[\begin{array}{c}\frac{2}{L_1}\\ 0\end{array}\right].(\varphi +\widehat{\varphi }).n(V_{SC}+{\widehat{v}}_{SC}),$$

(12)

then, by considering the perturbations on their own and by linearizing the model, the following expression can be obtained:

$$\frac{d}{dt}\left[\begin{array}{c}{i}_{L1}\\ {\widehat{v}}_o\end{array}\right]=\left[\begin{array}{cc}0& \frac{-1}{L_1}\\ \frac{1}{C_1}& \frac{1}{R{C}_1}\end{array}\right]\times \left[\begin{array}{c}{\widehat{i}}_{L1}\\ {\widehat{v}}_o\end{array}\right]+\left[\begin{array}{c}\frac{1}{L_1}\\ 0\end{array}\right].n.(\varphi .{\widehat{v}}_{SC}+V_{SC}\widehat{\varphi }),$$

(13)

Finally, the Laplace transformation can be used as an output function of the control (control-to-output), and the input voltage can be obtained:

$$\widehat{v_o}(s)=\frac{n\times (\varphi \times {\widehat{v}}_{SC}+V_{SC}\widehat{\varphi })}{s^2{L}_1{C}_1+s\frac{L_1}{R}+1}=\frac{n.(\varphi \times {\widehat{v}}_{SC}+V_{SC}\widehat{\varphi })}{{(\frac{s}{{\omega }_0})}^2+\frac{s}{Q{\omega }_0}+1}.$$

(14)

Thus, based on the control-to-output transfer function, a controller must be selected in order to provide in the output a DC signal plus an AC 50 Hz signal. Therefore, a bandwidth of at least 500 Hz is needed for the SM in order to be considered as an ideal transfer function by a high-level controller, in this case the MMC main controller. A voltage mode controller was selected due to its simplicity, but a current mode controller can be utilized as well. To increase the bandwidth of the DC/DC converter a type-III controller was used with the following transfer function:

$$G_C(s)=K\frac{(sT+1)}{sT}\times \frac{(s\alpha /{\omega }_c+1)}{\frac{s}{\alpha {\omega }_c}+1}\times \frac{1}{\frac{s}{{\omega }_{LPF}}+1},$$

(15)

The type-III controller consists of a PI controller, defined by K and T, a lead-lag controller, defined by $\alpha$ and ${\omega }_c,$and a low pass filter with ${\omega }_{LPF}$as the cut-off frequency. Therefore, the closed loop system to control the output voltage, according to Figure 3b, is:

$$G_{Cl}(s)=\frac{\widehat{v_o}}{\widehat{v_{ref}}}(s)=\frac{G_C(s)\frac{\widehat{v_o}}{\widehat{\varphi }}(s)}{1+G_C(s)\frac{\widehat{v_o}}{\widehat{\varphi }}(s)}\cong \frac{1}{1+\frac{s}{Q{\omega }_f}+\frac{s^2}{{\omega }_f{}^2}}$$

(16)

In order to obtain that transfer function, the controller must have ${\omega }_c={\omega }_0.(1.1)$, ${\omega }_{LPF}=\pi f_s$and $\alpha =2.1$ to have almost 50° of phase margin at around 10 kHz and K = 1.5 and T = 0.0005. This way, the MMC main controller will consider the SM with a simple transfer function and the control dynamics will not be coupled. Figure 5 shows the SM Bode plot with the described type-III controller and the MMC using a simple PI controller which is sufficient for a 50 Hz or 60 Hz sinusoidal output.

2.2. Boost-Mode (V_o → $V_{SC}$)

In this mode, energy is extracted from the grid and charges the SC. By controlling the boost voltage, it is possible to extract power from very low input voltage levels, such as those found in a sinusoidal wave close to the zero crossing. In this case, the active bridge is Q₅–Q₈ and the synchronous rectifier bridge is Q₁–Q₄. A complete analysis can be done using the same procedure as in the buck mode, here a simple analysis is presented only in order to obtain the voltage conversion ratio, based on the simulated waveforms of Figure 6. As in the buck mode, i_L1 is triangular, it is charged when ${v^{\prime }}_c$ = 0 and discharged when ${v^{\prime }}_c$ ≈ $n$ $·V_{SC}$. Thus, as L₁ in this direction is in the “input” side (V_o) and ${v^{\prime }}_c$ reflects the “output” side ($V_{SC}$), this behavior matches a boost converter with a voltage conversion ratio of:

$$M=\frac{V_{SC}}{V_o}=\frac{T_S/2}{(t_3-t_1).n}\approx \frac{\frac{T_S}{2}}{(1-D)T_S\times n}=\frac{0.5}{(1-D)\times n},$$

(17)

where the time interval for transfer the energy to the “output” corresponds to the off-time of the boost converter, which is approximately t₃–t₁, and the total time is $T_S$/2 (converter’s energy transfer period is half of the sampling period). Finally, from Figure 6, t₃–t₁ = $(1-D)T_S/2$. A more detailed analysis can be found in [28].

3. Modular Multilevel ESS

In the present work, only a single-phase converter is considered, but this can be extended to a three-phase system by repeating the structure. The proposed modular multilevel ESS is composed of SMs in series, which work as voltage sources, each of them including the DC/DC converter from Section 2 and an energy storage device (SC). This allows the discharge current to be perfectly controlled; this way, the SCs can be balanced using the same DC/DC converter. This section aims to show all of the functions of each submodule inside the MMC.

3.1. Energy Storage Device

The submodule includes the energy storage itself, so it is capable of delivering and absorbing energy using the SC. In this proposal, the energy storage device is a SC, but it can be replaced by a battery in EV applications or islanded microgrids with a high number of renewable sources.

3.2. DC/DC Conversion with Galvanic Isolation

The submodule includes an isolated DC/DC converter with a variable output voltage range. The converter’s output can fluctuate from values that are close to zero to positive values; in the present application, it goes from 1 V to 20 V (at V_SC = 2.7 V). The module provides an AC output signal with a DC offset. Then, combining half of the SMs in one direction and the other half in the opposite direction, as shown in Figure 2b, the DC offset is cancelled, and a pure AC signal is obtained.

From the point of view of control, the MMC includes two control levels with two controllers: one controller inside each SM, which follows a voltage reference in the discharge direction (buck-mode) and a current reference in the charge direction (boost-mode), and one master controller, which measures the MMC’s output signals and controls the energy transfer to the grid or load. In addition, the SM controller performs the balancing of the SCs (detailed in Section 3.3) and establishes the protection limits.

In the discharge direction, see Figure 7, the SM measures the output voltage, the SC voltage, and current, and it controls the output voltage. The control loop is based on a type-III controller, which was designed in Section 2.

In the charge direction, see Figure 8, the DC/DC controls the SC current and keeps the SC voltage within the limits. The type-III controller is limited when the voltage of the SC is approaching its maximum. The comparator creates the PWM signals and the $T_S/2$ delay, and the NOR gate creates the switching pulses.

3.3. Balancing Method

In order to simplify the control of the whole MMC and to add minimal circuitry to sense and control the SMs, the balancing of the SCs is conducted locally in each SM instead of giving this task to the master controller. Therefore, many SMs can be connected in series without increasing complexity in the control algorithm, as self-balancing is achieved at the SM level.

At hardware level (see Section 5), each SM is composed of a Microcontroller Unit (MCU) and all of the components that are required for operation. By taking advantages of this MCU, an integrated control can be implemented in such a way that the output power can be slightly adjusted for each SM in order to increase or decrease it. Thus, The SCs can be balanced without recirculating energy from one another. This is the main benefit of the proposed balancing control since any other active balancing system relies on the need to transfer the exceeding energy to another SC, and if the system is simple, then this energy might not be directly injected to the lowest voltage SC cell [4].

SCs are balanced when working in the buck-mode. Each SM measures its own SC voltage ($V_{SCn}$) and two adjacent SC voltages ($V_{SCn-1}$ and $V_{SCn+1}$), as shown in Figure 9. Thus, the DC/DC converter controller checks whether the SC is over or under the average voltage of this local measurement.

An error signal is defined as:

$$\epsilon =\frac{3\times V_{SCn}}{V_{SCn+1}+V_{SCn}+V_{SCn-1}}-1,$$

(18)

Finally, the reference for the output voltage of the n-th SM is:

$$V_{REFn}=V_{REF}+\underset{∆vn}{\underbrace{V_{REF}K\epsilon }},$$

(19)

where K is the proportional gain to limit $∆vn$ to around 10% of the reference value $V_{REF}$. This means that $∆vn$ can be slightly higher or lower than zero, and it is then added to $V_{REF}$, generating an individual $V_{REFn}$ = $V_{REF}$ + $∆vn$ for the n-th SM. As each SM controller is based on an MCU, these calculations are included in the SMs, as illustrated in Figure 9. In the boost-mode, the same method can be used if $∆in$ is added to $I_{REF}$.

3.4. DC/AC Conversion

Figure 2b shows two branches of SMs, the top and the bottom. The top branch delivers the positive half sinewave, and the bottom branch delivers the negative half sinewave. The master controller needs to sense the output voltage and current of the MMC (v_MMC and i_MMC) to properly command the whole array of SMs by sending only two variables to each SM: the operation mode (buck or boost-mode) and $V_{REF}$ (for buck-mode) or $I_{REF}$ (for boost-mode). These signals are sent to every SM in the corresponding active branch.

The master controller combines two 180° sinusoidal signals to achieve the DC/AC conversion. Figure 10 shows the controller details. In the proposed approach, the dq-frame method was used. The phase-locked loop (PLL) block obtains the grid angle and frequency [29] in order to extract the DC component to a low pass filter using a cut-off frequency of 5 Hz. The dq block includes the low pass filter, the DC signal, and the orthogonal signals, so its outputs are the dq signals and the DC component: dq0 signals.

The main controller shown in Figure 10a consists of three PI controllers: two of them for the dq components and one more to minimize the DC value and the cross i_d–i_q coupling elements (see Figure 10b). The resultant signal is processed and is divided by the number of SMs and is shifted by 180° to provide the signals to the lower half of the SMs. In order to clarify the control loop and to design the controller parameters, the d-axis control loop is shown Figure 10b. The PI values can be obtained by cancelling the r_C–L_C pole with the PI zero at −1/τ and by finally selecting K in order to provide stability and decent bandwidth. For this case, K/(r_C·τ) = ${\omega }_0/10$ was selected, where ω₀ was 2·π·10 kHz.

3.5. Grid Connection with Bidirectional Power Flow

As the converter can work in buck or boost-mode, Figure 11 shows a flow diagram that explains how the mode selector works. To absorb power, the DC/DC converter in each SM can operate in boost or buck-mode. In boost-mode, an I_REF signal is used to control the amount of power that is absorbed from the grid. It is preferable for only active power to be absorbed when working in the boost-mode, mainly because the losses can be higher when reactive power is being absorbed.

The mode selector retrieves the SC voltage from any SM (since all of them should be balanced automatically) and checks whether the voltage is lower than a predefined value (1.5 V in this case). If so, the boost-mode is activated to absorb active power from the grid and to recharge the SCs. This voltage level was selected to charge the SCs when they are close to their lowest limit and when they can no longer deliver energy in the buck-mode. After charging the SCs and once they reach a valid working level (2.25 V), the master controller selects the buck-mode. The buck-mode works in a voltage-controlled scheme, where the controller supervises v_MMC and i_MMC (Figure 7 and Figure 10) and where each SM can deliver or absorb active or reactive power by controlling i_d or i_q.

Since the proposed ESS is based on a series chain of DC/DC converters, it can also be used in DC microgrids, and as mentioned before, if batteries are the primary energy storage device, then a different control strategy can be used [30,31]. The present work is limited to demonstrating the capabilities of the proposed ESS, and more advanced control techniques should be addressed in future work.

4. Simulation Results

The ESS design was validated using a PSIM simulator. Four simulations were performed for a total of 62 SMs (31 SMs for each branch, top and bottom) to obtain an output voltage of 220VAC at 50 Hz.

Table 1. Components used for simulation and prototype tests.

Component	Value	Details
SC	10F PSIM and 3000F prototype	ESR = 0.4 mΩ
Q1 to Q4	3 × BSC009NE2LS5	rDS(on) = 0.9 mΩ
Q5 to Q8 and Qc	2 × BSC022N04LS6	rDS(on) = 2.2 mΩ
T1 core and LMAG	5.7 µH	ELP32, N87 material
Turns ratio	1:8	-
CC	6 × 0.068 µF in parallel	0805 X7R
L1	10 µH	EPCOS B82559
C1	2 × 100 µF in parallel	Solid tantalum
TS	10 µS	1/TS = Fsw = 100 kHz
LC	1 mH	Coupling inductor

shows the components for each SM and the coupling inductor (L_C). To reduce the simulation time, a SC with a capacitance value of 10F was used if not specified in the figure.

The first simulation was performed to validate the DC/DC converter that was delivering a DC signal. The waveforms in Figure 4 correspond to a simulation of the converter with $V_{REF }$= 5 V in the buck-mode, which was used during converter analysis.

The second simulation consisted of a discharge process with a forced unbalanced condition in the SC voltages to verify the self-balancing algorithm that was working in the buck-mode. To that end, the capacitance and the initial voltage values of the SCs were set to be slightly different. The converter was commanded to deliver 10.2 kW to a resistive–inductive load (4.9 Ω-7 mH). The initial voltage difference between the ten plotted SC voltages (of the 62 SCs in the whole chain) was 200 mV. Figure 12 shows the voltage of these ten SCs, including the initial voltage and capacitance. Notice that around 0.3 s after the discharging process started, the voltage difference between the maximum and minimum values was reduced to 10mV, which is small enough to consider the SCs to be balanced. In the MMC, the upper half modules have a different voltage than the bottom half modules, as the zoom in Figure 12 shows. This is because the energy is transferred from the upper half modules during the positive half cycle and from the bottom half modules during the negative half cycle. Thus, the upper and the bottom half modules are balanced (voltage difference less than 10 mV) at different voltages, but both groups are close, around 20 mV for the 10F case.

Although the SCs were initially unbalanced, v_MMC stayed stable for the whole time that the algorithm presented in Section 3.3 was balancing the SCs. This test also validates AC operation using the MMC configuration and the wide input operating voltage range of each SM, from 2.7 V to 1.0 V, where v_MMC is slightly reduced when the SC voltage is lower than 1.5 V.

The third simulation consisted of connecting the MMC to the grid to validate the operations of the four quadrants involved in the buck-mode. Figure 13 demonstrates the capabilities of the MMC under different MMC voltage angles and amplitudes. In the simulations, the angles and amplitudes were controlled by I_{REF_dq}. Thus, different power transfers could be obtained. This simulation was created using the controller proposed in Figure 10. Figure 13 shows the voltage in two SMs from different half branches (top and bottom), i_MMC and v_MMC. In the first interval, the MMC delivers 4 kVAr of reactive power with I_{REF_dq} = (I_{REF_d}, I_{REF_q}) = (0, 25 A). Then, the MMC absorbs 4 kVAr, so I_{REF_dq} = (0, −25 A). Then, at t=1s, active power is delivered, so for 0.2 s, the system delivers 4kW-3.2kVAr, I_{REF_dq} = (25 A, −20 A). After that, the reactive current is set to zero, and only active power is delivered. Finally, 4 kW of active power is absorbed. This test shows the MMC is capable of absorbing and delivering active and reactive power. Notice the balancing process in the SC voltages and the increase and decrease in the SC voltages when they are absorbing and delivering power, respectively.

The fourth simulation validated the boost-mode (or absorbing mode), as shown In Figure 14, where the SC in each SM recharges from 1.4 V to 2.25 V and where the SCs are balanced at the same time.

5. Experimental Results

A down-scaled prototype for two SMs from each half branch was constructed, with a maximum power transfer of 175W per SM. Figure 15 shows the complete MMC, which is composed of the top branch, the bottom branch, a v_MMC and i_MMC sensor board, and a microcontroller unit (MCU), which acts as the master controller. Each SM integrates all of the components that are listed in Table 1; the power switches are at the bottom and are attached to a heatsink. In addition, the TI TMS320F28027 DSP was used as the SM controller, which includes the proportional controller for balancing the SCs and the PWM generator. The SM planar transformer was designed and developed specifically for the prototype. The master controller was implemented in a TI TMS320F28379D MCU, which gives the references to the SMs.

Three experimental tests were performed. The first test was the validation of the SM waveforms in buck-mode and boost-mode, as shown in Figure 16. These waveforms are consistent with the theoretical and simulated ones (Figure 4 and Figure 5).

The second test shows the operation of the MMC. Figure 17 shows the discharge mode (buck-mode) with a resistive load; the test depicts v_MMC and i_MMC. It shows that the voltage stayed stable during a step change in the load.

The third test shows the operation of the MMC when the load changes from R to RL and from R to RC, as shown in Figure 18, which validates the operation with reactive current flow. As the grid connection was validated in the simulation section, only the MMC was tested with different experimental loads to generate the experimental results, and thus the MMC was the only AC grid generator.

Finally, the fourth test demonstrated the efficiency of the whole MMC in both operation modes, as shown in Figure 19. The efficiency at high power is not as good as it is in a high-voltage DC/DC converter because of the large currents and low input voltages; however, it can be improved by paralleling the DC/DC converters in each submodule and by using wide band semiconductors, such as GaN or SiC. The prototype shows how the circuit works; however, the efficiency is not optimized and can be improved further.

Comparsion with Other ESSs

In order to summarize the advantages and disadvantages of the proposed converter,

Table 2. Components used for simulations and prototype’s tests.

ESS	Efficiency at 50%	Additional Stages	Drawbacks
[17]	84~86%	Balancing system	Medium THD
[18]	95~97%	Balancing system	Complexity
[25]	91~94% *	Output transformer	High THD
Proposed	85~88%	None	Cost

* Obtained by numerical simulations.

is presented. To make a fair comparison between the proposed ESS, only systems that require one additional stage to operate in the same way as the one proposed here are analysed.

The converter that is proposed in [17] requires an additional balancing system for the SC cells but provides isolation and the DC/DC and DC/AC conversions in a single cell. The main drawback is that the efficiency is not as high as the proposed converter.

A highly efficient multi-cell converter is presented in [18]; however, a balancing system is required in order to accommodate the SC cells. However, the complexity of the converter’s transformer design and control operation can be the main drawbacks, and the high efficiency can be reduced with the incorporation of the balancing system.

A comparable ESS is presented in [25] since it is based on the traditional control scheme of MMC. A high THD is presented at the output, but because of this, the efficiency is high due the fact that less switching stress is presented. However, this ESS lacks isolation, and if required, a bulky transformer should be placed at the output and efficiency could be further reduced.

Since the proposed ESS can accomplish all of the required stages in a single SM and since the balancing control is embedded and is relatively simple to operate, the main concern relays in the efficiency of the system. For this reason, the only drawback would be the cost if efficiency has to be increased, as GaN or SiC transistors should be integrated in each SM.

6. Conclusions

In a traditional supercapacitor (SC)-based ESS, four stages are needed: energy storage devices, the balancing system, and the DC/DC and DC/AC converters that connect the storage devices to the grid. The SC-based ESS that is proposed in this article uses a modular multilevel converter (MMC) that is able to reduce the number of stages by performing the self-balancing process and the DC/DC and DC/AC conversions in a single stage. Each submodule (SM) of the MMC consists of a DC/DC converter and a single SC. The DC/DC converter is a bidirectional full-bridge that has an active clamp and soft-switching techniques and works at 100 kHz and at low input voltages. In addition, the DC/DC converter includes a planar transformer, galvanic isolation is also achieved, and a bulky 50 Hz transformer can be avoided.

The MMC that was proposed here can be implemented using a large number of SMs in series without increasing the complexity of the main controller. This is because the balancing process is performed in each SM, and the main controller only governs the power flow between the SCs and the grid. This makes the proposed MMC attractive for SC-based ESS designs.

The proposed design was validated in simulations and in a real prototype. Four-quadrant operation with low distortion was achieved. Although the efficiency was not greater than those of the compared topologies, further work should overcome this limitation by using GaN or SiC transistors.