Generalized Behavioral Modelling Methodology of Switch-Diode Cell for Power Loss Prediction in Electromagnetic Transient Simulation

Abstract

Modern wide-bandgap (WBG) devices, such as silicon carbide (SiC) or gallium nitride (GaN) based devices, have emerged and been increasingly used in power electronics (PE) applications due to their superior switching feature. The power losses of these devices become the key of system efficiency improvement, especially for high-frequency applications. In this paper, a generalized behavioral model of a switch-diode cell (SDC) is proposed for power loss estimation in the electromagnetic transient simulation. The proposed model is developed based on the circuit level switching process analysis, which considers the effects of parasitics, the operating temperature, and the interaction of diode and switch. In addition, the transient waveforms of the SDC are simulated by the proposed model using dependent voltage and current sources with passive components. Besides, the approaches of obtaining model parameters from the datasheets are given and the modelling method is applicable to various semiconductors such Si insulated-gate bipolar transistor (IGBT), Si/SiC metal–oxide–semiconductor field-effect transistor (MOSFET), and GaN devices. Further, a multi-dimensional power loss table in a wide range of operating conditions can be obtained with fast speed and reasonable accuracy. The proposed approach is implemented in PSCAD/ Electromagnetic Transients including DC, EMTDC, (v4.6, Winnipeg, MB, Canada) and further verified by the hardware setups including different daughter boards for different devices.

1. Introduction

A power electronics (PE) system plays a key role in the process of efficient energy control, conversion, and management. Power semiconductor devices are the core components in a PE system and have a significant impact on system efficiency, reliability, and cost [1]. For decades, silicon-based devices, such as insulated-gate bipolar transistors (IGBTs) [2], metal-oxide-semiconductor field-effect transistors (MOSFETs) [3], are mainly and widely used in various modern PE applications (e.g., Photovoltaics (PV) [4], Power Factor Correction (PFC) [5], power supply [6], and other power converters [7,8]). However, the PE system performance and efficiency are hindered by Si-based devices due to the fundamental material limits. Recently, wide-bandgap (WBG) devices [9,10,11], such as silicon carbide (SiC) MOSFETs [12], enhancement-mode gallium nitride (eGaN) high-electron-mobility transistors (HEMTs) [13,14], have emerged and gained great popularity due to the superior features of fast switching speed and low switching loss. Thereby, the switching frequency can be further increased bringing the merits of size reduction for magnetic components, high power density, and high efficiency. Whereas the increased power losses of semiconductors are typically the main contributor to total loss especially for high-frequency (HF) applications, and the generated heat energy during switching transition may lead to fatigue failure and affect the reliability [15]. Hence, an accurate power loss model, which is applicable for different semiconductors and provides a deep insight into the switching process, is highly desirable for device selection and PE system optimization.

Currently, the ideal switch or two-state resistances model is typically adopted in most electromagnetic transient (EMT) simulators such as PSCAD/EMTDC and MATLAB/Simulink [16]. This simple model is mainly used to evaluate the overall system response and control strategy, and only the conduction loss is roughly considered. The conduction loss can be directly determined by the output curves in the datasheet, while the switching loss is more complicated and can be measured in the double-pulse test (DPT) [17]. Although DPT is widely used and can achieve high accuracy, it typically involves expensive probes and much peripheral bulky equipment such as a high voltage power supply. Designing a testing board with low parasitics is challenging and also significant for WBG devices due to the fast switching. Recently, several physic-based semiconductor models [18,19,20,21], such as simulation program with integrated circuit emphasis (SPICE) models [22,23], have been proposed to accurately describe the transient behaviors of the devices. However, the geometrical parameters for the model are often not available in the datasheet and thus the applicability of the model is limited. Another type of model (i.e., behavioral model [24,25]) has been developed, which focuses more on the external behaviors of the devices instead of the internal physics. As a result, the complexity is reduced and fast simulation speed can be achieved. It is adequate and widely used for system-level study, but more detailed transient concerns are needed to accurately evaluate the switching performance and estimate the power losses.

To have a better description of the switching transients, a lot of analytical loss models have been proposed [26,27]. Piecewise linearizing the switching process of the device is a commonly used method which enables simple and rapid loss estimation [28]. Whereas, the accuracy is still limited due to the ignorance of the parasitics. To improve it, more comprehensive loss models are developed considering various factors, such as temperature-dependent parameters [29,30], interactions between diode and switch [31], cross-talk issue [32], displacement current [33,34], and non-flat miller plateau [35]. Thereby, the switching loss can be obtained by solving the equivalent circuit for each switching sub-stage. Further, the entire switching process of eGaN HEMT in synchronous buck converter application is presented in [36,37] considering the third quadrant operation with the help of the 2-dimensional electron gas (2DEG). However, these methods are complicated involving huge computational burdens, not to mention the convergence issue. The measurement techniques and loss distribution including the capacitive losses for eGaN HEMT are illustrated in [38,39] and the scalable loss estimation method is further proposed based on the measurements. However, the measured data in the datasheet is typically under specific conditions, which limits the applicability and accuracy.

In a PE system, a power switch is typically paired with a diode as a switch-diode cell (SDC) to provide current commutation [40]. This basic commutation cell as shown in Figure 1a is widely used in PE applications and it consists of the active power switch ($S$), diode ($D$), equivalent circuit voltage ($V_{\mathrm{dd}}$) and load current ($I_{\mathrm{L}}$) [41]. Note that, four configurations of $S$, namely Si/SiC MOSFET, Si IGBT and eGaN HEMT, are taken into account in this paper and D can be a single positive-intrinsic-negative (PIN) diode, a Schottky barrier diode (SBD), the body diode of MOSFET or the equivalent diode of eGaN HEMT. During switching transition, power loss is resulted mainly from the switching and conduction losses of $S$ as well as the conduction loss and reverse recovery loss of $D$. In order to estimate these power losses in a PE system, a generalized behavioral modelling method of switch-diode cell in electromagnetic transient simulation (EMT) is proposed and it is an extension of previous work [42,43,44,45]. There are three technical contributions in this paper comparing with the conventional methods.

• A generalized behavioral model of SDC is proposed which is realized by dependent sources with passive components considering the impacts of parasitics, the temperature-dependent parameters, and the reverse recovery behavior of $D$. This model is not limited to a specific device and it is applicable to various devices including Si/SiC MOSFET, Si IGBT, and eGaN HEMT. In addition, most of the model parameters can be obtained from the device datasheets by the curve fitting method and no additional measurement is involved. Based on the specific requirement, the model can be modified and integrated into different simulators accordingly.
• The switching process of the switch-diode cell in a clamped inductive switching circuit is studied analytically based on the equivalent circuits for each switching sub-stage. Accordingly, the semiconductor model is developed and implemented in PSCAD/EMTDC. The switching analysis in this paper is more comprehensive considering the respective features of different devices such as the tail current of IGBT and the third quadrant operation of eGaN HEMT.
• A DPT setup was designed for experimental verification. To meets the different requirements of different semiconductors, three daughter boards were specifically designed incorporating with the main control board to characterize various devices and measure the corresponding power losses in a wide range of operating conditions. The simulated results are compared with the experimental results and show good agreements within 10% average error range.

2. Model Description

The simulation procedure of the proposed model is demonstrated in Figure 2. Initially, the device requirements for the desired PE application (e.g., voltage, current, temperature, and frequency) are determined. Based on those requirements, a specific semiconductor device is preliminarily selected for modelling and characterization. According to the device’s datasheet, the key model parameters can be extracted by the curve fitting method. Afterwards, the model parameters together with the operating conditions are input to the proposed device model, and a DPT simulation using the proposed model is further carried out. Subsequently, the transient voltage and current waveforms can be obtained, and simultaneously the power loss of the device can be computed. If the simulated results, in terms of switching transient behaviors and power loss, meet the requirements within the acceptable range, then the semiconductor is eventually selected for this application. Otherwise, it is necessary to reselect another device and evaluate the performance until the design is optimized.

In order to understand the switching behaviors of the SDC, a diode-clamped inductive load circuit (i.e., DPT circuit) is taken as an example which is widely used for device characterization. As shown in Figure 1b, the basic commutation unit consists of two complementary switches, one operates as a freewheeling diode $D$ and the other is an active switch $S$ controlled by the gate drive voltage ($v_{\mathrm{G}}$) through the external gate resistance $R_{\mathrm{gext}}$. In a typical hard-switching PE system, $S$ is identified by a positive drain current $i_{\mathrm{d}}$ (collector current $i_{\mathrm{c}}$ for IGBT) direction matching with the direction of $I_{\mathrm{L}}$. Since the commutation time is sufficiently short, $I_{\mathrm{L}}$ and $V_{\mathrm{dd}}$ are hardly changing during switching transition and thus they are treated as constant current and voltage sources, respectively.

Note that, the crucial circuit parasitic elements are also included as shown in Figure 1b. All the stray inductances in the power loop including the printed circuit board (PCB) trace and device package inductance are lumped and represented by $L_{\mathrm{s}}$, while the common source inductance ($L_{\mathrm{cs}}$) of $S$ is considered separately. In addition, the parasitic capacitances of $S$ include gate-drain capacitance ($C_{\mathrm{gd}}$), gate-source capacitance ($C_{\mathrm{gs}}$) and drain-source capacitance ($C_{\mathrm{ds}}$). Besides, the equivalent capacitance of $D$ ($C_{\mathrm{F}}$) denotes for junction capacitance of diode. It should be mentioned that when $D$ is configured as the body diode of a switch rather than a single diode,$C_{\mathrm{F}}$ will be the corresponding parasitic capacitance of the switch. During a switching transition, $I_{\mathrm{L}}$ commutates between $S$ and $D$. When a positive $v_{\mathrm{G}}$ is given, the gate-source voltage ($v_{\mathrm{gs}}$) will increase to turn on $S$. Subsequently, $i_{\mathrm{d}}$ including the channel current ($i_{\mathrm{ch}}$), the gate-drain current ($i_{\mathrm{gd}}$) and the drain-source current ($i_{\mathrm{ds}}$) starts rising, meanwhile the diode forward current ($i_{\mathrm{F}}$) declines gradually. When $S$ is fully turn on, the drain-source voltage ($v_{\mathrm{ds}}$) decreases to the on-state voltage and the diode forward voltage ($v_{\mathrm{F}}$) rises to $V_{\mathrm{dd}}$. The behavioral models of a SDC as illustrated in Figure 1c are proposed to reproduce the switching behaviors of $S$ and $D$, respectively. The details of the model descriptions including the active switch and diode model are presented as follows.

2.1. Active Switch Model

As shown in Figure 1c, the proposed active switch model consists of two parts, the gate loop and the power loop. It is noted that $L_{\mathrm{cs}}$ is shared by both loops and thus each loop includes one $L_{\mathrm{cs}}$ in order to decoupling both loops. Additionally, a dependent voltage source ($v_{\mathrm{Lcs}}$) is added in the gate loop to reflect the interactive impact of the current source ($i_{\mathrm{S}}$) on $L_{\mathrm{cs}}$ as expressed by,

$$v_{\mathrm{Lcs}}=L_{\mathrm{cs}}·\mathrm{d}{i}_{\mathrm{S}}/\mathrm{d}t$$

(1)

• Gate Loop Part

The external $v_{\mathrm{G}}$ is typically flipped between $V_{\mathrm{gon}}$ (20 or 15 V) and $V_{\mathrm{goff}}$ (−5 or 0 V) based on the specific gate drive requirement of the switch. The device internal gate resistance ($R_{\mathrm{gint}}$) is merged into $R_{\mathrm{gext}}$ as the total gate resistance ($R_{\mathrm{G}}$). Furthermore, the gate related junction capacitances (i.e., $C_{\mathrm{gd}}$ and $C_{\mathrm{gs}}$) are represented by the input capacitance ($C_{\mathrm{iss}}$) and an additional dependent voltage source ($v_{\mathrm{mil}}$). This equivalent $v_{\mathrm{mil}}$ becomes valid only when the miller plateau occurs on $v_{\mathrm{gs}}$ during switching transition and its value can be computed by

$$v_{\mathrm{mil}}=v_{\mathrm{th}}+i_{\mathrm{ch}}/g_{\mathrm{fs}}$$

(2)

where $v_{\mathrm{th}}$ and $g_{\mathrm{fs}}$ stand for threshold voltage and transconductance of a switch, respectively. Additionally, $i_{\mathrm{ch}}$ during miller plateau period typically equals to $I_{\mathrm{L}}$ which will be discussed in Section 2.3.

It is noted that the gate inductance is neglected here for simplicity although it can introduce a slight delay on $v_{\mathrm{gs}}$. In fact, this delay is mainly resulted from $L_{\mathrm{cs}}$ and $v_{\mathrm{Lcs}}$ due to the fast change of $i_{\mathrm{d}}$. Besides, the gate drive circuit is normally placed close to $S$ in order to minimize the potential oscillation introduced by the gate inductance and thus this inductance is negligible.

• Power Loop Part

In this model, $i_{\mathrm{d}}$ is represented by $i_{\mathrm{S}}$ which is the sum of $i_{\mathrm{ch}}$, $i_{\mathrm{gd}}$ and $i_{\mathrm{ds}}$. Note that, most of the time, $i_{\mathrm{S}}$ is the same as $i_{\mathrm{ch}}$ except for the voltage transition period when a displacement current is introduced due to the process of charging and discharging of the parasitic capacitance. In order to reflect the voltage change during switching transition as well as the on-state voltage ($v_{\mathrm{on}}$) of $S$, an equivalent dependent voltage source ($v_{\mathrm{S}}$) is adopted here. The value of $v_{\mathrm{on}}$ can be determined by $R_{\mathrm{ds}\left(\mathrm{on}\right)}$ with $I_{\mathrm{L}}$ in (3) or the saturation voltage ($v_{\mathrm{cesat}}$) for the case of IGBT.

$$v_{\mathrm{on}}=R_{\mathrm{ds}\left(\mathrm{on}\right)}·I_{\mathrm{L}}.$$

(3)

Besides, $L_{\mathrm{cs}}$ is also included in the power loop part which is associated with $L_{\mathrm{s}}$ to influence the transient waveforms. Thereby, the gate loop and power loop parts are decoupled and their interaction is represented by the equivalent dependent sources instead of nonlinear junction capacitances resulting in a reduction of model complexity.

2.2. Diode Model

The static model of a diode typically can be represented by an ideal diode ($D_{\mathrm{F}})$, a forward resistance ($R_{\mathrm{F}})$ and a voltage source ($v_{\mathrm{F}0}$) based on the forward characteristics in the device datasheet. Typically, $v_{\mathrm{F}}$ of the diode can be computed by,

$$v_{\mathrm{F}}=R_{\mathrm{F}}·i_{\mathrm{F}}+v_{\mathrm{F}0}.$$

(4)

It should be mentioned that, for the case of eGaN HEMT as $D$, the diode behavior is realized by 2DEG and thus the calculation of $v_{\mathrm{F}}$ is based on the reverse conduction characteristic of the GaN device [44] which is highly affected by the gate drive voltage ($v_{\mathrm{GF}}$) of GaN device as shown in (5),

$$v_{\mathrm{F}}\left(\mathrm{GaN}\right)=R_{\mathrm{Fr}}·i_{\mathrm{F}}+v_{\mathrm{thF}}-v_{\mathrm{GF}}$$

(5)

where $R_{\mathrm{Fr}}$ and $v_{\mathrm{thF}}$ are on-resistance in the third quadrant and threshold voltage of a GaN device, respectively. Since negative $v_{\mathrm{GF}}$ is typically provided to avoid the cross-talk issue, higher $v_{\mathrm{F}}$ is thus resulted which will increase the conduction loss of $D$. Notice that, if a positive $v_{\mathrm{GF}}$ is provided enabling the channel fully on, the on-state resistance will be the same value in the first quadrant.

Moreover, the dynamic characteristic of $D$ is described by $C_{\mathrm{F}}$ in parallel with an equivalent dependent current source ($i_{\mathrm{re}}$) for the reverse recovery behavior of $D$. When $D$ switches from forwarding conduction to off-state, $i_{\mathrm{F}}$ cannot be eliminated immediately and it takes a while to extinguish the excess carriers, this time is called reverse recovery time ($t_{\mathrm{rr}}$). The reverse recovery process occurs as soon as $i_{\mathrm{F}}$ becomes negative, $i_{\mathrm{re}}$ can be expressed by [45],

$$i_{\mathrm{re}}=\{\begin{array}{l}\mathrm{d}{i}_{\mathrm{F}}/\mathrm{d}t·t, t<t_{\mathrm{rm}}\hfill \\ I_{\mathrm{rm}}·\exp \left(\left(t-t_{\mathrm{rm}}\right)/{\tau }_{\mathrm{re}}\right), t\ge t_{\mathrm{rm}}\hfill \end{array},$$

(6)

where ${\tau }_{\mathrm{re}}$ denotes decay time constant and $i_{\mathrm{re}}$ reaches the peak current ($I_{\mathrm{rm}}$) at time $t_{\mathrm{rm}}$. In addition, the slew rate of diode current ($\mathrm{d}{i}_{\mathrm{F}}/\mathrm{d}t$) typically keeps the same as the turn-off slew rate of $S$. It needs to notice that, this reverse recovery behavior commonly exists in PIN diode and body diode of $S$, while the reverse recovery loss is eliminated for the case of SBD or eGaN HEMT and thus $i_{\mathrm{re}}$ can be neglected for simplicity. In fact, in these cases, the effect of $C_{\mathrm{F}}$ is the main concern which can introduce displacement current resulting in capacitive loss during switching transition.

2.3. Switching Transient Modelling

The switching process of the SDC in the DPT circuit is thoroughly analyzed based on the switching waveforms and the equivalent circuits as follows.

• Turn-on transition ($t_0$ − $t_3$)

The typical turn-on waveforms along with power loss information are illustrated in Figure 3 considering the case of PIN or body diode as well as the case of SBD or eGaN HEMT. The equivalent circuits during this period are also provided in Figure 4.

Initially, $S$ is in the off-state, and all the $I_{\mathrm{L}}$ flows through $D$. The corresponding $v_{\mathrm{F}}$ can be estimated by (5). At $t_0$, the gate charging period begins with a positive $V_{\mathrm{gon}}$ applying to $v_{\mathrm{G}}$ and $C_{\mathrm{iss}}$ is charged up through $R_{\mathrm{G}}$. Subsequently, $v_{\mathrm{gs}}$ will increase accordingly with the time constant (${\tau }_{\mathrm{iss}}=R_{\mathrm{G}}·C_{\mathrm{iss}}$). Note that $L_{\mathrm{cs}}$ in the gate loop will prolong the turn-on time causing more power losses.

The current rising period begins when $v_{\mathrm{gs}}$ goes beyond $v_{\mathrm{th}}$. During this interval, the conductive channel of $S$ is forming and $i_{\mathrm{S}}$ starts rising from zero to $I_{\mathrm{L}}$ which can be expressed by

$$i_{\mathrm{S}}=g_{\mathrm{fs}}·\left(v_{\mathrm{gs}}-v_{\mathrm{th}}\right).$$

(7)

The fast change of $i_{\mathrm{S}}$ on one hand, will introduce a negative feedback $v_{\mathrm{Lcs}}$ from power loop to gate loop due to $L_{\mathrm{cs}}$ to further delay the turn-on process. On the other hand, it will result in a total voltage drop ($v_{\mathrm{L}}$) on $L_{\mathrm{s}}$ and $L_{\mathrm{cs}}$. Simultaneously, $v_{\mathrm{ds}}$ decreased by $v_{\mathrm{L}}$ as shown in Figure 3.

As $I_{\mathrm{L}}$ commutates from $D$ to $S$, $i_{\mathrm{S}}$ reaches $I_{\mathrm{L}}$ at $t_2$ and $v_{\mathrm{gs}}$ will be clamped at $v_{\mathrm{mil}}$. At the same time, $i_{\mathrm{F}}$ decreases to zero and $D$ enters into the reverse recovery as shown in Figure 3a. This additional $i_{\mathrm{re}}$ will add to $i_{\mathrm{S}}$ (= $I_{\mathrm{L}}$ + $i_{\mathrm{re}}$) resulting a current spike and thus a bump in $v_{\mathrm{gs}}$ according to (2). When $i_{\mathrm{re}}$ reaches $I_{\mathrm{rm}}$, it starts declining and the voltage falling period begins. Subsequently, $v_{\mathrm{ds}}$ starts decreasing which is controlled by $v_{\mathrm{S}}$ and the corresponding slew rate can be determined by,

$$\mathrm{d}{v}_{\mathrm{ds}}/\mathrm{d}t=\mathrm{d}{v}_{\mathrm{S}}/\mathrm{d}t=-\left(V_{\mathrm{gon}}-v_{\mathrm{mil}}-v_{\mathrm{Lcs}}\right)/\left(C_{\mathrm{gd}}·R_{\mathrm{G}}\right).$$

(8)

As $v_{\mathrm{ds}}$ keeps decreasing and $v_{\mathrm{F}}$ increases simultaneously, the output capacitance ($C_{\mathrm{oss}}$) of $S$ and $C_{\mathrm{F}}$ of $D$ is discharged and charged, respectively. Since the voltage of $C_{\mathrm{oss}}$ and $C_{\mathrm{F}}$ are clamped to $V_{\mathrm{dd}}$, they share the same absolute value of voltage change. The resultant capacitive displacement current for $C_{\mathrm{oss}}$ ($i_{\mathrm{oss}}$) can be expressed by (9). Additionally, this $i_{\mathrm{oss}}$ along with the counterpart for $C_{\mathrm{F}}$ ($i_{\mathrm{CF}}=-C_{\mathrm{F}}·\mathrm{d}{v}_{\mathrm{ds}}/\mathrm{d}t$) will affect $i_{\mathrm{d}}$ as can be seen in Figure 3. By applying Kirchhoff’s law, $i_{\mathrm{d}}$ can be determined by (10) and $i_{\mathrm{S}}$ is modified accordingly to consider these displacement currents.

$$i_{\mathrm{oss}}=i_{\mathrm{gd}}+i_{\mathrm{ds}}=C_{\mathrm{oss}}·\mathrm{d}{v}_{\mathrm{ds}}/\mathrm{d}t$$

(9)

$$i_{\mathrm{d}}=i_{\mathrm{S}}=I_{\mathrm{L}}+i_{\mathrm{re}}-C_{\mathrm{F}}·\mathrm{d}{v}_{\mathrm{ds}}/\mathrm{d}t$$

(10)

Based on Figure 1b along with the above equations, $i_{\mathrm{ch}}$ can be further obtained,

$$i_{\mathrm{ch}}=i_{\mathrm{d}}-i_{\mathrm{oss}}=I_{\mathrm{L}}+i_{\mathrm{re}}-\left(C_{\mathrm{oss}}+C_{\mathrm{F}}\right)·\mathrm{d}{v}_{\mathrm{ds}}/\mathrm{d}t$$

(11)

Consequently, during this period, $i_{\mathrm{d}}$ includes $I_{\mathrm{L}}$, $i_{\mathrm{re}}$ and $i_{\mathrm{CF}}$, while the additional $i_{\mathrm{oss}}$ is further added to $i_{\mathrm{ch}}$ as shown in Figure 3. As a result, $v_{\mathrm{mil}}$ will also change according to (2). This period ends when $v_{\mathrm{ds}}$ drop to $v_{\mathrm{on}}$ at $t_3$. Thereafter, $v_{\mathrm{gs}}$ will continue climbing until reaches $V_{\mathrm{gon}}$.

Furthermore, the turn-on waveforms for the case of SBD or eGaN HEMT are presented in Figure 3b. Since the reverse recovery behavior is neglected for these cases as mentioned previously, $i_{\mathrm{re}}$ keeps zero and the voltage falling period starts right after $i_{\mathrm{S}}$ reaches $I_{\mathrm{L}}$. Apart from that, the turn-on modelling and analysis are the same as the case of the PIN diode.

• Turn-off transition ($t_4$ − $t_7$)

The turn-off process can be considered as the opposite of turn-on transition and the typical transient waveforms are illustrated in Figure 5. In order to turn off $S,$ $V_{\mathrm{gon}}$ is replaced by a negative gate drive signal $V_{\mathrm{goff}}$ and thus $C_{\mathrm{iss}}$ is discharged through $R_{\mathrm{G}}$ resulting the reduction of $v_{\mathrm{gs}}$. As $v_{\mathrm{gs}}$ drops to $v_{\mathrm{mil}}$, $C_{\mathrm{gd}}$ absorbs nearly all the $i_{\mathrm{g}}$ and thus $v_{\mathrm{ds}}$ begins to rise which again causes a current decline of $i_{\mathrm{d}}$. When $v_{\mathrm{ds}}$ reaches $V_{\mathrm{dd}}$, the miller plateau disappears and $i_{\mathrm{d}}$ begins decreasing with $v_{\mathrm{gs}}$ which results an additional $v_{\mathrm{L}}$ on $v_{\mathrm{ds}}$ as shown in Figure 5a.

As $v_{\mathrm{gs}}$ drops below $v_{\mathrm{th}}$, $i_{\mathrm{d}}$ becomes zero and $S$ turns off completely. However, for the case of Si IGBT, the tail current ($i_{\mathrm{tail}}$) is considered due to the recombination of the excess carriers. This $i_{\mathrm{tail}}$ will prolong the turn off time and can be modelled by the exponential function [42],

$$i_{\mathrm{tail}}=I_{\mathrm{tail}0}·\exp \left(-\left(t-t_{\mathrm{tail}0}\right)/{\tau }_{\mathrm{tail}}\right)$$

(12)

where ${\tau }_{\mathrm{tail}}$ stands for carrier transit time and the tailing period starts at $t_{\mathrm{tail}0}$ with the initial value of $I_{\mathrm{tail}0}$. These parameters can be estimated from the turn-off current waveform.

As can be seen from Figure 5b, a notable difference for the case of eGaN HEMT is $v_{\mathrm{gs}}$ does not typically plateau due to the much smaller capacitance and it keeps decreasing until reaches $V_{\mathrm{goff}}$. As a result, $i_{\mathrm{ch}}$ quickly declines synchronized with $v_{\mathrm{gs}}$ based on (7), meanwhile $v_{\mathrm{ds}}$ rises slightly and the slew rate is limited by the relatively high $C_{\mathrm{oss}}$ at low $v_{\mathrm{ds}}$. In fact, the channel turns off completely before $v_{\mathrm{ds}}$ is significantly rising. However, $i_{\mathrm{d}}$ does not follow the fast decreasing $i_{\mathrm{ch}}$ since its changing rate is limited by the inductances in the power loop. Additionally, $C_{\mathrm{oss}}$ is charged by the current difference between $i_{\mathrm{d}}$ and $i_{\mathrm{ch}}$ resulting a slight increase of $v_{\mathrm{ds}}$ which can be expressed as

$$\mathrm{d}{v}_{\mathrm{ds}}/\mathrm{d}t=\mathrm{d}{v}_{\mathrm{S}}/\mathrm{d}t=\left(i_{\mathrm{d}}-i_{\mathrm{ch}}\right)/C_{\mathrm{oss}}$$

(13)

Meanwhile, $C_{\mathrm{F}}$ is discharged resulting in a reduction of $v_{\mathrm{F}}$. Additionally, $i_{\mathrm{d}}$ thus can be obtained by

$$i_{\mathrm{d}}=i_{\mathrm{S}}=I_{\mathrm{L}}-C_{\mathrm{F}}·\mathrm{d}{v}_{\mathrm{F}}/\mathrm{d}t$$

(14)

Once $v_{\mathrm{gs}}$ drops below $v_{\mathrm{th}}$, namely $i_{\mathrm{ch}}$ becomes zero, the channel shuts down and $I_{\mathrm{L}}$ is shared by $C_{\mathrm{oss}}$ and $C_{\mathrm{F}}$. During this period, $v_{\mathrm{ds}}$ keeps rising according to (14). When $v_{\mathrm{ds}}$ rises to $V_{\mathrm{dd}}$, $I_{\mathrm{L}}$ starts commuting to $D$ and the $S$ turn-off transition finishes. Note that if very high $R_{\mathrm{G}}$ is used for eGaN HEMT, the turn-off analysis will be the same as the case of MOSFET as shown in Figure 5a.

Based on the above analysis $v_{\mathrm{S}}$ can be considered as an open circuit except for voltage rising/falling periods and $S$ on-state. During the voltage transition period, $v_{\mathrm{s}}$ is modelled as a dependent voltage source with a voltage slew rate as mentioned previously. In addition, the key expressions of $i_{\mathrm{S}}$ for different conditions can be summarized in

Table 1. Key expressions for $i_{\mathrm{S}}$ in the proposed model.

${\mathit{i}}_S$	Condition	${\mathit{v}}_{gs}<{\mathit{v}}_{th}$	${\mathit{i}}_d<{\mathit{I}}_L$	${\mathit{i}}_d>{\mathit{I}}_L$	Tail Period for IGBT	Turn-off for eGaN HEMT
	Expression	0	(7)	(10)	(12)	(14)

. It is noted that when $v_{\mathrm{gs}}$ is less than $v_{\mathrm{th}}$, the conduction channel is not established and theoretically, no current is flowing through the device. As a result, $i_{\mathrm{S}}$ is modelled with zero ampere under this condition in PSCAD/EMTDC which can be considered as open circuit. In this paper, all analytical equations for $v_{\mathrm{s}}$ and $i_{\mathrm{s}}$ are implemented and programmed with conditions in the custom programming modules in PSCAD. In this way, it is feasible and convenient to make any modifications as necessary.

3. Power Loss Analysis and Parameter Extraction

In general, the power losses of SDC mainly include conduction loss and switching loss. Typically the conduction losses of $S$ and $D$ can be calculated directly as the product of operating current (i.e., $I_{\mathrm{L}}$) and the on-state voltage drop based on (3–5). In addition, the reverse recovery loss of $D$ can be estimated based on the reverse recovery charge ($Q_{\mathrm{rr}}$) and $v_{\mathrm{F}}$ from the device datasheet and the switching loss of $S$ is analyzed as follows.

3.1. Turn on Loss($E_{on}$)

The instantaneous power of $S$ ($p_{\mathrm{S}}$) along with $E_{\mathrm{on}}$ are presented in Figure 3. Basically, $E_{\mathrm{on}}$ consists of the turn-on V-I overlap loss ($E_{\mathrm{vion}}$), the reverse recovery related loss ($E_{\mathrm{rr}}$) and the capacitive losses ($E_{\mathrm{oss}}$ and $E_{\mathrm{F}}$) for $C_{\mathrm{oss}}$ and $C_{\mathrm{F}}$, respectively. $E_{\mathrm{vion}}$ graphically can be divided into two parts, the $i_{\mathrm{d}}$ rising period and $v_{\mathrm{ds}}$ decreasing period. Hence, $E_{\mathrm{vion}}$ can be expressed as

$$E_{\mathrm{vion}}={{\displaystyle \int }}_{t_1}^{t_2}{v}_{\mathrm{ds}}·i_{\mathrm{d}}\mathrm{d}t+I_{\mathrm{L}}·{{\displaystyle \int }}_{t_2}^{t_3}{v}_{\mathrm{ds}}\mathrm{d}$$

(15)

Since reverse recovery behavior of $D$ and the displacement current of $C_{\mathrm{oss}}$ already have been considered in the modelling of $i_{\mathrm{S}}$, therefore the sum of $E_{\mathrm{vion}}$, $E_{\mathrm{rr}}$ and $E_{\mathrm{oss}}$, which is actually the measured turn-on loss ($E_{\mathrm{onm}}$), can be directly obtained by integrating $i_{\mathrm{d}}$ and $v_{\mathrm{ds}}$. This significantly reduces the complexity comparing with the analytical loss model by computing the switching time for each sub-stages. Moreover, according to (11), both the discharging current of $C_{\mathrm{oss}}$ and charging current of $C_{\mathrm{F}}$ are flowing through the channel of $S$ and thus these capacitive energy losses (i.e., $E_{\mathrm{oss}}$, $E_{\mathrm{F}}$) are dissipated into the channel. Based on the capacitance curves, $E_{\mathrm{oss}}$ can be expressed as

$$E_{\mathrm{oss}}={{\displaystyle \int }}_0^{V_{\mathrm{dd}}}{v}_{\mathrm{ds}}·C_{\mathrm{oss}}\mathrm{d}{v}_{\mathrm{ds}}$$

(16)

Since the charging current of $C_{\mathrm{F}}$ is provided by $V_{\mathrm{dd}}$ and part of the energy is stored in $C_{\mathrm{F}}$, thus the energy loss dissipated in the channel (i.e., $E_{\mathrm{F}}$) can be derived based on the charge of $C_{\mathrm{F}}$ ($Q_{\mathrm{F}}$),

$$E_{\mathrm{F}}=V_{\mathrm{dd}}·Q_{\mathrm{F}}-{{\displaystyle \int }}_0^{V_{\mathrm{dd}}}{v}_{\mathrm{F}}·C_{\mathrm{F}}\mathrm{d}{v}_{\mathrm{F}}={{\displaystyle \int }}_0^{V_{\mathrm{dd}}}\left(V_{\mathrm{dd}}-v_{\mathrm{F}}\right)·C_{\mathrm{F}}\mathrm{d}{v}_{\mathrm{F}}$$

(17)

Consequently, $E_{\mathrm{F}}$ theoretically should also be included in $E_{\mathrm{on}}$ which can be expressed as,

$$E_{\mathrm{on}}=E_{\mathrm{onm}}+E_{\mathrm{F}}={{\displaystyle \int }}_{t_1}^{t_3}{i}_{\mathrm{d}}·v_{\mathrm{ds}}\mathrm{d}t+E_{\mathrm{F}}$$

(18)

3.2. Turn off Loss($E_{off}$)

Generally, the power loss during turn-off transition occurs from $t_5$ to $t_7$ which includes the turn-off V-I overlap loss ($E_{\mathrm{vioff}}$), $E_{\mathrm{oss}}$ and the tailing loss for the case of IGBT ($E_{\mathrm{tail}}$). The analysis of $E_{\mathrm{vioff}}$ is significantly different for the slow-switching scenario in Figure 5a and the typical fast-switching for eGaN HEMT in Figure 5b. As for the former case, $v_{\mathrm{gs}}$ is fixed at $v_{\mathrm{mil}}$ and thus $i_{\mathrm{d}}$ is relatively constant throughout the voltage rising period. Thereafter, $i_{\mathrm{d}}$ decreases significantly meanwhile $v_{\mathrm{ds}}$ keeps relatively constant. Hence, $E_{\mathrm{vioff}}$ for this case can be graphically calculated as

$$E_{\mathrm{vioff}}={{\displaystyle \int }}_{t_5}^{t_6}{v}_{\mathrm{ds}}·i_{\mathrm{d}}\mathrm{d}t+{{\displaystyle \int }}_{t_6}^{t_7}\left(V_{\mathrm{dd}}+v_{\mathrm{L}}\right)·i_{\mathrm{d}}\mathrm{d}$$

(19)

Similarly, the sum of $E_{\mathrm{vioff}}$ and $E_{\mathrm{tail}}$, namely the measured turn-off loss ($E_{\mathrm{offm}}$), is typically an integral of $i_{\mathrm{d}}$ and $v_{\mathrm{ds}}$. It is noticed that, $C_{\mathrm{F}}$ is discharged and the energy is transferred to the inductive load during the voltage rising period resulting in a reduction of $i_{\mathrm{d}}$, while $C_{\mathrm{oss}}$ is charged and the corresponding energy (i.e., $E_{\mathrm{oss}}$) is stored which will be dissipated in the next turn-on transition. Therefore, $E_{\mathrm{oss}}$ should be theoretically excluded from $E_{\mathrm{off}}$ which can be expressed as

$$E_{\mathrm{off}}=E_{\mathrm{offm}}-E_{\mathrm{oss}}={{\displaystyle \int }}_{t_5}^{t_7}{v}_{\mathrm{ds}}·i_{\mathrm{d}}\mathrm{d}t-E_{\mathrm{oss}}$$

(20)

As for the typical eGaN HEMT scenario, $v_{\mathrm{gs}}$ skips the plateau and the channel turns off quickly before $v_{\mathrm{ds}}$ rises significantly as discussed previously. Afterwards, the energy is commutating between the inductive load and the two capacitances (i.e., $C_{\mathrm{F}}$ and $C_{\mathrm{oss}}$) which is almost lossless. Since the resistive overlap loss only occurs as long as the channel is on, it is significantly reduced for this case due to the relatively low $v_{\mathrm{ds}}$ during this time. Nevertheless, $E_{\mathrm{off}}$ still can be calculated by (20).

3.3. Parameter Extraction

The key model parameters can be directly extracted from the corresponding curves provided in the device datasheet by the curve fitting method [46,47,48], to avoid the supplementary experiments which are usually not practical. This method is adopted in this paper since it is applicable to different semiconductor devices and provides a relatively balanced tradeoff between accuracy and practicability. As an example, different types of semiconductors from different manufacturers as listed in

Table 2. Semiconductor devices selected for modelling and validation.

Device Type	Si IGBT	SiC MOSFET	Si MOSFET	eGaN HEMT	SiC SBD
Part Number	IKW40T120	SCT2080KE	NVHL072N65S3	GS66506T	SCS220KG
Manufacturer	Infineon	Rohm	On Semiconductor	GaN System	ROHM

are selected for modelling and validation of the proposed method. The extracting sequence is discussed in detail as follows.

• Static characteristic

In order to reproduce the switching behavior of $S$, two key parameters (i.e., $v_{\mathrm{th}}$ and $g_{\mathrm{fs}}$) are considered first. Since $v_{\mathrm{th}}$ typically is a temperature-dependent parameter rather than a constant value, it can be fitted by the 2nd order polynomial of junction temperature ($T_{\mathrm{j}}$) from the corresponding curve in the datasheet. Likewise, the transfer characteristic of $S$ can be fitted by the quadratic function of $v_{\mathrm{gs}}$ and subsequently $g_{\mathrm{fs}}$ can be further determined based on $v_{\mathrm{th}}$ and (7) as

$$g_{\mathrm{fs}}=i_{\mathrm{s}}·\sqrt{k_{\mathrm{ga}}/\left(i_{\mathrm{s}}-k_{\mathrm{gb}}\right)}·k_{\mathrm{gTa}}·{\left(T_{\mathrm{j}}/T_{\mathrm{a}}\right)}^{k_{\mathrm{gTb}}}$$

(21)

where $k_{\mathrm{ga}}$, $k_{\mathrm{gb}}$, $k_{\mathrm{gTa}}$, and $k_{\mathrm{gTb}}$ are fitting constants. $T_{\mathrm{a}}$ is room temperature which is considered as $25 °\mathrm{C}$ here. In this way, $g_{\mathrm{fs}}$ under the given $T_{\mathrm{j}}$ in datasheet can be obtained. The fitted results of transfer characteristics are compared and shown in good agreement with the datasheet in Figure 6. It is also found that there is a positive correlation between $T_{\mathrm{j}}$ and $g_{\mathrm{fs}}$ for Si IGBT and Si/SiC MOSFET while it shows a negative correlation for the case of eGaN HEMT.

Furthermore, in order to represent the on-state characteristic of $S$ as expressed in (3), the parameter $v_{\mathrm{cesat}}$ for IGBT or $R_{\mathrm{ds}\left(\mathrm{on}\right)}$ for other cases is needed to be extracted. Typically, both of $v_{\mathrm{cesat}}$ and $R_{\mathrm{ds}\left(\mathrm{on}\right)}$ are affected by $T_{\mathrm{j}}$ and $i_{\mathrm{S}}$ according to the curves in the datasheet. Therefore, $v_{\mathrm{cesat}}$ can be obtained by the following Equation (22).

$$v_{\mathrm{cesat}}=\left(k_{\mathrm{cea}}+r_{\mathrm{cea}}·i_{\mathrm{S}}\right)+\left(k_{\mathrm{ceb}}+r_{\mathrm{ceb}}·i_{\mathrm{S}}\right)·\left(T_{\mathrm{j}}-T_{\mathrm{a}}\right)$$

(22)

where $k_{\mathrm{cea}}$, $r_{\mathrm{cea}}$, $k_{\mathrm{ceb}}$ and $r_{\mathrm{ceb}}$ are fitting coefficients. Note that the gate voltage is assumed as constant in the parameter extraction for simplicity.

Likewise, $R_{\mathrm{ds}\left(\mathrm{on}\right)}$ for the cases of MOSFET and eGaN HEMT can be extracted by

$$R_{\mathrm{ds}\left(\mathrm{on}\right)}=\left(k_{\mathrm{ona}}+r_{\mathrm{ona}}·i_{\mathrm{S}}\right)+\left(k_{\mathrm{onb}}+r_{\mathrm{onb}}·i_{\mathrm{S}}\right)·\left(T_{\mathrm{j}}-T_{\mathrm{a}}\right)$$

(23)

where $k_{\mathrm{ona}}$, $r_{\mathrm{ona}}$, $k_{\mathrm{onb}}$ and $r_{\mathrm{onb}}$ are fitting coefficients. Based on the above equations, the key parameters for different semiconductors in this paper can be extracted and illustrated in

Table 3. Key fitting coefficients parameters of different semiconductors.

Parameter	${\mathit{k}}_{\mathrm{ga}}$	${\mathit{k}}_{\mathrm{gb}}$	${\mathit{k}}_{\mathrm{gTa}}$	${\mathit{k}}_{\mathrm{gTb}}$	${\mathit{k}}_{\mathrm{cea}},{\mathit{k}}_{\mathrm{ona}}$	${\mathit{r}}_{\mathrm{cea}},{\mathit{r}}_{\mathrm{ona}}$	${\mathit{k}}_{\mathrm{ceb}},{\mathit{k}}_{\mathrm{onb}}$	${\mathit{r}}_{\mathrm{ceb}},{\mathit{r}}_{\mathrm{onb}}$
Si IGBT	2.05	−6.96	14.2	−0.012	−0.001	$1·{10}^{-4}$	0.972	0.0215
SiC MOSFET	0.42	−0.35	2.96	−0.086	$4.1·{10}^{-4}$	$1.12·{10}^{-6}$	0.073	$5.1·{10}^{-4}$
Si MOSFET	3.72	−19.2	13	−0.57	0.048	$2.87·{10}^{-3}$	0.034	0.0012
eGaN HEMT	0.23	−776.9	0.51	−0.31	0.067	$7.2·{10}^{-5}$	$8.4·{10}^{-4}$	$4·{10}^{-6}$

.

• Parasitic capacitance and inductance

It is a fact that nonlinear capacitances are the key to the dynamic characteristic of the device. Typically, the capacitance curves provided in the datasheet is in the form of $C_{\mathrm{iss}}, C_{\mathrm{oss}}$ and reverse capacitance ($C_{\mathrm{rss}}$) which can be mathematically converted to junction capacitances. Generally, these capacitances are voltage-dependent and can be extracted by fitting the curves as

$$C\left(v\right)=f\left(v\right),$$

(24)

where f is a general fitting function for extraction of capacitance. In this paper, various $f$ are used for different devices to fit the corresponding curves as shown in Figure 7. Notice that the nonlinear capacitance curves vary from different devices and thus it is reasonable to change $f$ accordingly.

As for the parasitic inductance, only the internal inductance of the device is normally provided in the datasheet, while the stray parasitic inductance is highly related to the specific device package and PCB design. There are two widely used methods for inductance extraction, namely calculation method and experimental method. Based on the PCB and device package specification, the corresponding inductance can be computationally obtained with the help of calculation tools such as the Ansys Q3D Extractor software (v1.0, Canonsburg, PA, USA). According to (1), it also can be extracted from the slew rate of current along with $v_{\mathrm{L}}$ during $S$ turn on transition or from the resonant frequency of the power loop in the experimental results. In this paper, the parasitic inductances are initially estimated based on the PCB trace length of the power loop and the gate loop [50] as well as the device package (e.g., 2–5 nH for TO-247 [51]) and further calibrated from the switching waveforms.

• Diode parameters

According to (4), $R_{\mathrm{F}}$ and $v_{\mathrm{F}0}$ are the key static parameters for $D$ which can be extracted directly from the diode I-V curve in the datasheet and the corresponding values for various temperatures can be estimated by linear interpolation. Furthermore, the third quadrant operation of eGaN HEMT as $D$ is of special concern. Since the corresponding voltage drop is dependent on the gate drive voltage of $D$, thus it should be fitted by (5) based on the output curves in the third quadrant from the datasheet. The diode I-V curve fitted results for different devices are compared with the datasheet and illustrated in Figure 8. Notice that the conduction performance of the body diode in SiC MOSFET is generally worse than the anti-parallel diode of IGBT and SiC SBD. As for the eGaN HEMT, the reverse voltage drop is highly dependent on the gate drive voltage and the typical value for turn off (i.e., −3 V) will result in considerable conduction loss.

In addition, $C_{\mathrm{F}}$ can be obtained using the same method as mentioned above for $S$ from the capacitance curve in the datasheet. According to the previous switching transition analysis, it can be found that the reverse recovery behavior of diode plays a considerable role and the main parameters $I_{\mathrm{rm}}$ and $Q_{\mathrm{rr}}$ can be extracted from the diode curves as a function of $T_{\mathrm{j}}$ and $\mathrm{d}{i}_{\mathrm{F}}/\mathrm{d}t$ [42],

$$I_{\mathrm{rm}}=k_{\mathrm{rm}0}+t_{\mathrm{rm}0}·\mathrm{d}{i}_{\mathrm{F}}/\mathrm{d}t+\left(k_{\mathrm{rm}1}+t_{\mathrm{rm}1}·\mathrm{d}{i}_{\mathrm{F}}/\mathrm{dt}\right)·\left(T_{\mathrm{j}}-T_{\mathrm{a}}\right)$$

(25)

$$Q_{\mathrm{rr}}=k_{\mathrm{rr}0}+t_{\mathrm{rr}0}·\mathrm{d}{i}_{\mathrm{F}}/\mathrm{d}t+\left(k_{\mathrm{rr}1}+t_{\mathrm{rr}1}·\mathrm{d}{i}_{\mathrm{F}}/\mathrm{dt}\right)·\left(T_{\mathrm{j}}-T_{\mathrm{a}}\right)$$

(26)

where $k_{\mathrm{rm}0}$,$t_{\mathrm{rm}0}$, $k_{\mathrm{rm}1}$, $t_{\mathrm{rm}1}$, $k_{\mathrm{rr}0}$, $t_{\mathrm{rr}0}$, $k_{\mathrm{rr}1}$ and $t_{\mathrm{rr}1}$ are all fitting coefficients. Besides, the reverse recovery time ($t_{\mathrm{rr}}$) and ${\tau }_{\mathrm{re}}$ can be further determined by

$$t_{\mathrm{rr}}=2\sqrt{Q_{\mathrm{rr}}/\left(\mathrm{d}{i}_{\mathrm{F}}/\mathrm{d}t\right)}$$

(27)

$${\tau }_{\mathrm{re}}=1/\ln 10·\left(t_{\mathrm{rr}}-I_{\mathrm{rm}}/\left(\mathrm{d}{i}_{\mathrm{F}}/\mathrm{d}t\right)\right)$$

(28)

4. Experimental Verification

The objective of the proposed method is to reproduce the switching performance of the SDC and generate the corresponding power loss look-up table (LUT) with reasonable accuracy and fast simulation speed. The models are implemented in PSCAD/EMTDC and validated by comparing with the experimental waveforms and power loss results in the DPT bench for different semiconductor combinations.

4.1. Setup Description

An automatic DPT bench was designed and built for device characterization and loss validation [17]. Since the gate-drive requirements and device package are different for all the devices, three daughter boards were designed accordingly with a power supply (up to 1 kV) and the inductive load (5 mH) as shown in Figure 9. Tektronix High voltage differential probe THDP0200 and current probe TCP0030A were used for Si IGBT/MOSFET voltage and current measurements, respectively, while passive voltage probe (TTP800) and 0.1 Ω current shunt resistor (SDN-414-01) were adopted for SiC MOSFET and eGaN HEMT measurements. The temperature was controlled by a heating block and monitored by a thermal imager (Fluke, TiS40). In the DPT, the desired test conditions (voltage, current, and temperature) were initially set in the personal computer (PC) and all the control signals were given by the microcontroller Arduino on the board. Afterwards, the DC capacitor bank was charged to the desired voltage by the power supply unit, and the device was heated to the desired temperature. When voltage and temperature conditions were ready, two gate pulses were given in sequence to turn on and turn off the device under test (DUT). The switching waveforms and data were obtained by oscilloscope and processed in the PC for transient information and power loss analysis. In order to mitigate the measurement error of power loss due to the asynchrony of voltage and current, it is necessary to calibrate the probes before conducting the DPTs. To further guarantee the accuracy, additional delay time adjustments for the transient waveforms are also needed for the turn-on and turn-off processes. Taking the current as the reference, the calibration time of probe and waveform are provided in

Table 4. Calibration time of probes and waveforms.

DUT Case	Si IGBT	SiC MOSFET	Si MOSFET	eGaN HEMT
Probes calibration (ns)	48	26	45	23
Turn-on calibration (ns)	35	13	26	14
Turn-off calibration (ns)	31	18	25	12

. The calibrating fixture (067-1686-02) from Tektronix was used for calibration of the current and voltage probes. A 10 MHz sinusoidal signal was applied to both probes and the deskew time for voltage probe was adjusted until both measurements were synchronizing. Note that, these calibration times can be different for various probes and DUTs.

4.2. Switching Transient Verification

• Si IGBT

The daughterboard in Figure 9a was used for Si IGBT and MOSFET tests, and $v_{\mathrm{G}}$ was flipped between 15 V and 0 V to control the DUT’s on and off, respectively. The simulated results of switching current and voltage waveforms for IKW40T120 are compared with the DPT measurements in Figure 10. The simulated results demonstrate good agreement with measurements for current and voltage switching waveforms under 25$°\mathrm{C}$ and $150 °\mathrm{C}$. The switching details such as the tail current and the current spike resulting from the reverse recovery of $D$ can be clearly observed. In addition, $v_{\mathrm{ce}}$ slightly drops to 500 V as current rising and reaches a peak of 700 V during turn-off transition due to parasitic inductance. Besides, as $T_{\mathrm{j}}$ increases from 25$°\mathrm{C}$ to 150$°\mathrm{C}$, the reverse recovery behavior of $D$ becomes more obvious resulting higher current peak (up to 60 A) and the rise of $v_{\mathrm{ce}}$ as well as the decline of $i_{\mathrm{c}}$ during turn off transition slows down which will increase the switching power loss.

• SiC MOSFET

A more compact daughterboard as shown in Figure 9b was designed for testing SiC MOSFET. Additionally, the gate drive integrated circuit (IXDN609SI) was adopted as the gate driver onboard to provide 20 V/−5 V drive voltage for SiC MOSFET. Figure 11 shows the simulated switching waveforms of SiC MOSFET under the condition of 600 V and 20 A which match well with measured results. It can be observed that there is only a slight impact of $T_{\mathrm{j}}$ on the switching transients in terms of turn-on and turn-off time. Nevertheless, the current still can reach almost 40 A during the turn-on transition due to the reverse recovery behavior of the diode. Besides, it is found that a current ringing occurs during both turn-on and turn-off transitions because of the parasitic resonance. This ringing energy is generally consumed by the HF damping resistance in the circuit. Since either the voltage or current has typically dropped to a low level during the ringing period, thus this ringing loss is neglected in the model for simplicity.

• Si MOSFET with SiC diode

The DPT results for Si MOSFET with SiC diode using the same daughterboard as for testing Si IGBT are shown in Figure 12. In general, the simulated results match well with the measured results for different $R_{\mathrm{G}}$ conditions. As $R_{\mathrm{G}}$ increases from 10$\mathsf{\Omega }$ to 33$\mathsf{\Omega }$, a half less voltage drop of $v_{\mathrm{ds}}$ can be observed during turn-on transition due to the slower current rising speed. Likewise, only a slight increase of $v_{\mathrm{ds}}$ can be seen after $v_{\mathrm{ds}}$ climbs to $V_{\mathrm{dd}}$. Moreover, it is noted that the current spike is significantly limited comparing with the previous testing using PIN diode due to the merit of zero reverse recovery for SiC SBD. Whereas, there is still a slight current bump causing by the resonance of parasitics as well as the capacitive displacement current as discussed previously.

• eGaN HEMT

In order to test the eGaN HEMT which is a surface-mount device (SMD), a specific DPT daughterboard was used as shown in Figure 9c. The gate driver provided 6 V/0 V as gate drive voltage to control the lower side GaN switch $S$, while the upper side SiC SBD served as a freewheeling diode when $S$ turned off. The simulated switching results are compared with the measurements for the two operating conditions as shown in Figure 13. It can be seen that the simulation results are consistent with the experimental results. In the turn-on waveforms, the current rising time is only tens of nanoseconds. After $i_{\mathrm{d}}$ reaches $I_{\mathrm{L}}$, it behaves in the similar manner as previous test using Si MOSFET with SiC SBD. However, during the turn-off period, it can be clearly observed that, $i_{\mathrm{d}}$ declines significantly and drops to zero almost the same time as $v_{\mathrm{ds}}$ reaches steady state while for the other cases of devices, the fast decrease of current typically occurs after $v_{\mathrm{ds}}$ climbs to $v_{\mathrm{dd}}$. This is mainly because the channel of eGaN shuts down very fast before $v_{\mathrm{ds}}$ increase significantly as discussed in Section 2.3. Hence, when the channel turns off completely, the apparent $i_{\mathrm{d}}$ is dominated by the capacitive displacement current which is highly related to the change of $v_{\mathrm{ds}}$.

4.3. Power Loss Verification

With the aim of power loss verification for various devices, the switching losses were measured in the DPT and compared with the simulated results. During the switching transients, $p_{\mathrm{S}}$, which is the product of voltage and current, can be obtained using the math function in oscilloscope and similarly the $E_{\mathrm{onm}}$ and $E_{\mathrm{offm}}$ can also be obtained by integrating $p_{\mathrm{S}}$. As mentioned previously, the current and voltage probes are calibrated for each test and additional delay time is also added to the waveforms results to keep transient voltage and current synchronous. The captured waveforms and simulated waveforms under the same test conditions are demonstrated in Figure 14 taking Si IGBT as an example. By comparing the measured results with the simulated results, a good agreement can be clearly seen in terms of not only transient voltage and current waveforms but also computed $p_{\mathrm{S}}$, $E_{\mathrm{onm}}$ and $E_{\mathrm{offm}}$. Furthermore, the measured power loss results are compared with the simulated loss results for different devices under various operating conditions to validate the proposed method. The average error (ē) is calculated by averaging the absolute value of the error in each case.

Figure 15 shows the power loss results of Si IGBT under different conditions of current, voltage, and temperature. Generally, the total power loss ($E_{\mathrm{ts}}$) increases as the operating voltage and current increase, and $E_{\mathrm{off}}$ is less than $E_{\mathrm{on}}$ except for the high temperature condition. It can be seen that, the average errors of $E_{\mathrm{ts}}$ are within 7%, namely 5.1%, 5.5%, and 6.3% for different operating conditions of current, voltage, temperature, respectively.

Likewise, the power loss comparison results for SiC MOSFET are illustrated in Figure 16. Note that the $E_{\mathrm{ts}}$ for SiC MOSFET is typically less than 1 mJ which is much less than the counterpart of Si IGBT for similar conditions. It also can be found in Figure 16c that, there is a negative correlation between $E_{\mathrm{on}}$ and $T_{\mathrm{j}}$. Since $E_{\mathrm{on}}$ is the dominated loss, as $T_{\mathrm{j}}$ rises, $E_{\mathrm{ts}}$ reduces accordingly though $E_{\mathrm{off}}$ increases slightly. It is also noted that ē of $E_{\mathrm{off}}$ for various conditions are more than 7% while ē for $E_{\mathrm{on}}$ and $E_{\mathrm{ts}}$ are still within acceptable range. The reasons for the loss deviation can be the underestimation of parasitics and ringing loss as well as measurement error. Besides, a relatively small amount of loss deviation can still result in a high error percentage when the overall loss is relatively low.

Figure 17 shows $E_{\mathrm{ts}}$ results for the combination of Si MOSFET and SiC SBD as the SDC. It can be observed that $E_{\mathrm{ts}}$ increases as the operating voltage and current increase. In addition, a slight increase of $E_{\mathrm{ts}}$ can be found as the operating temperature rise from 25 °C to 150 °C, while $E_{\mathrm{ts}}$ increases significantly when 33 $\mathsf{\Omega }$ $R_{\mathrm{G}}$ is used. Moreover, the power loss results for the case of eGaN HEMT with SiC SBD are illustrated in Figure 18. It should be mentioned that, in order to capture the switching waveforms and the power loss with reasonable accuracy, a 220 $\mathsf{\Omega }$ gate resistance is used to relatively sacrifice the switching speed and avoid shoot through issue due to the very low $v_{\mathrm{th}}$ of GaN. Comparing with the simulated and measured results, a good agreement is achieved at various testing conditions and the error is within an acceptable range, although the ē of $E_{\mathrm{off}}$ is slightly higher.

4.4. Discussion

• Accuracy

Comparing with the original two-state resistance switch model in PSCAD/EMTDC, the proposed model is capable to reproduce the switching transient waveforms considering various impacts of parasitics and interactive behavior of diode. In addition, the thermal effect is also considered to provide reasonably accurate results comparing with the measured results where the temperature is monitored by a thermal imager as shown in Figure 19a. Apart from the switching waveforms, multi-dimensional (i.e., voltage, current, temperature) power loss LUT as shown in Figure 19b also can be obtained simultaneously. The average error is within 10% comparing with measured results for various devices under various conditions. Comparing to the traditional physical model or analytical loss model, no significant advantage is found in the modelling accuracy using the proposed model due to the ignorance of parasitic resonance and some linear assumptions. Nevertheless, the complexity of the proposed model is reduced with no state equations and numerical calculations, and all the model parameters can be extracted from the datasheet.

• Efficiency

The proposed model uses equivalent dependent voltage and current sources to represent the dynamic characteristics of devices based on the analytical equations for each sub-stage of the switching process. In addition, the gate loop and power loop are decoupled and the complicated numerical calculation as well as solving physical equations are not necessary which can boost the simulation efficiency and avoid convergence issue. In order to obtain an accurate power loss LUT with a wide range of operating conditions, there are numerous permutations to be taken into account and thousands of simulation runs are required instead of repetitive DPTs. For example, it requires around 5400 simulation runs to cover the operating range, namely voltage from 20 V to 600 V with 20 V step, current from 2 A to 60 A with a 2 A step, and temperature from 25 °C to 150 °C with a 25 °C step. Figure 19c demonstrates the time cost of using the SPICE model provided by the manufacturer and using the proposed model in PSCAD. In order to achieve reasonable accuracy, the simulation time step is typically one nanosecond or less. Notice that, it takes thousands of seconds to barely finish around 200 runs in SPICE, while more than 10 times less running time is needed to finish the same number of runs by the proposed model with even less time-step (i.e., 0.1 ns). Furthermore, to finish the whole 5400 simulation runs using the proposed model at 1 ns time-step, it takes less than 300 s which shows the merit of time-saving in generating the power loss LUT.

• Applicability

The proposed approach can be used to reproduce the switching waveforms and obtain the power loss LUT of SDC configured by various devices such as Si IGBT, Si/SiC MOSFET, eGaN HEMT, and SiC SBD. When it comes to other devices with a new structure such as Cascade GaN, the proposed model cannot be used directly and modifications are needed though the basic modelling method is still applicable. In addition, for each specific device, the curve fitting functions and algorithms for parameter extraction are needed to be adjusted for good fitting results. Apart from PSCAD/EMTDC, the proposed approach can also be applied to other simulators such as MATLAB/Simulink, PLECS, and Saber with respective modifications. Besides, the proposed model provides an insight into the device behavior and most of the elements have clear descriptions. As a result, it is more easily apprehensible than mathematical equations. Conversely, analytical loss models are normally limited to the specific device type or combination and it is difficult to extend the models to various PE applications for loss estimation. Besides, loss measurements are time-consuming, costly, and challenging especially for WBG devices due to the fast switching speed.

5. Conclusions

In this paper, a generalized behavioral modelling approach of the switch-diode cell for power loss prediction is proposed, implemented in PSCAD/EMTDC, and validated by experimental results in double-pulse tests. This proposed model consists of an active switch model and diode model and it can be used for different modern power semiconductors. The modelling approach along with power loss analysis is derived based on the comprehensive switching process analysis in a clamped inductive switching circuit. The static and dynamic characteristics of the switch-diode cell are modelled by dependent voltage and current sources with passive components. In addition, the proposed model is improved by considering the impacts of parasitic elements, interactive behavior of diode, and the temperature-dependent parameters. Besides, the extraction of the model parameters is introduced by curve fitting from the device datasheet. Moreover, the switching transient verification along with power verification is conducted for different devices under a wide range of operating conditions. A good agreement between the simulated results using the proposed model and experimental results can be achieved with less than 10% average error. Consequently, the proposed model provides a good balance in terms of accuracy, efficiency, and applicability.