# Sequential Switching Shunt Regulator Parallel Power Processing Control for High Capacitance Solar Arrays

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## Abstract

**:**

## 1. Introduction

^{3}R) due to its high efficiency, low mass, simplicity and high reliability [2,3]. In Figure 2, a simplified S

^{3}R schematic diagram is presented; as can be seen, the solar array is divided into n equal sections and each one is connected to a shunt regulator so the section can be short-circuited or connected to the bus. The MEA is in charge of controlling which sections are connected directly to the bus, which sections are short-circuited and which is the only section that switches to regulate the bus voltage.

_{SA}) has increased considerably, complicating the S

^{3}R design. The main reason for the C

_{SA}increase is the use of triple and quadruple junction solar cells. Current quadruple junction technology presents a very high efficiency, up to 32% of what is directly reflected in a solar array mass and volume reduction. However, it also shows a higher parasitic capacitance that can be up to five times larger than silicon technology for the same voltage and power [4,5,6,7]. As reported in [8], the impact of a higher C

_{SA}on the S

^{3}R can be summarized as follows:

- The requirement to use an active current limiter [3,9] to avoid the current spikes produced by the discharge of the C
_{SA}at shunt–transistor turn on. When one solar array section is connected to the bus, the C_{SA}is charged to the bus voltage. That energy is dissipated in the shunt transistor when it turns on. The requirement to use an active current limiter has a major drawback because the shunt transistor switching time increases drastically, and this results in an increase of the switching power losses. - Increase of the dump turn-on delay penalizing the DC characteristic (output voltage ripple) and the AC characteristics (regulator bandwidth and output impedance).

_{BUS}). The benefit of having smaller sections is the reduction of the C

_{SA}, which combined with an increase of the C

_{BUS}, reduces the switching frequency and improves the AC characteristics of the system. These solutions also have a constraint at system level; a high number of sections or a higher C

_{BUS}penalize the system in terms of mass and volume. Another proposed solution to reduce the switching frequency is the use of nesting on the S

^{3}R cells [10], but with the penalty of making the transconductance gain depend on the regulator operating point and complicating the control loop design.

^{3}R topology is used, but instead of dividing the complete solar array into equal sections, two types of sections will be used. The solar array will be divided into two types of sections: low and high current solar array sections. A new parallel power processing strategy has been developed, so the small sections are the only ones that switch to regulate the bus, achieving lower switching power losses. In addition, the use of small sections to regulate the bus reduces the current ripple on the bus capacitor. The high-power sections are only connected or disconnected during high load power changes.

^{3}R, with a constant conductance, independent of the regulator working point, and the control loop implanted is entirely analog.

_{sa}is mathematically modeled so that the impact in the AC characteristics of the regulator can be represented and analyzed. Using the delay model, a new control loop design is suggested to reduce the impact of the delay. This control loop is also modeled and simulated, thus improving the AC behavior of the regulator.

## 2. Proposed S^{3}R Control Method

^{3}R topology is used, but the solar array is divided into two types of sections: low current solar array sections (sas) with low parasitic capacitance (C

_{sa}), and high current solar array sections (SAS) with high parasitic capacitance (C

_{SA}). The control strategy is modified so the small sections are the only ones that switch to regulate the bus, producing low switching power losses. The modification consists in a new distribution of the hysteric windows control references of all the sections and the inclusion of an analog subtractor in the low C

_{SA}sections MEA control loop; the proposed solar array regulator is depicted in Figure 3.

_{sas}) sections needed is given by the division of the current of a high-power section (I

_{SAS}) by the current of a low-power section (I

_{sas}), adding one more section for redundant purposes, see Equation (1).

_{sas}= I

_{SAS}/ I

_{sas}+ 1

_{hl}) defined by Equation (2) and distributed as is shown in Figure 4.

_{hl}= I

_{sas}/ G

_{HL}) is defined by Equation (3).

_{HL}= V

_{hl}· (N

_{sas}+ I

_{SAS}/ I

_{sas})

_{Ln}) is given by Equation (4), where v

_{l}

_{1}is the first low-power section lower limit reference.

_{Ln}= v

_{l1}+ V

_{hl}·(n − 1)·I

_{SAS}/ I

_{sas}

_{ERROR_sas}) is needed to control the low-power sections, see Figure 3. The substractor, included in the low-power sections control loop, subtracts a voltage (D) to the original MEA control signal (V

_{ERROR}) proportional to the high-power sections connected to the bus (N

_{SAS_ON}), see Equations (5) and (6).

_{ERROR_sas}= V

_{ERROR}− D·N

_{SAS_ON}

_{SAS}/ G

- From t0 to t1 (steady state response): In this state, the low-power Section 2 switches to regulate the bus voltage, while all the high-power sections are fully off. The total load-averaged current is given by Equation (7).I
_{LOAD}= I_{sas1}+ <I_{sas2}> - From t1 to t2 (small load perturbation): At t1, a load current step occurs. V
_{ERROR}and V_{ERROR}_sas increase switching on the upper low-power current sections until the current balance is reached. In this case, the compensation is achieved with the third low-power section. Since the V_{ERROR}signal does not cross the V_{H}_{1}threshold, the high-power sections are not connected. This is the classical S^{3}R response. In this case, the total load-averaged current is given by Equation (8).I_{LOAD}= I_{sas1}+ I_{sas2}+ <I_{sas3}> - From t2 to t3 (large load perturbation): At t2, a large load current step occurs. Now the low-power sections remaining current is insufficient to compensate the load change. After switching on all the low-power sections, V
_{ERROR}increases until it crosses the V_{H}_{1}threshold; at this moment the high-power Section 1 is switched on and a constant voltage is subtracted to V_{ERROR}to generate V_{ERROR_sas}. The compensation is not yet achieved, so V_{ERROR}increases until it crosses the V_{H}_{2}threshold, at this moment the high-power Section 2 is switched on and the voltage subtracted to V_{ERROR}to generate V_{ERROR_sas}is doubled, see Equation (9). Now the balance between bus and load currents becomes positive so the control voltage decreases, and the system enters in the small power sections regulation zone. The fine current balance is achieved with the second small power section. The total load-averaged current is given by Equation (10).V_{ERROR_sas}= V_{ERROR}− 2·DI_{LOAD}= I_{sas1}+ <I_{sas2}> + I_{SAS1}+ I_{SAS2} - From t3 to t4 (large load perturbation): At t3, a large load current step occurs. All the low-power sections are switched off, but this is insufficient to compensate the load change. After switching off all of the low-power sections, V
_{ERROR}still decreases until it crosses the V_{L}_{2}threshold; at this moment the high-power Section 2 is switched off and the voltage subtracted to V_{ERROR}to generate V_{ERROR_SAS}is given by Equation (11). Now the balance between the bus and load currents becomes negative so the control signals increase and the system enters into the small power sections regulation zone. The fine current balance is achieved with the first small power section. The total load-averaged current is given by Equation (12).V_{ERROR_sas}= V_{ERROR}− DI_{LOAD}= <I_{sas1}> + I_{SAS1}

## 3. Shunt Transistor Turn-On Delay Modeling

^{3}R. The shunt transistor turn-on delay (τ

_{delay}) is not improved because the relationship between the parasitic capacitance and the current for each section is constant, see Equation (13).

_{O}). With the delay, the regulator loop gain (TBUS) is given by Equation (15).

_{cbus}) (Equation (16)) to assure a 60° PM and 10 dB GM is given by Equation (17).

_{O}) is shown in Equation (18).

_{Omax}) is not affected by the delay and is given by Equation (19).

## 4. Simulation Results

_{SA}, the PM is degraded to 55.3°. In red is shown the response using the lead–lag network and considering the delay, the PM is improved to 62.1°.

_{SA}. In red is shown the response using the lead–lag network and taking into account the delay. In all of the cases, the standard is accomplished, but the addition of lead–lag network improves the output impedance.

## 5. Experimental Results

## 6. Conclusions

^{3}R control parallel power control method is presented for reducing the losses and improving the AC characteristics when high parasitic capacitance solar arrays are used. The proposed method was implemented in a low-power prototype and validated with different tests. This concept can also be applied to the sequential switching shunt series regulator (S

^{4}R) [14], reducing the ripple on the battery charging current.

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 4.**Hysteretic comparator window references: low-power sections (blue) and high-power sections (red).

**Figure 8.**Simulated control loop response: blue, no delay; green, Csa delay; red, Csa delay + lead–lag network.

**Figure 9.**Output impedance simulation: blue, no delay; green, Csa delay; red, Csa delay + lead–lag network.

**Figure 10.**Experimental results (steady-state), ILoad = 12.5 A. Yellow, bus voltage ripple; blue, low-power sections control signal; pink, low-power sections bus current; green, high-power sections bus current.

**Figure 11.**Experimental results (large load perturbation), ILoad = 2.5–12.5 A. Yellow, bus voltage ripple; blue, low-power sections control signal; pink, low-power sections bus current; green, high-power sections bus current.

**Figure 12.**Experimental results (large load perturbation detail), ILoad = 2.5–12.5 A. Yellow, bus voltage ripple; blue, low-power sections control signal; pink, low-power sections bus current; green, high-power sections bus current.

System Specifications | |
---|---|

Power | 4500 W |

C_{sa} | 0.3 μF/A |

Bus voltage (V_{BUS}) | 50 V |

Bus voltage ripple (ΔV_{BUS}) | <1% V_{BUS} |

Maximum output impedance (Z_{O max}) | 11.1 mΩ |

Control loop gain margin | ≥10 dB |

Control loop phase margin | ≥60° |

System Specifications | |
---|---|

Number of high-power solar array sections (SAS) | 10 (7 A/section) |

Number of low-power solar array sections (sas) | 6 (3.5 A/section) |

Bus capacitance | 2.76 mF |

G | 7 A/V |

K | 0.1 |

R1 | 1 kΩ |

R2 | 145 kΩ |

C2 | 5 nF |

R3 | 100 Ω |

C3 | 3.7 nF |

R4 | 1 kΩ |

C4 | 3 pF |

Breadboard System Specifications | |
---|---|

Power | 1200 W |

Bus voltage (V_{BUS}) | 50 V |

Bus voltage ripple (ΔV_{BUS}) | <1% V_{BUS} |

Maximum output impedance (Z_{O max}) | 50 mΩ |

Control loop gain margin | ≥10 dB |

Control loop phase margin | ≥60° |

High-power solar array sections | 3 (4 A/section) |

Low-power solar array sections | 4 (1 A/Section) |

Bus capacitance | 480 μF |

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**MDPI and ACS Style**

Blanes, J.M.; Carrasco, J.A.; Garrigós, A.; Marroquí, D.; Torres, C. Sequential Switching Shunt Regulator Parallel Power Processing Control for High Capacitance Solar Arrays. *Energies* **2021**, *14*, 429.
https://doi.org/10.3390/en14020429

**AMA Style**

Blanes JM, Carrasco JA, Garrigós A, Marroquí D, Torres C. Sequential Switching Shunt Regulator Parallel Power Processing Control for High Capacitance Solar Arrays. *Energies*. 2021; 14(2):429.
https://doi.org/10.3390/en14020429

**Chicago/Turabian Style**

Blanes, José M., José A. Carrasco, Ausiàs Garrigós, David Marroquí, and Cristian Torres. 2021. "Sequential Switching Shunt Regulator Parallel Power Processing Control for High Capacitance Solar Arrays" *Energies* 14, no. 2: 429.
https://doi.org/10.3390/en14020429