# All-SiC ANPC Submodule for an Advanced 1.5 kV EV Charging System under Various Modulation Methods

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Modulation Strategies in Active Neutral Point Clamped (Anpc) Converter

_{1}–S

_{6}, connected according to Figure 2.

_{DC}voltage and zero voltage; and when the output voltage is negative, the inverter is switching between negative −V

_{DC}and zero voltage. Control of the converter when the voltage is positive and negative is analogous. Therefore, in this article, the different control methods are only described when the voltage is positive. P and N states can be obtained only by turning on transistors S

_{1}and S

_{2}in P state, and S

_{3}and S

_{4}in N state. During P state, transistor S

_{6}can be turned on. Similarly, during N state, transistor S

_{5}can be on as well. This ensures constant v

_{DS}voltages equal to V

_{DC}on transistors S

_{3}and S

_{4}during P state, and on S

_{1}and S

_{2}during N state. Simultaneously, in the ANPC topology, there are different approaches to obtain zero state. Four modulation strategies of the ANPC and one of the NPC converters are depicted in Table 1 and Figure 3. In this paper, there are four different modulations described (PWM1–PWM4). These PWM techniques differ from each other in regard to the zero state, in which the current flows through different conduction paths marked in Figure 4 by 2 and 3.

_{2}and S

_{5}are on, and the current flows through conduction path two (marked in blue in Figure 4). In this control method, during transition P–0 a high value of di/dt in L

_{σ}

_{1}, L

_{σ}

_{5}, L

_{σ}

_{7}causes voltage spikes on the switching transistors. In technique PWM2 [35], during zero state, the current flows via transistors S

_{3}and S

_{6}, and in this case during the transition there is a high value of di/dt in stray inductances L

_{σ}

_{1}–L

_{σ}

_{3}, and L

_{σ}

_{5}–L

_{σ}

_{7}. When we compare the transition in PWM2 to the one in PWM1, the equivalent stray inductance is higher, and thus, di/dt is higher as well, which leads to a higher value of voltage spikes. In method PWM3 [23,36], during zero state, transistors S

_{2}, S

_{3}, S

_{5}, and S

_{6}are on, and current flows through conduction paths two and three; equivalent resistances of both conduction paths are lower, which leads to immensely lower conduction losses. PWM4 [22] is similar to PWM1. In both cases, after the transition from P to 0, the current flows through conduction path two. However, in PWM4 instead of transistor S

_{6,}transistor S

_{4}is turned on, and thus, even if the modulation pattern differs, the outcome is highly similar.

## 3. Simulation Study

_{1}and S

_{4}are characterized by the highest value of roughly 30 W each, while pair S

_{2}and S

_{3}show 17.3 W, and the last pair S

_{5}and S

_{6}just 11.9 W per device. The second modulation method, PWM2, is similar in terms of total power loss. However, it is also characterized by a highly imbalanced distribution—transistors S

_{2}and S

_{3}are the sources of over a 70% semiconductor power loss with 42.5 W, while pairs S

_{1}, S

_{4}, and S

_{5}, S

_{6}emit 6.4 and 10.8 W, respectively. PWM3 exhibits top performance in terms of power loss, with nearly the most imbalanced distribution, as over 60% of the power loss with 30.3 W is dissipated on pair S

_{1}, S

_{4}, while pairs S

_{2}, S

_{3}, and S

_{5}, S

_{6}are the source of 11.8 and 5.6 W, respectively. However, it is worth noting that the source of this higher imbalance compared with PWM1 and PWM4 is lower power loss for the other MOSFET pairs, and not the increase in the S

_{1}, S

_{4}pair. Finally, results for method PWM4 are very similar to PWM1 in terms of the loss distribution at 30.3, 16.4, and 11.7 W for transistor pairs S

_{1}, S

_{4}; S

_{2}, S

_{3}; and S

_{5}, S

_{6}, respectively. In terms of the conducting paths and thus power losses, these methods are akin to each other.

## 4. Experimental Study

#### 4.1. The ANPC Submodule Prototype

#### 4.2. Experimental Setup

#### 4.3. Results from the Experimental Study

_{0}, DC-link voltages V

_{DC1}and V

_{DC2}, load AC voltage v

_{AC}, and current i

_{AC}. As the impact of the PWM method is minimal in a 50 Hz context, it is assumed that for other modulation techniques, the waveforms are identical and thus are not shown. As can be seen, there is still some imbalance between the +/0 and 0/− DC voltages, regardless of high 610 µF capacitance; however, its impact is limited regarding the load AC current and voltages as its THD settled below 5% for all the tests, and thus we can omit the mismatches throughout the further result analysis. For the nominal parameters, the AC load current settled at roughly 28 A, whereas the load voltage was established close to 230 V RMS resulting in a power of 6.5 kW. This operating point was further used as a nominal for further experimental comparison between the different PWM methods.

#### 4.3.1. Transistor Overvoltage and Ringing

_{1}and S

_{4}, S

_{2}and S

_{3}, as well as S

_{5}and S

_{6}were identical, only the switching voltages for the bottom switches (S

_{3}, S

_{4}, S

_{6}) were measured. Unfortunately, due to the highly compacted design of the submodule, it was impossible to apply current probes and measure the transistor currents. Nevertheless, in terms of the safety of operation for the semiconductor power devices, the drain–source voltage is the crucial factor, while the impact of the current oscillations was indirectly included in the study through efficiency measurements. Furthermore, it is worth noting that transistor overvoltages were also affected by the DC-link voltage imbalances. Thus, peak overshoot voltages could have been even more limited with a higher capacitance, and would not occur if the submodule was used in a different system, e.g., three-phase inverter, where DC-link voltage balancing is assured.

_{DC1}and V

_{DC2}settled at roughly 60 V, corresponding to roughly 4% of nominal voltage.

_{1}and S

_{4}(depending on the line current sign) are not bound to any constant potential, but rather float depending on the current ANPC leg state. This is not an issue for PWM4, as transistors S

_{5}and S

_{6}connect the floating potential to the zero voltage, and thus peak transistor voltage overshoots are lower. The significant difference between PWM2 and other techniques is caused by this method’s relatively lengthy conduction loop, as mentioned in Section 2. Nevertheless, the variance is still on a minimal level. Therefore, when a similar power rating as in the presented system is considered, it is safe to assume that for a well-optimized system, in terms of conduction path length, the effect of chosen PWM technique on the transistor overvoltage is somewhat limited and should not be as important as other factors, such as power loss and its distribution or filter requirements, or even omitted at all. However, this effect is enlarged when the current is higher. Thus, such an approach should not be applicable in very high power systems.

#### 4.3.2. Power Losses

_{2}, S

_{3}, S

_{5}, S

_{6}), and thus, the lowest effective on resistance. PWM2, on the other hand, showcases top performance for lower power, below 60% of the nominal value. In this modulation type, when only the positive half of the line current is considered, transistors S

_{1}and S

_{5}do not switch at all as the switching occurs between S

_{2}and S

_{3}. Therefore, switching loss is limited to this transistor pair, contrary to other PWM techniques where the switching occurs for more power devices. However, when higher power is regarded, the importance of switching loss is diminished, and the efficiency becomes very similar for all the methods except for PWM3, which is characterized by more available conduction paths. Thus, using PWM2 and PWM3 alternately, depending on the load conditions, should be considered to ensure the lowest power losses throughout the whole operating range. Furthermore, developing an algorithm that optimally chooses the modulation technique according to the operating point may be considered. When we study the two other methods more generally, in terms of efficiency, they are pretty similar with the slight advantage for PWM1 for lower power ratings.

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Conflicts of Interest

## References

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**Figure 3.**Different modulation strategies for the ANPC converters (

**a**) PWM 1, (

**b**) PWM 2, (

**c**) PWM 3, (

**d**) PWM 4.

**Figure 7.**Experimental setup for the ANPC single-phase inverter system with a resistive load—(

**a**) scheme, (

**b**) photo.

**Figure 8.**Experimental results from a test at 1500 V DC and 6.5 kW power (m = 0.45, v

_{AC}= 230 V) with a line frequency-focused view. From the top: ANPC leg output voltage v

_{0}, DC-link voltages V

_{DC1}and V

_{DC2}, load AC voltage v

_{AC}, and current i

_{AC}.

**Figure 9.**Exemplary experimental waveforms showcasing drain–source transistors for positive load current (i

_{AC}> 0) for the modulation technique with highest overvoltages (PWM2)—(

**a**) turn-on, (

**b**) turn-off.

**Figure 10.**Exemplary experimental waveforms showcasing drain–source transistors for negative load current (i

_{AC}< 0) for the modulation technique with highest overvoltages (PWM2)—(

**a**) turn-on, (

**b**) turn-off.

**Figure 11.**Experimental characteristics showcasing performance of the ANPC leg in function of converter power P—(

**a**) efficiency at 1500 V DC, 230 V AC, and m = 0.45, (

**b**) power loss at nominal operating point (1500 V DC, 6.5 kW, m = 0.45).

State | S_{1} | S_{2} | S_{3} | S_{4} | S_{5} | S_{6} | Conduction Path(s) | PWM Method |
---|---|---|---|---|---|---|---|---|

P | 1 | 1 | 0 | 0 | 0 | 1/0 | 1 | 1, 2, 3, 4 |

0U3 | 1 | 0 | 1 | 0 | 0 | 1 | 3 | 2 |

0U2 | 0 | 1 | 0 | 0 | 1 | 0 | 2 | 1 |

0U1 | 0 | 1 | 0 | 1 | 1 | 0 | 2 | 4 |

0F | 0 | 1 | 1 | 0 | 1 | 1 | 2 and 3 | 3 |

0L1 | 1 | 0 | 1 | 0 | 0 | 1 | 3 | 4 |

0L2 | 0 | 0 | 1 | 0 | 0 | 1 | 3 | 1 |

0L3 | 0 | 1 | 0 | 1 | 1 | 0 | 2 | 2 |

N | 0 | 0 | 1 | 1 | 1/0 | 0 | 4 | 1, 2, 3, 4 |

Parameter | Description |
---|---|

DC voltage | 1500 V |

AC voltage | 230 V RMS/50 Hz |

Rated power | 6.67 kVA (1/3 of 20 kVA) |

Operating frequency | 64 kHz |

SiC MOSFETs | NTH4L040N120SC1 |

Filter inductor | 220 µH |

Filter capacitor | 4.7 µF |

DC capacitors | 2 × 610 µF |

V_{DC} = 1500 V; P = 6.5 kW; v_{AC} = 230 V rms | ||||
---|---|---|---|---|

Parameter | PWM1 | PWM2 | PWM3 | PWM4 |

P_{(S1,S4)} [W] | 30.3 | 6.4 | 30.3 | 30.3 |

P_{(S2,S3)} [W] | 17.3 | 42.5 | 11.8 | 16.4 |

P_{(S5,S6)} [W] | 11.9 | 10.8 | 5.6 | 11.7 |

V_{DC} = 1500 V; P = 6.5 kW; v_{AC} = 230 V rms | ||||
---|---|---|---|---|

Parameter | PWM1 | PWM2 | PWM3 | PWM4 |

v_{DS_max(S3)} [V] | 832 | 957 | 846 | 827 |

v_{DS_max(S4)} [V] | 889 | 802 | 868 | 873 |

v_{DS_max(S6)} [V] | 857 | 848 | 842 | 843 |

P_{LOSS(exp.)} [W] | 182 | 177 | 165 | 182 |

P_{LOSS(sim.)} [W] | 137 | 137 | 114 | 136 |

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**MDPI and ACS Style**

Kopacz, R.; Harasimczuk, M.; Lasek, B.; Miśkiewicz, R.; Rąbkowski, J.
All-SiC ANPC Submodule for an Advanced 1.5 kV EV Charging System under Various Modulation Methods. *Energies* **2021**, *14*, 5580.
https://doi.org/10.3390/en14175580

**AMA Style**

Kopacz R, Harasimczuk M, Lasek B, Miśkiewicz R, Rąbkowski J.
All-SiC ANPC Submodule for an Advanced 1.5 kV EV Charging System under Various Modulation Methods. *Energies*. 2021; 14(17):5580.
https://doi.org/10.3390/en14175580

**Chicago/Turabian Style**

Kopacz, Rafał, Michał Harasimczuk, Bartosz Lasek, Rafał Miśkiewicz, and Jacek Rąbkowski.
2021. "All-SiC ANPC Submodule for an Advanced 1.5 kV EV Charging System under Various Modulation Methods" *Energies* 14, no. 17: 5580.
https://doi.org/10.3390/en14175580