A Switched Quasi-Z-Source Inverter with Continuous Input Currents

Abstract

Impedance source converters as single-stage power conversion alternatives can boost and regulate the output voltages of renewable energy sources. Nevertheless, they, also known as Z-source inverters (ZSIs), still suffer from limited voltage gains and higher stresses across the components. To tackle such issues, extra diodes, passive components, and active switches can be utilized in the basic ZSIs. In this paper, a modified switched-quasi-Z-source inverter (S-qZSI) is proposed, which features continuous input currents and high boosting capability to boost output voltage by minor modifications of a prior-art topology. Furthermore, the voltage stress of the active switches is reduced, which contributes to a lower cost. The operation principles are discussed comprehensively. The performance of the proposed ZSI in terms of conversion ratio, voltage gain, and stresses on the power switches and capacitors is benchmarked with selected ZSIs. Finally, simulations and experimental tests substantiate the theoretical analysis and superior performance.

1. Introduction

Impedance source converters have gone through rapid development in the last few decades since the first Z-source inverter (ZSI) proposed by Peng in [1]. It is known that the traditional voltage source inverter (VSI) only has buck characteristics so that it is usually not directly applied in the power conversion applications. That is, a front-end stage is commonly adopted. However, the extra DC–DC converters may lead to higher costs and lower efficiency [2]. Furthermore, the power switches of the VSI may be damaged if the inverter leg is short-circuited due to wrong drive signals. To address these issues, the Z-source network, as shown in Figure 1a, which features buck-boost characteristics, can be adopted. However, the basic ZSI still suffers from certain limitations, such as discontinuous input currents and high voltage stresses across the components. The quasi-ZSI (q-ZSI), as shown in Figure 1b, provides an effective solution to the above limitations [3]. Based on the basic ZSI/qZSI structure, many attempts have been made to enhance the performance of impedance source converters in terms of high boost capability, low voltage stresses across the components, and high efficiency [4,5,6,7,8,9,10,11,12,13,14,15,16,17].

The principle of enhancing the boost capability in the impedance source networks is to add more passive components or power switches into the basic ZSI/qZSI networks. For example, the inductors in the ZSI/qZSI can be replaced by the switched-inductor (SI) cells in Figure 2, in which a higher boost voltage gain can be obtained [8,9,10]. Compared with the SI-ZSI, the SI-qZSI can achieve a continuous input current and lower stresses across the components. Moreover, switched-capacitor (SC) cells can be employed to obtain low voltage stress, small inductors, high voltage gains, and efficiency [11,12].

Nevertheless, the limitation of these modified converters based on extra components is that many passive devices lead to a higher cost and larger volume of the converter. To tackle this, modified ZSI topologies based on switched-boost networks have been proposed in the literature. The switched-boost inverter (SBI) and embedded-qSBI are shown in Figure 3 [13,14]. The SBI features a lower number of components and the same boost capability by adding one power switch compared to the ZSI. Moreover, the q-SBI and embedded-qSBI have additional advantages, such as reduced voltage stresses on the capacitors, higher voltage gains, and continuous input currents, which makes them appropriate for renewable energy applications. Similarly, the SI or SC cells can be utilized in the SBI/qSBI for a higher boost capability, as presented in [15]. In addition, a diode-assisted SBI (DA-SBI) was proposed in [16]. This modified topology is a combination of the SBI and diode-assisted network, which provides a high voltage gain and continuous input currents. Furthermore, the modified topology quasi-ZSI with continuous input current (CC-qZSI) in [17] shows the improved boost capabilities and less voltage stresses by adding a switched boost network to the original qZSI.

Inspired by the above, this paper proposes a modified qZSI with a switched-boost network (S-qZSI), which can achieve continuous input currents and higher boost capability compared with selected switched-boost inverters and modified ZSIs. The rest of this paper is organized as follows. The detailed analysis of the proposed S-qZSI is presented in Section 2. Furthermore, in Section 3, a comprehensive comparison with selected switched-boost ZSIs is carried out and the benchmarking results are provided. The theoretical analysis is verified by simulation and experimental tests in Section 4. Finally, the paper is concluded in Section 5.

2. Operation Principle of the Proposed S-qZSI

The schematic of the proposed S-qZSI is presented in Figure 4. It consists of three capacitors ($C_1$, $C_2$, and $C_3$), three diodes ($D_1$, $D_2$, and $D_3$), two inductors ($L_1$ and $L_2$), one power switch ($S_1$), and a traditional two-level VSI ($S_1$–$S_6$). The input voltage is defined as $V_{\mathrm{in}}$. The voltages across the capacitors ($C_1$, $C_2$ and $C_3$) are defined as $V_{{\mathrm{C}}_1}$, $V_{{\mathrm{C}}_2}$, and $V_{{\mathrm{C}}_3}$, and the diode voltages can be expressed as $V_{{\mathrm{D}}_1}$, $V_{{\mathrm{D}}_2}$, and $V_{{\mathrm{D}}_3}$, and the inductor currents are denoted as $i_{{\mathrm{L}}_1}$ and $i_{{\mathrm{L}}_2}$. Moreover, the load current of phase a is defined as $i_a$.

Similar to the prior-art ZSIs, the boost capability of the proposed S-qZSI can be achieved by utilizing the shoot-through state of the inverter, in which the inverter leg is short-circuited by turning on two switches simultaneously. Therefore, the operation modes of the proposed S-qZSI can be considered as shoot-through mode and non-shoot-through mode, as presented in Figure 5. The corresponding steady-state waveforms are given in Figure 6. In order to simplify the analysis, the capacitors or inductors in the proposed topology are identical.

As shown in Figure 5a, if the switches in one of the inverter legs receive the same turn-on signal, the inverter side is short-circuited and the DC-link voltage $V_{\mathrm{dc}}$ is zero. The power switch $S_1$ is in the conduction state due to the turn-on gate signal $G_s$, as can be seen in Figure 6. Moreover, the diodes $D_1$, $D_2$, and $D_3$ are in OFF-state and the diodes sustain the negative voltage, as presented in Figure 6. Meanwhile, the energy from the input source can be stored in the inductors and the capacitors charge the inductors. Figure 6 shows the inductor currents increase from the minimum to maximum value during the time interval $t_1$ to $t_2$. On the other hand, Figure 5b shows the non-shoot-through mode and the corresponding time interval is $t_2$ to $t_3$. In this mode, the operation principle of the inverter is the same as traditional VSI. It can be seen in Figure 6 that the inverter bridge is equivalent to a current source viewed from the DC side [18]. Meanwhile, the switch $S_1$ is turned OFF and the switch voltage is equal to the voltage of the capacitor $C_1$. Additionally, all three diodes are ON-state and the voltages of the diodes become zero in Figure 6. Moreover, the inductors can release the stored energy to the load or grid side by controlling the inverter switches. That is, the inductor currents decrease from maximum to minimum value as expected in Figure 6. Accordingly, the voltage and currents across the components can be derived by applying the Kirchhoff’s law, as given in

Table 1. Voltage of the components in shoot-through and non-shoot-through modes.

Components	Voltage
	Shoot-Through Mode	Non-Shoot-Through Mode
Inductor $L_1$	$V_{{\mathrm{C}}_1}+V_{{\mathrm{C}}_3}+V_{\mathrm{in}}$	$V_{\mathrm{in}}+V_{{\mathrm{C}}_3}-V_{\mathrm{dc}}^{\mathrm{p}}$
Inductor $L_2$	$V_{{\mathrm{C}}_1}-V_{{\mathrm{C}}_2}$	$-V_{{\mathrm{C}}_2}=-V_{{\mathrm{C}}_3}$
Switch S	0	$V_{{\mathrm{C}}_1}$
Diode $D_1$	$-V_{{\mathrm{C}}_1}+V_{{\mathrm{C}}_2}-V_{{\mathrm{C}}_3}$	0
Diode $D_2$	$-V_{{\mathrm{C}}_1}$	0
Diode $D_3$	$-V_{{\mathrm{C}}_1}$	0
peak DC-link	0	$V_{{\mathrm{C}}_1}$

.

The time intervals in the shoot-through mode and non-shoot-through mode can be expressed as $DT$ and $D(1-T)$, where D and T represent the duty cycle and switching period. By applying the volt-second balance principle to the inductors $L_1$ and $L_2$, the following can be obtained:

$$D(V_{{\mathrm{C}}_1}+V_{{\mathrm{C}}_3}+V_{\mathrm{in}})+\left(1D\right)(V_{\mathrm{in}}+V_{{\mathrm{C}}_3}-V_{\mathrm{dc}}^{\mathrm{p}})=0$$

(1)

$$D(V_{{\mathrm{C}}_1}-V_{{\mathrm{C}}_2})-\left(1D\right)V_{{\mathrm{C}}_2}=0$$

(2)

where $V_{\mathrm{dc}}^{\mathrm{p}}$ is the peak DC-link voltage. Subsequently, the capacitor voltages can be derived as

$$V_{{\mathrm{C}}_1}=\frac{1}{1-3D}{V}_{\mathrm{in}}$$

(3)

$$V_{{\mathrm{C}}_2}=V_{{\mathrm{C}}_3}=\frac{D}{1-3D}{V}_{\mathrm{in}}$$

(4)

Furthermore, $V_{\mathrm{dc}}^{\mathrm{p}}$ and boost factor B can be obtained as

$$V_{\mathrm{dc}}^{\mathrm{p}}=\frac{1}{1-3D}{V}_{\mathrm{in}}=B·V_{\mathrm{in}}$$

(5)

with

$$B=\frac{1}{1-3D}$$

(6)

being the boost factor. Consequently, the voltage gain G in respect to the modulation index M can be expressed as

$$G=MB=\frac{M}{3M-2}$$

(7)

3. Comparison with Prior-Art ZSI Topologies

In order to show the performance of the proposed S-qZSI, the component count, boost factor, voltage gain, and component stresses of the proposed S-qZSI and selected topologies are investigated in detail. Firstly, the number of the components in the proposed S-qZSI and selected ZSI topologies is presented in

Table 2. Comparison of the number of the components in the proposed Sq-ZSI.

		SBI [13]	Embedded-qSBI [14]	DA-SBI [16]	CC-qZSI [17]	Proposed S-qZSI
Component count	Inductors	1	1	2	2	2
	capacitors	1	1	2	2	3
	switches	1	1	1	1	1
	diodes	2	2	4	2	3

. According to Table 2, the DA-SBI, CC-qZSI, and the proposed topology all employ two inductors, but the basic SBI and embedded-qSBI only utilize one inductor. Moreover, the quantity of the capacitors in the proposed S-qZSI is higher than the other selected topologies, but it has the same component-count with the DA-ZSI by replacing one diode with a capacitor to construct a quasi-Z-source network.

Furthermore,

Table 3. Benchmarking of boost factor, voltage gain, and voltage stresses among selected impedance source inverters.

	SBI [13]	Embedded-qSBI [14]	DA-SBI [16]	CC-qZSI [17]	Proposed S-qZSI
Boost factor B	${\displaystyle \frac{1D}{1-2D}}$	${\displaystyle \frac{1}{1-2D}}$	${\displaystyle \frac{1}{D^2-3D+1}}$	${\displaystyle \frac{1}{D^2-3D+1}}$	${\displaystyle \frac{1}{1-3D}}$
Voltage gain G	${\displaystyle \frac{M^2}{2M-1}}$	${\displaystyle \frac{M}{2M-1}}$	${\displaystyle \frac{M}{M^2+M-1}}$	${\displaystyle \frac{M}{M^2+M-1}}$	${\displaystyle \frac{M}{3M-2}}$
${\displaystyle \frac{V_{S_i}}{G{V}_{in}}}$	${\displaystyle \frac{1}{G-\sqrt{G^2-G}}}+{\displaystyle \frac{1}{G}}$	$1-{\displaystyle \frac{1}{G}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}$	1	${\displaystyle \frac{3G-1}{2G}}$
${\displaystyle \frac{V_{S_1}}{G{V}_{in}}}$	${\displaystyle \frac{1}{G-\sqrt{G^2-G}}}$	$2-{\displaystyle \frac{1}{G}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}$	${\displaystyle \frac{3G-1}{2G}}$
${\displaystyle \frac{V_{C_1}}{G{V}_{in}}}$	${\displaystyle \frac{1}{G-\sqrt{G^2-G}}}$	$2-{\displaystyle \frac{1}{G}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}-1$	${\displaystyle \frac{3G-1}{2G}}$
${\displaystyle \frac{V_{C_2}}{G{V}_{in}}}$	/	/	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}-1$	1	${\displaystyle \frac{G-1}{2G}}$
${\displaystyle \frac{V_{C_3}}{G{V}_{in}}}$	/	/	/	/	${\displaystyle \frac{G-1}{2G}}$
${\displaystyle \frac{V_{D_1}}{G{V}_{in}}}$	${\displaystyle \frac{1}{G-\sqrt{G^2-G}}}+{\displaystyle \frac{1}{G}}$	$1-{\displaystyle \frac{1}{G}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}$	${\displaystyle \frac{3G-1}{2G}}$
${\displaystyle \frac{V_{D_2}}{G{V}_{in}}}$	${\displaystyle \frac{1}{G-\sqrt{G^2-G}}}$	$2-{\displaystyle \frac{1}{G}}$	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}$	1	${\displaystyle \frac{3G-1}{2G}}$
${\displaystyle \frac{V_{D_3}}{G{V}_{in}}}$	/	/	1	/	${\displaystyle \frac{3G-1}{2G}}$
${\displaystyle \frac{V_{D_4}}{G{V}_{in}}}$	/	/	${\displaystyle \frac{2G}{1-G+\sqrt{5G^2-2G+1}}}-1$	/	/

benchmarks the boost factor, voltage gain, and component stresses among the proposed S-qZSI and selected topologies. Figure 7 compares the boost capability of the proposed topology with other selected ZSI/SBIs. In Figure 7a, the comparison between the duty cycle D and the boost factor B for these topologies is presented. It can be seen in Figure 7a that the basic SBI and embedded-qZSI have relatively lower boost capability due to their small component-count. Furthermore, the boost capability of the DA-SBI and CC-qZSI is greatly enhanced by adding more passive components. It is noteworthy that the proposed S-qZSI can achieve a higher boost factor compared with selected topologies in a certain range of shoot-through duty cycles (i.e., 0–0.3), but the component-count of the proposed topology is the same as that of the DA-SBI. Similarly, Figure 7b shows the relationship between the voltage gain and the modulation index. The proposed S-qZSI has the highest voltage gain among the selected topologies if the modulation indexes are identical within the range of 0.68–1. Therefore, the higher modulation index of the proposed S-qZSI results in better power quality for the same voltage output.

In addition to the advantage of the high boost capability, as demonstrated above, the proposed S-qZSI can also achieve lower voltage stresses on the power switches. The detailed voltage stresses expressions for the active switch in the network, inverter bridge switch, the capacitors, and the diodes are presented in Table 3. The voltage stress on the components can be defined as the ratio of voltage across the components to $G{V}_{\mathrm{in}}$. As shown in Figure 8a, the switch stress of the proposed S-qZSI (see $S_i$ in Figure 6) is lower than that of the SBI and DA-SBI, although the component-count of the proposed S-qZSI and DA-SBI is the same. Moreover, it is noteworthy that the ratio of the CC-qZSI for switch stress is a constant value, which means that the ratio is independent of voltage gain and input voltage. As for the stress comparison of inverter bridge switches ($S_1$–$S_6$) as presented in Figure 8b and Table 3, the DA-SBI and CC-qZSI have the same inverter bridge switch stress, and the proposed S-qZSI has the best performance compared with other selected topologies, which allow lower ratings of the switches and reduce the cost to some extent. Moreover, Figure 9a compares the capacitor stress. According to Table 3, two of the capacitors in the proposed S-qZSI have the same voltage stress. Moreover, although the proposed topology utilizes one more capacitor, this additional capacitor has low voltage stress compared with other capacitors based on Table 3. Considering all the topologies in Figure 9a, the CC-qZSI has the lowest capacitor voltage among all the topologies, but the proposed S-qZSI shows better performance than the SBI, the embedded-qSBI, and the DA-SBI. Finally, the comparison of diode stress is presented in Figure 9b. Similarly, the diode stress of the proposed S-qZSI is much lower than most of the selected topologies, except the embedded-qSBI.

4. Simulation and Experimental Results

In this section, simulations and experimental tests are provided to verify the performance of the proposed S-qZSI. As shown in Figure 4, the output stage is achieved by a three-phase system for verification.

Table 4. Parameters of the proposed S-qZSI.

Parameter	Symbol	Value
Modulation index	M	0.83
Duty cycle	D	0.25
DC input voltage	$V_{\mathrm{in}}$	$30$V
S-qZSI inductance	$L_1,L_2$	$643\mathsf{\mu }$H
S-qZSI capacitor	$C_1,C_2,C_3$	$100\mathsf{\mu }$F
Load inductance	$L_f$	$3$mH
Load resistance	$R_f$	$40\mathsf{\Omega }$
Switching frequency	$f_s$	5 kHz

presents the system parameters applied in the simulations and experimental prototype.

4.1. Simulation Results

The simulations are executed in the PLECS and Matlab/Simulink platform. The simulation results are given in Figure 10. The output voltage and load current of the whole system are shown in Figure 10a. According to Equation (6), the boost factor B is equal to four when D is 0.25, and thus the DC-link peak voltage can be boosted to 120 V. Figure 10a shows that the DC-link peak voltage is the same as the theoretical value, which equals 120 V. Moreover, the peak load current is about 2 A. Additionally, the DC-link voltage and inductor currents are presented in Figure 10b. It can be seen that the characteristics of the inductor currents match well with the steady-state analysis, where the inductor currents increase during the shoot-through state and decrease during the non-shoot-through state. It can be observed in Figure 10b that the inductor current $i_{L_1}$ is continuous DC currents. In Figure 10c, the gate signal $G_S$ and diode voltage $V_{{\mathrm{D}}_1}$, $V_{{\mathrm{D}}_2}$ and $V_{{\mathrm{D}}_3}$ are presented, where the peak diode voltage is the same as the peak DC-link voltage. Figure 10d presents the capacitor voltage of the proposed topology. The voltage of the capacitor $C_1$ is 120 V, which is equal to the DC-link peak voltage. Moreover, the voltages of the capacitors $C_2$ and $C_3$ are only 30 V, which is consistent with the input DC voltage.

4.2. Experimental Results

The prototype of the proposed S-qZSI is designed based on the previous analysis, as presented in Figure 11. The parameters of the prototype are the same as the parameters applied in the simulations. The control signals applied in the proposed S-qZSI are generated from a digital signal processor (DSP) TMS320F28335 from Texas Instrument and field-programmable gate array (FPGA) Altera Cyclone 4. The DSP is used to generate the complementary signals and the FPGA board can perform the logical operation based on the output signals from the DSP.

Figure 12 presents the experimental results of the proposed S-qZSI under the condition that M is 0.83 and D is 0.25. As shown in Figure 12a, the boosted DC-link voltage is approximately 3.88 times as large as the input voltage (30 V) and the load current is about 1.8 A. It can be observed in Figure 12 that the obtained boost factor from the experimental result is slightly lower than the theoretical value due to the parasitic components associated with diodes, switches, capacitors, or inductors applied in the prototype. Moreover, Figure 12b shows the experimental results for the DC-link voltage and inductor currents. It can be observed in Figure 12b that the inductor currents increase linearly in the shoot-through state and decrease linearly in the non-shoot-through state, which is in correspondence with theoretical analysis and simulation results. Meanwhile, the DC-link voltage is zero in the shoot-through state and nonzero in the non-shoot-through state, which matches well with the simulation results. Furthermore, the continuous input current can be ensured in the proposed topology by observing the inductor current $i_{L_1}$. Additionally, the gate signal $G_S$ and diode voltages are shown in Figure 12c. The peak diode voltage is equal to the peak DC-link voltage. Finally, the capacitor voltages of the proposed topology are shown in Figure 12d. It can be seen that the capacitor voltage $V_{{\mathrm{C}}_1}$ is boosted to 116 V, and it is the same as the DC-link peak voltage. Nevertheless, the capacitor voltages $V_{{\mathrm{C}}_2}$ and $V_{{\mathrm{C}}_3}$ are the same and almost equal to the input voltage (30 V).

In summary, the simulations and experimental results have validated the superior performance of the S-qZSI in terms of high voltage gain, continuous input current, and low voltage stresses on the capacitors.

5. Conclusions

This paper has presented a modified switched quasi-Z-source inverter (S-qZSI) based on a switched-impedance network. In the proposed S-qZSI, the boost capability is enhanced by minor modifications compared with other switched-based Z-source networks. Moreover, the proposed S-qZSI features a continuous input current, which makes it suitable for renewable energy applications. In order to show the effectiveness of the proposed S-qZSI, a benchmarking with selected topologies was carried out. The comparison reveals that the voltage stresses of the inverter bridge power switches are lower than the other selected topologies, while the stress of the capacitor remains low. Therefore, the lower rating devices can be utilized to decrease the cost. Finally, the simulation and experimental results shows the superior performance in terms of high boost capability, lower voltage stresses of switches and capacitors, and continuous input currents.