Design and Implementation of a Hybrid Single T-Type Double H-Bridge Multilevel Inverter (STDH-MLI) Topology

Abstract

Multilevel inverters are proficient in achieving a high-quality staircase output voltage waveform with a lower amount of harmonic content. In this paper, a new hybrid multilevel inverter topology based on the T-type and H-bridge module is presented. The proposed topology aims to achieve a higher number of levels utilizing a lower number of switches, direct current (dc) voltage sources, and voltage stresses across different switches. The basic unit of the proposed single T-type and double H-bridge multilevel inverter (STDH-MLI) produces 15 levels at the output using three dc voltage sources. The proposed topology can be extended by connecting a larger number of dc voltage sources in the T-type section. The nearest level control (NLC) switching technique is used to generate gate pulses for switches to achieve a high-quality output voltage waveform. In addition, a simplified way to achieve NLC is also described in the paper. A detailed comparison with other similar topologies is provided to set the benchmark of the proposed topology. Finally, experimental work is carried out to validate the performance of the proposed topology.

1. Introduction

Over the past two to three decades, multilevel inverters have become a favorite choice for industrial applications due to their advantages, such as better output voltage quality, reduced electromagnetic interference (EMI), a lower voltage rating of switches for higher voltage generation with high efficiency, and a decrease in the size of the filter compared to their two-level counterpart. Multilevel inverters (MLIs) arrange the power electronics components and direct current (dc) voltage sources with or without capacitors to achieve an output voltage waveform close to a sinusoidal waveform. Three conventional MLI topologies, i.e., neutral point clamped (NPC) multilevel inverter, flying capacitor (FC) multilevel inverter, and cascade H-bridge (CHB) multilevel inverter, have been extensively explored and commercialized. As the number of levels increases, the number of components increases significantly, i.e., clamping diodes with switches in NPC, flying capacitors in FC, and isolated dc voltage sources in CBH [1,2,3]. In order to overcome these drawbacks, hybrid MLIs have become an area of intense research [4,5].

A hybrid MLI topology has been divided into two sections. The first section is commonly known as a level generation unit, which generates the different voltage levels in unidirectional polarity. To convert the output of the level generation unit into an alternating quantity, an H-bridge structure is commonly used. The H-bridge generates both positive and negative polarities across the load. Several hybrid MLI topologies that employ an H-bridge have been proposed in the literature. Hinago and Koizumi in [6] suggested a hybrid topology. The proposed switched series/parallel sources (SSPS) topology has the ability to utilize the different dc voltage sources in series and parallel combinations to provide affability in terms of voltage and current obligations for different loads. A topology similar to [6] has been suggested in [7]. In this topology, only a series connection of different dc voltage sources is possible.

Another category of hybrid topologies has been suggested in [8,9,10,11]. These topologies have a notable difference in connecting an additional dc voltage source that precedes the H-bridge. In [8,9,10], the dc voltage source has been directly connected to the H-bridge. In such configurations, the number of levels has been reduced as one of the voltage sources will appear in each of the voltage levels across the load. This problem has been solved in [11], as the dc voltage source has been configured in a half bridge with two switches. With this configuration, the number of levels doubles. In all the topologies, the main problem has been the higher switch count to generate a particular number of levels at the output.

In recent years, there has been some improvement in the hybrid topologies. In [12], a hybrid single-phase MLI has been proposed employing one H-bridge and two power frequency transformers. Two dc voltage sources with 10 switches and two transformers were used to achieve 19 levels at the output having different transformer turn ratios. The use of two transformers made the topology bulky and costly. A single-phase hybrid seven-level MLI has been proposed in [13]. It uses one dc voltage source with three capacitors with eight switches. The use of capacitors in the topology conveys the problem of capacitor voltage balancing with additional losses associated with them. Similarly, another single-phase hybrid MLI topology for nine levels at the output by means of 12 switches and four capacitors was proposed in [14]. Likewise, a nine-level single-phase hybrid MLI has been reported in [15] for grid connection using 10 switches and three capacitors. In all these topologies, the use of an H-bridge increases the total standing voltage (TSV) of the topology as the switches connected to the H-bridge need to block the maximum output voltage.

Some topologies based on the T-type have also been published in several papers. References [16] and [17] present two similar topologies based on a back-to-back connection of T-types. Thirteen levels can be produced in the E-type [16] and 17 levels in the ST-type [17] using four dc voltage sources with 10 and 12 switches, respectively. Similarly, other MLI topologies have been proposed in [18,19,20,21,22,23,24,25,26,27,28].

This paper proposes a new hybrid multilevel inverter topology that combines a T-type MLI and an H-bridge to achieve a staircase output voltage. The proposed topology aims to achieve a larger number of levels with a reduction in the number of switches and dc voltage sources along with reduced voltage stress across switches. This paper is organized as follows. Section 2 gives the description and analysis of the proposed topology along with the mathematical formulation of TSV. A detailed comparative study with several recently proposed topologies has been carried out in Section 3. The control technique used for the proposed MLI has been described in Section 4, and Section 5 deals with the power loss analysis. The results and discussion are provided in Section 6. The proposed topology has been summarized in Section 7.

2. Description and Analysis of the Proposed Topology

2.1. Basic Unit of the Proposed Topology

Figure 1 depicts the circuit diagram of the basic unit of the proposed multilevel inverter topology. As shown in Figure 1, the basic unit consists of eight unidirectional switches and one bidirectional switch with three dc voltage sources. Two dc voltage sources with a magnitude of 3V_dc are connected on the left-hand side of the basic unit. These two dc voltage sources along with the bidirectional switch S₁ form the T-type section of the proposed basic unit. The T-type section is operated at a high voltage and a low frequency. The switches S₂–S₉ form two H-bridges, i.e., one H-bridge (H₁) formed by S₂, S₃, S₈, and S₉ and remaining switches S₄–S₇ form the other H-bridge (H₂) with a dc voltage source with a magnitude of V_dc. H₁ works at the low switching frequency and H₂ operates at the high switching frequency. The load is connected between these two H-bridges. Therefore, the proposed topology can be termed as a “Single-T Double H-bridge” (STDH) MLI. The different switching strategy of the proposed STDH-MLI to generate different voltage levels at the output is given in

Table 1. Switching Table of the Proposed Basic Unit.

S1	S2	S3	S4	S5	S6	S7	S8	S9	Vo
0	1	0	1	0	1	0	1	0	0
0	1	0	1	0	0	1	1	0	Vdc
1	0	0	0	1	1	0	1	0	2Vdc
1	0	0	0	1	0	1	1	0	3Vdc
1	0	0	1	0	0	1	1	0	4Vdc
0	0	1	0	1	1	0	1	0	5Vdc
0	0	1	0	1	0	1	1	0	6Vdc
0	0	1	1	0	0	1	1	0	7Vdc
0	0	1	0	1	0	1	0	1	0
0	0	1	0	1	1	0	0	1	−Vdc
1	0	0	1	0	0	1	0	1	−2Vdc
1	0	0	1	0	1	0	0	1	−3Vdc
1	0	0	0	1	1	0	0	1	−4Vdc
0	1	0	1	0	0	1	0	1	−5Vdc
0	1	0	1	0	1	0	0	1	−6Vdc
0	1	0	0	1	1	0	0	1	−7Vdc

. Similarly, Figure 2a–h demonstrate the different combinations of switches and dc voltage sources of the basic unit in the positive half cycle.

2.2. Generalized Structure of the Proposed Topology

To increase the number of levels at the output, the suggested basic unit can be extended as shown in Figure 3. This is done by adding more dc voltage sources to the T-type section. Therefore, when adding one dc voltage source, one bidirectional switch needs to be added to the basic unit. The equations for the proposed STDH-MLI with k number of dc voltage sources are given as:

$$\mathrm{Number}\mathrm{of}\mathrm{Levels}=N_{level}=n=3\left(2\mathrm{k}-1\right)$$

(1)

$$\mathrm{Number}\mathrm{of}\mathrm{Switches}=N_{switch}=2\mathrm{k}+4$$

(2)

$$\mathrm{Number}\mathrm{of}\mathrm{Driver}\mathrm{Circuits}=N_{driver}=\mathrm{k}+6$$

(3)

$$\mathrm{Variety}\mathrm{of}\mathrm{dc}\mathrm{sources}=N_{variety}=2$$

(4)

2.3. Calculation of Total Standing Voltage (TSV)

The total standing voltage (TSV) of the topology is an important parameter as it decides the voltage rating of switches to be used in the MLI. TSV is the sum of all the voltage stresses across each switch considering each level at the output. For the proposed STDH-MLI, TSV can be expressed as:

$$\mathrm{TSV}={\mathrm{TSV}}_{\mathrm{T}}+{\mathrm{TSV}}_{\mathrm{H}1}+{\mathrm{TSV}}_{\mathrm{H}2}$$

(5)

where ${\mathrm{TSV}}_{\mathrm{T}}$ is the TSV of the T-section consisting of all bidirectional switches ${\mathrm{S}}_{11}$ to ${\mathrm{S}}_{\mathrm{k}-2,\mathrm{k}-2}$. ${\mathrm{TSV}}_{\mathrm{H}1}$ and ${\mathrm{TSV}}_{\mathrm{H}2}$ represent the TSV of H-bridge H₁ (made up of ${\mathrm{S}}_2$, ${\mathrm{S}}_3$, ${\mathrm{S}}_8$, and ${\mathrm{S}}_9)$ and H-bridge H₂ consisting of switches ${\mathrm{S}}_4$ to ${\mathrm{S}}_7$, respectively. ${\mathrm{TSV}}_{\mathrm{T}}$ can be calculated as follows:

$${\mathrm{TSV}}_{\mathrm{T}}=\mathrm{M}\times 3{\mathrm{V}}_{\mathrm{dc}}$$

(6)

where M in terms of k is given by

$$\begin{array}{c}\mathrm{M}=\frac{3{\mathrm{k}}^2-4\mathrm{k}+1}{4} \mathrm{for} \mathrm{an} \mathrm{odd} \mathrm{number} \mathrm{of} \mathrm{k}\\ \mathrm{M}=\frac{3{\mathrm{k}}^2-4\mathrm{k}}{4} \mathrm{for} \mathrm{a} \mathrm{even} \mathrm{number} \mathrm{of} \mathrm{k}\end{array}$$

(7)

The voltage across each switch connected in H₁ is (k − 1)V₁ as all the switches of H₁ are connected to the dc voltage sources connected in the T-section. Therefore,

$${\mathrm{TSV}}_{\mathrm{H}1}=4\left(\mathrm{k}-1\right)\times 3{\mathrm{V}}_{\mathrm{dc}}$$

(8)

Similarly,

$${\mathrm{TSV}}_{\mathrm{H}2}=4{\mathrm{V}}_{\mathrm{dc}}$$

(9)

Therefore, from (6)–(9), total TSV of the proposed MLI is given as:

$$\mathrm{TSV}=\left(3\mathrm{M}+12\mathrm{k}-8\right){\mathrm{V}}_{\mathrm{dc}}$$

(10)

3. Comparative Study

3.1. Comparison of Basic Units

The performance of the proposed basic unit is determined by comparing with it with several new topologies with three dc voltage sources and is given in

Table 2. Quantitative Comparison of the Basic Unit with Topologies having Three direct current (dc) Voltage Sources.

Topology	A	B	C	D	E	TSV (×Vdc)	TVS/D
[18]	10	10	0	15	3	42	2.80
[19]	12	9	0	11	2	35	3.18
[20]	7	7	4	9	2	26	2.89
[21]	7	7	4	9	2	21	2.33
Proposed	10	9	0	15	2	31	2.07

. From Table 2, the proposed topology generates the maximum number of levels along with [18], but [18] has higher TSV. TSV is an important factor in the selection of switches. The proposed topology has the least TVS/N_level, which appears to be an essential factor for an MLI. In addition, the proposed topology does not use any power diode apart from the antiparallel diodes connected to the switches, which results in a lower amount of losses.

3.2. Comparison of Generalized Structure

The proposed topology can generate any number of levels using the generalized structure. The generalized structure has been compared with some similar MLI topologies to prove the superiority of the proposed topology. The comparison has been carried out in terms of the number of switches, the required number of driver circuits, the number of dc voltage sources, and TSV against the number of levels across the load. Figure 4a presents the variation of number of switches corresponding to the number of levels across the load. The proposed topology requires a lower number of switches with contrast to the other topologies as shown in Figure 4a. As the proposed topology uses bidirectional switches made up of two unidirectional switches connected in a common emitter configuration, the required number of driver circuits is less than the number of switches used in the topology. Figure 4b correlates the required number of driver circuits and the number of levels at the output. The proposed topology uses a minimal number of driver circuits compared to all other topologies used for the comparison.

A figure correlating the number of dc voltage sources with the number of levels across the load is shown in Figure 5a. As shown in the figure, the proposed topology requires a lower number of dc voltage sources except [17]. Similarly, the voltage stress represented as TSV has been shown in Figure 5b. The proposed topology has a lower TSV compared to [6,19]. From this comparison, the proposed topology has a lower number of switches, driver circuits, dc voltage sources, and TSV. The lower number of components along with the lower amount of TSV gives an upper edge to the proposed topology for low- and medium-voltage applications. The lower number of components also reduces the cost and size of the proposed topology.

4. Nearest Level Control Modulation Method

Several modulation techniques have been researched and applied to multilevel inverters, such as carrier-based (CB) PWM, Space Vector (SV) PWM, and selective harmonic elimination (SHE) PWM. CBPWM techniques use multiple carrier signals to generate gate pulses but cause higher switching losses. In SVPWM, the complexity of the algorithm increases as the number of levels at the output increases. Likewise, with SHEPWM, the calculation of switching angles becomes more and more complex with increases in the number of levels [29,30,31,32]. The nearest level control (NLC) is a low-switching-frequency PWM technique [33]. In the NLC method, the calculation time is reduced with the complexity in the implementation with an increase in the number of levels compared to SVPWM and SHEPWM. In this method, the sampled waveform can be generated by comparing the sinusoidal reference signal with the existing voltage level at the output as shown in Figure 6a. Figure 6b shows the general control diagram for the NLC. A simplified NLC implementation scheme is given in Figure 6c, where x = (n − 1)/2. The reference signal is multiplied by x to obtain the amplified signal. This signal is compared with different constant dc lines to generate the pulses, and a switching logic is used to combine different pulses to generate the switching pulses for the different switches.

5. Power Loss Analysis

For any power converter with power semiconductor devices, two major losses take place, namely conduction loss (P_c) and switching loss (P_sw) [27]. Equivalent resistance and On-state voltage drop of devices are the main factors that decide the amount of conduction loss. The conduction loss for a switch ($P_{c_S}$) and its antiparallel diode ($P_{c_d}$) is calculated as follows:

$$P_{c_S}=V_{S_{ON}}i\left(t\right)+R_s{i}^{\beta }\left(t\right)$$

(11)

$$P_{c_d}=V_{d_{ON}}i\left(t\right)+R_d{i}^2\left(t\right)$$

(12)

where $V_{S_{ON}}$ and $V_{d_{ON}}$ represent the On-state voltage drop of the switch and its antiparallel diode, respectively. $R_s$ and $R_d$ are the equivalent resistance of the switch and diode, respectively, and the constant $\beta$ depends upon the different parameters of the switch. All these factors associated with the conduction losses can be found from the datasheet of the switch. The average conduction loss for a fundamental period (2π) is calculated as:

$$P_c={\displaystyle \sum }_{x=1}^{N_s}\frac{1}{2\pi }{{\displaystyle \int }}_0^{2\pi }\left(V_{S_{ON}}i\left(t\right)+R_s{i}^{\beta }\left(t\right)\right)dt+{\displaystyle \sum }_{x=1}^{N_d}\frac{1}{2\pi }{{\displaystyle \int }}_0^{2\pi }\left(V_{d_{ON}}i\left(t\right)+R_d{i}^2\left(t\right)\right)dt.$$

(13)

Switching losses are another type of losses associated with semiconductor devices. Switching losses occur due to the non-ideal operations of the power semiconductor devices. To calculate switching losses, it is assumed that the voltage and current during turn-ON and turn-OFF vary linearly. Thus

$$P_{sw}=\left[{\displaystyle \sum }_{x=1}^{N_s}\left(N_{O{N}_x}{E}_{O{N}_x}+N_{OF{F}_x}{E}_{OF{F}_x}\right)\right]\times f$$

(14)

where $N_{O{N}_x}$ and $N_{OF{F}_x}$ represent the number of turn-ONs and turn-OFFs during one complete cycle for the x^th switch. $E_{O{N}_x}$ and $E_{OF{F}_x}$ are the energy losses during turn-ON and turn-OFF in one complete cycle for the x^th switch and its anti-parallel diode, respectively, and f represents the fundamental frequency of the output voltage. Therefore, total losses (P_t) is the sum of both conduction and switching losses, given by

$$P_t=P_c+P_{sw}.$$

(15)

Therefore, the efficiency ($\eta$) of the converter with output power P_o is given by

$$\eta =\frac{P_o}{P_o+P_t}\times 100\%.$$

(16)

The PLECS software has been used for the calculation of power loss of the semiconductor devices of the proposed topology. The thermal modeling of the proposed topology has been simulated using the parameters of the IGBT switch IKW20N60H3. The energy losses E_ON and E_OFF are associated with the ON-state current and OFF-state blocking voltages. For the selected IGBT, the curves of energy loss with respect to the ON-state current (i_ON) and OFF-state blocking voltage (V_block) are given in Figure 7. Figure 7a,b show the curve of energy loss for turn-ON losses and turn-OFF losses, respectively. Figure 7c relates the ON-state voltage drop with ON-state current and it is used for the calculation of the conduction losses.

Figure 8a shows the efficiency of the proposed converter with respect to the output power P_o. The estimated efficiency of the proposed converter comes out to be 97.8% at the output power of 50 W. The efficiency of the output power at 5 kW was found to be 93.7%. Furthermore, the proposed topology has been compared with the topology proposed in [18] in terms of efficiency and the results are shown in Figure 8b. To estimate the efficiency, NLCPWM was used with the same peak voltage for both topologies. It is clear from Figure 8b that the efficiency of the proposed topology is better compared to [18].

In terms of efficiency, the proposed topology has been analyzed with both low- and high-switching-frequency techniques. For the low-switching frequency, NLC is used and for the high-switching frequency, sinusoidal PWM (SPWM) is used with the in-phase disposition configuration of the carrier signals. Figure 9a–d show the output voltage waveform of the proposed topology with different switching frequencies and NLCPWM. For SPWM, the carrier frequency has been selected as 5 kHz, 2.5 kHz, and 1 kHz, and the respective 15-level output voltage is depicted in Figure 9a–c, respectively. Figure 9d shows the output voltage waveform with NLCPWM. For all the above four cases, the efficiency has been calculated and the different efficiency versus output power curves are shown in Figure 10. As shown in Figure 10, the proposed topology with NLC gives improved efficiency compared to SPWM.

In addition, the power loss distribution across the different switches has also been analyzed for the proposed topology with different loading conditions with NLCPWM. Figure 11a–d show the switching and conduction losses of different switches and their antiparallel diodes for different loading conditions. The power losses across the complementary switches are similar, i.e., switch S₂ and S₃ have the same conduction and switching losses as both switches operate for an equal duration with the same number of ON and OFF transitions. As the NLCPWM technique is used, the switching loss has a negligible impact on the total power loss, and conduction loss is the major contributor to the overall losses of the proposed topology.

6. Results and Discussion

To verify the performance of the proposed topology, different experimental tests have been performed on the prototype experimental setup as shown in Figure 12. TOSHIBA IGBT GT50J325 has been used as a switch for the topology. dSPACE CP1104 has been used to generate the gate pulses for all the switches using the NLC method described in Section 4. The gate drive circuits, made up of an NXP 74HC04N IC and an A3120 optocoupler, have been used to make the gate pulses suitable for proper IGBT operation.

A different test has been performed for the basic unit, which generates 15 levels across the load. The magnitude of the dc voltage source connected to the T-section has been selected as 90 V, and the magnitude of the dc voltage source connected to H₂ has been fixed to 30 V. This selection of dc voltage sources results in an output voltage having a peak magnitude of 210 V with a 30 V voltage step (V_dc = 30 V) as shown in Figure 13a.

The voltages stress across the switches has a crucial role in the design of an MLI topology. For the proposed basic unit, the voltage stress across switches has been analyzed and is shown in Figure 13b,c). The voltage stress across the bidirectional switch S₁ is shown in Figure 13b, which varies from zero to 90 V, i.e., 3 V_dc. The switches connected to H₁ (S₂, S₃, S₈, and S₉) have a maximum voltage stress equal to 6 V_dc, i.e., 180 V. The voltage stress across switches S₂ and S₃ is shown in Figure 13b. Similarly, for the switches of H₂ (S₄ to S₇), the maximum voltage stress has been fixed to V_dc, i.e., 30 V. The voltage stress across switches S₅ and S₇ along with the voltage stress of switch S₉ are demonstrated in Figure 13c.

The proposed basic unit has been tested under different loading conditions and the results are shown in Figure 14 and Figure 15. Figure 14a depicts the output voltage and current waveform with a purely resistive load having a magnitude of 100 Ω. With the resistive load, the current waveform is in phase with the voltage waveforms as shown in Figure 14a. The different output parameters captured by the power analyzer are provided in Figure 14b. For the 15-level output voltage with resistive load, the voltage total harmonic distortion (THD) is 4.9% and the current THD has a similar magnitude to the voltage THD. Furthermore, the output voltage and current waveforms with the series connected resistive-inductive (RL) load are shown in Figure 14c. The values of resistance and inductance have been selected as R = 100 Ω and L = 200 mH, respectively. With this load, the different output parameters are given in Figure 14d.

Additionally, the proposed topology has been analyzed with the change in the modulation indexes with a load of R = 100 Ω, L = 200 mH. Figure 15a shows the output voltage and current for the change in modulation index from 1.0 to 0.5 with RL load. Similarly, a change in modulation index from 0.2 to 1.0 is provided in Figure 15b. From all these figures, the proposed topology performs well under different loading conditions along with a change in the modulation indexes.

7. Conclusions

This paper presents the working concept of the proposed STDH-MLI, which is a hybrid combination of one T-Type section and two H-Bridges. The basic unit of the proposed topology is able to generate 15 levels at the output employing three dc voltage sources. Moreover, the expansion of the basic unit has been deliberated on with the mathematical formulation of the topology. A comparison with existing topologies approves the merit of the proposed topology in terms of ability to achieve a higher number of levels with a lower TSV using a low number of switches and total components. Finally, the performance of the proposed STDH-MLI is verified through several experimental results using the NLCPWM method.