# Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

^{*}

## Abstract

**:**

## 1. Introduction

#### 1.1. Background

#### 1.2. Literature Review

#### 1.3. Contributions and Paper Organization

- An introduction of a mathematical model for odd/even order sampling with memory considerations
- A simulation performance investigation of novel odd/even order sampling
- An experimental setup with laboratory equipment to investigate sampling frequency and memory performance
- A field programmable gate array (FPGA) application experimental setup to investigate the performance of odd/even order sampling when compared to other sampling schemes.

## 2. Materials and Methods

- Laboratory equipment, Excel, a simulation tool and FPGA implementation.
- Laboratory equipment such as an oscilloscope, spectrum analyzer, Radar signal synthesizer, and Excel were used during preliminary efforts to develop research assumptions for a feasible study. A four channel Tektronix oscilloscope with a maximum resolution of 10 million sampling points and a maximum operating frequency of 1 GHz was used to capture a sample for preliminary processing with Excel. A Tektronix spectrum analyzer with a maximum operating frequency of 26 GHz was used to evaluate a quadrature signal in time and frequency domains. An Anritsu signal generator with a maximum operating frequency of 20 GHz was used to generate a Radar signal. A simulation was conducted on Matlab Simulink and the delta-sigma model in reference [14] was used and modified to cater for an odd/even order sampling architecture. An ADL5380-EVALZ-ND I/Q demodulator was used as a quadrature demodulator. Xilinx Vivado was used for a FPGA firmware design, with MiniZed being the FPGA of choice.

- High level research assumptions were that odd/even order sampling would reduce the total sample number and signal frequency without affecting the dynamic range.
- An I/Q sine signal was designed on the Anritsu signal generator and was supplied as input to an I/Q demodulator.
- Outputs of the I/Q demodulator were connected to two channels of the oscilloscope.
- The two channels of the oscilloscope were captured and the signal was stored as comma-separated values (CSV) files for further analysis on Excel. Results were plotted using Excel figures.

- A derived mathematical model used to process the CSV captured sine signal from the oscilloscope.
- A simulation on Matlab Simulink was used investigate the performance of step size while evaluating the effect on dynamic range.
- A 1st order delta-sigma model was used in all simulation investigations and all results were plotted using Matlab figures.
- Four sampling schemes were implemented on Xilinx Vivado, one being the proposed novel odd/even order sampling scheme and the others were from the literature.
- Performance of these schemes were captured and exported to CSV using Integrated Logic Analyzer(ILA) from Vivado.
- CSV were further processed for SNR and results were plotted using Excel figures.

## 3. Results

#### 3.1. Derivation of Odd/Even Order Sampling I/Q Demodulator

#### 3.1.1. I/Q Demodulator

#### 3.1.2. Odd Order Sampling

#### 3.1.3. Even Order Sampling

#### 3.1.4. Odd/Even Order Sampling

_{n}in Equations (4) to (7) fall away. We introduce analog-to-digital converter tuning signal controlled by random access memory strobe. When the following modifications are applied to Equations (4) and (5), the new equation become Equations (10) and (11).

#### 3.2. Simulation Towards Investigation of Odd/even Order Sampling Step Size

#### 3.2.1. General Phase Performance

#### 3.2.2. Step Size, Dynamic Range, and Mean Square Error Performance

#### 3.3. Liborarory Investigation Towards Verification of High Level Research Assupmsions

#### 3.3.1. Experimental I/Q Signal Design

#### 3.3.2. Experimental I/Q Signal Acquisition

#### 3.3.3. Experimental I/Q Signal Odd/even Order Sampling

#### 3.4. FPGA Implementation Investigation Towards Verification of Practical Applications of New Odd/even Order Sampling and A Signal-to-Noise (SNR) Performance Comparison to the Literature Available on Sampling Schemes

#### 3.4.1. Verification of Practical Application of New Odd/even Order Sampling

#### 3.4.2. Signal-to-Noise (SNR) Performance Comparison to Literature Available Sampling Schemes

## 4. Discussion

## 5. Conclusions

- A simulation investigated step-size, dynamic range, and dynamic range error behavior. Results verified that odd/even ordered sampling can significantly reduce the sample frequency from 8 kHz to 2 kHz, while not adversely affecting the dynamic range.
- Laboratory experimentation investigated the feasibility of the research assumption that ordered sampling reduces sample frequency. Results verify this assumption using time and spectral analysis.
- Implementation experimentation the investigated feasibility of implementing ordered sampling on a FPGA platform in comparison to sampling architecture in the literature. We also investigated the SNR behavior of odd/even ordered sampling in comparison to Mod-∆, Mod-∆ (Gaussian), and Mod-∆ (Noise) literature. Results indicate that odd/even order sampling is the most economical method in comparison to architectures evaluated with resource utilization at 45%. SNR results were not conclusive for a sampling resolution below 8 bits, for a resolution between 8 bits and 11 bits odd/even ordered sampling is the second-best performer, while showing the best performance for a sampling resolution above 11 bits.

- Random frequency uniformly distributed [0, B)
- Amplitude is a square root of covariance.

## Author Contributions

## Funding

## Conflicts of Interest

## Nomenclature

RAM | Random Access Memory |

FPGA | Field Programmable Gate Array |

LUT | Look Up Table |

DSP | Digital Signal Processing |

ILA | Integrated Logic Analyzer |

RMS | Root Mean Square |

ARMS | Average Root Mean Square |

Probability Distribution Function | |

CDF | Cumulative Distribution Function |

PSD | Power Spectral Density |

AR-PSD | Autoregressive Power Spectral Density |

ADC | Analog-to-Digital Converter |

SNR | Signal-to-Noise Ratio |

SQNR | Signal-to-Quantization-Noise Ratio |

R | Bit Rate |

D | Distortion |

MASH | Multi-Stage Noise Shaping |

dB | Decibels |

dBm | Decibel-milliwatts |

dBFS | Decibels Relative to Full Scale |

dBTP | Decibels True Peak |

MSE | Mean Square Error |

DR | Dynamic Range |

Mod-∆ | Mod-Delta |

REW | Radar & Electronic Warfare |

PRI | Pulse Repetition Interval |

PRF | Pulse Repetition Frequency |

SAR | Synthetic Aperture Radar |

ISAR | Inverse Synthetic Aperture Radar |

EW | Electronic Warfare |

ECM | Electronic Counter Measure |

ECCM | Electronic Counter-Counter Measure |

ESM | Electronic Support Measure |

RGPO | Range Gate Pull Off |

VGPO | Velocity Gate Pull Off |

AGPO | Angle Gate Pull Off |

RSP | Radar Signal Processor |

DRFM | Digital Radio Frequency Memory |

FMCW | Frequency Modulated Continuous Wave |

AI | Artificial Intelligence |

ML | Machine Learning |

ANN | Artificial Neural Network |

BPNN | Back-Propagation Neural Network |

FNN | Fuzzy Neural Network |

GA-NN | Generic Neural Network |

GA | Generic Algorithm |

Hz | Hertz |

kHz | Kilohertz |

MHz | Megahertz |

GHz | Gigahertz |

I | Current |

V | Voltage |

DoE | Design of Experiment |

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**Figure 1.**This portrays the phase performance between 1st order delta-sigma and odd/even order sampling. The phase difference between 1st order delta-sigma and odd/even sampling was created for the design by the transport delay between the signals, and should be ignored for analysis. 1st delta-sigma is indicated by the yellow, odd order sampling by red and even order sampling by black. It should be noted there is a (n−1) phase lag between even order sampling (black) and odd order sampling (red).

**Figure 2.**This portrays the phase lag performance between odd and even order sampling. Odd order sampling is marked by black and even order sampling is marked by red. It should be noted that the (n−1) phase lag between even order sampling (red) and odd order sampling (black) varies per period interval.

**Figure 3.**This portrays the phase lag performance between odd and even order sampling. Odd order sampling was marked by black and even order sampling was by red. It should be noted that the (n−1) phase lag between even order sampling (red) and odd order sampling (black) varies per period interval.

**Figure 4.**The oscilloscope output performance of I/Q demodulator with I component connected to Channel 1 and Q connected to Channel 2.

**Figure 9.**FPGA architecture implementation results: (

**a**) Source signal which is in phase with I and odd/even order sampling results; (

**b**) Odd and even order sampling results with Vivado integrated logic analyzer (ILA) window configured to 1 kilobyte.

**Figure 12.**This figure presents SNR performance between the new odd/even order, Mod-∆, Mod-∆ (Gaussian) and Mod-∆ (Noise) sampling.

Variable | Description |
---|---|

s(t) | Complex signal |

I(t) | Inphase component |

Q(t) | Quadrature component |

W_{IF} | Intermediate Freq |

Variable | Description |
---|---|

I_{raw}(t) | Demodulated I component |

Q_{raw}(t) | Demodulated Q component |

a_{m}(t) | Demodulated amplitude |

φ_{m}(t) | Demodulated phase |

**Table 3.**I/Q demodulator odd 4th order digital mixing [2].

Sample No: (n) | 0 | 1 | 2 | 3 | 4 |
---|---|---|---|---|---|

I-coefficients | 0 | 1 | 0 | −1 | 0 |

Q-coefficients ^{1} | 0 | 0 | −1 | 0 | 1 |

^{1}Q coefficients is phase lag (n−1).

Variable | Description |
---|---|

I_{odd}(t) | Odd sampled I component |

Q_{even}(t) | Even sampled Q component |

T_{1,3}(t) | Odd sampling time |

C_{1,3} | FIR coefficients |

T_{2,4}(t) | Even sampling time |

∆ | Quantization error |

**Table 5.**A 4th order FIR filtering I/Q demodulator odd order digital mixing pattern [2].

Sample No: (n) | 0 | 1 | 2 | 3 | 4 |
---|---|---|---|---|---|

I-coefficients | 0 | 1 | 0 | −3 | 0 |

Q-coefficients ^{1} | 0 | 0 | −3 | 0 | 1 |

^{1}Q coefficients is phase lag (n−1), FIR filter introduces coefficient −3.

**Table 6.**I/Q demodulator for even 7th order digital mixing [1].

Sample No: (n) | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
---|---|---|---|---|---|---|---|---|

I-coefficients | 1 | 0 | −1 | 0 | 1 | 0 | −1 | 0 |

Q-coefficients ^{1} | 0 | 1 | 0 | −1 | 0 | 1 | 0 | −1 |

^{1}Q coefficients is phase lag (n−1).

**Table 7.**I/Q demodulator for odd 7th order digital mixing [1].

Sample No: (n) | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
---|---|---|---|---|---|---|---|---|

I-coefficients | 1 | 0 | −11 | 0 | 15 | 0 | −5 | 0 |

Q-coefficients ^{1} | 0 | 5 | 0 | −15 | 0 | 11 | 0 | −1 |

^{1}Q coefficients is phase lag (n−1).

Input Addr | Dual-Port Mem | Output Addr |
---|---|---|

0x00 | I (0) | 0x00 |

… | … | … |

0xFF | I (i) | 0xFF |

Reserved to guard data leak + 2-bit strobe | ||

0x109 | Q (0) | 0x109 |

… | … | … |

0x208 | Q (i) | 0x208 |

Bit No | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
---|---|---|---|---|---|---|---|---|

Bit Function | Strobe | Reserved | Reserved | Reserved | Reserved | Flag |

Variable | Description |

dRM | Dual-port memory |

wr_{s} | Memory write |

rd^{s} | Memory read |

S_{i} | Sample number |

s | Memory strobe |

Quantization Step Parameter | Simulation Measurement |
---|---|

∆T | 124.687 us |

∆Y | 0.1477 volts |

∆F | 8.020 kHz |

∆Y/∆T | 1.185 (Volts/ms) |

Quantization Step Parameter | Simulation Measurement |
---|---|

∆T | 378.747 us |

∆Y | 0.4120 volts |

∆F | 2.640 kHz |

∆Y/∆T | 1.088 (Volts/ms) |

Experimental Equipment | Equipment Range |
---|---|

Anritsu Signal Generator | 1 Hz to 20 GHz |

Tektronix Oscilloscope | 1 Hz to 1 GHz |

Tektronix Spectral Analyzer | 1 Hz to 26 GHz |

Connector Schedule | Electrical Schedule |
---|---|

RF_p | SMA to Waveguide from Signal Gen |

RF_n | No SMA connector PCB terminated |

I_p | SMA to Waveguide to Oscilloscope |

I_n | No SMA connector PCB terminated |

Q_p | SMA to Waveguide to Oscilloscope |

Q_n | No SMA connector PCB terminated |

V_cc | Croc Clips to Power Supply |

Ground | Croc Clips to Power Supply |

Measurements | Settings | ||
---|---|---|---|

∆ Overlap | Freq | Time/Div | Span |

19% | 1.004649 GHz | ||

450 us | 24.40 MHz |

Measurements | Settings | ||
---|---|---|---|

Amplitude | Freq | Time/Div | Span |

−72.56 dBm | 1.004649 GHz | ||

10 dB | 24.40 MHz |

Type | Measurements | Settings | ||
---|---|---|---|---|

Ch1 | Ch2 | Ch1 | Ch2 | |

Amplitude (P-P) | 4.92 V | 874 mV | 2 V/div | 200 mV/div |

Phase | 63.90° | 0.00° | 4 ns/div | 4 ns/div |

Sub Block | Functionality |
---|---|

Scalar Processing | Access to Registers as Datatype for Software |

Adaptable Hardware | Process Container access to Digital Logic(LUT), Pin/Ports, Registers, Block RAM |

Intelligent Processing | Access to a ground of DSP Slices for equation manipulation |

Description | Used | Available | Utilization |
---|---|---|---|

SliceUtilization | |||

Slice LUTs | 2044 | 14,400 | 14.19% |

LUT as Logic | 1828 | 14,400 | 12.69% |

LUT as Memory | 216 | 6000 | 3.60% |

SliceRegUtilization | |||

Reg as Flip Flop | 3158 | 28,800 | 10.97% |

Reg as Latch | 0 | 28,800 | 0.00% |

MultiplexerUtilization | |||

F7 Muxes | 52 | 8800 | 0.59% |

F8 Muxes | 5 | 4400 | 0.11% |

MemoryUtilization | |||

Black RAM | 1.5 | 50 | 3.00% |

DSPUtilization | |||

DSPs | 2 | 66 | 3.03% |

SpecificFeatureUtilization | |||

XADC | 0 | 1 | 0.00% |

Total Utilization | 48.15% |

Description | Used | Available | Utilization |
---|---|---|---|

SliceUtilization | |||

Slice LUTs | 2044 | 14,400 | 14.19% |

LUT as Logic | 1828 | 14,400 | 12.69% |

LUT as Memory | 216 | 6000 | 3.60% |

SliceRegUtilization | |||

Reg as Flip Flop | 3158 | 28,800 | 10.97% |

Reg as Latch | 0 | 28,800 | 0.00% |

MultiplexerUtilization | |||

F7 Muxes | 52 | 8800 | 0.59% |

F8 Muxes | 5 | 4400 | 0.11% |

MemoryUtilization | |||

Black RAM | 1.5 | 50 | 3.00% |

DSPUtilization | |||

DSPs | 20 | 66 | 30.30% |

SpecificFeatureUtilization | |||

XADC | 0 | 1 | 0.00% |

Total Utilization | 75.45% |

Description | Used | Available | Utilization |
---|---|---|---|

SliceUtilization | |||

Slice LUTs | 2044 | 14,400 | 14.19% |

LUT as Logic | 1828 | 14,400 | 12.69% |

LUT as Memory | 216 | 6000 | 3.60% |

SliceRegUtilization | |||

Reg as Flip Flop | 3158 | 28,800 | 10.97% |

Reg as Latch | 0 | 28,800 | 0.00% |

MultiplexerUtilization | |||

F7 Muxes | 52 | 8800 | 0.59% |

F8 Muxes | 5 | 4400 | 0.11% |

MemoryUtilization | |||

Black RAM | 1.5 | 50 | 3.00% |

DSPUtilization | |||

DSPs | 22 | 66 | 33.33% |

SpecificFeatureUtilization | |||

XADC | 0 | 1 | 0.00% |

Total Utilization | 78.48% |

Description | Used | Available | Utilization |
---|---|---|---|

SliceUtilization | |||

Slice LUTs | 2044 | 14,400 | 14.19% |

LUT as Logic | 1828 | 14,400 | 12.69% |

LUT as Memory | 216 | 6000 | 3.60% |

SliceRegUtilization | |||

Reg as Flip Flop | 3158 | 28,800 | 10.97% |

Reg as Latch | 0 | 28,800 | 0.00% |

MultiplexerUtilization | |||

F7 Muxes | 52 | 8800 | 0.59% |

F8 Muxes | 5 | 4400 | 0.11% |

MemoryUtilization | |||

Black RAM | 1.5 | 50 | 3.00% |

DSPUtilization | |||

DSPs | 27 | 66 | 40.91% |

SpecificFeatureUtilization | |||

XADC | 0 | 1 | 0.00% |

Total Utilization | 86.06% |

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Mfana, M.; Hasan, A.N.; Ahmed, A.
Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications. *Energies* **2019**, *12*, 4567.
https://doi.org/10.3390/en12234567

**AMA Style**

Mfana M, Hasan AN, Ahmed A.
Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications. *Energies*. 2019; 12(23):4567.
https://doi.org/10.3390/en12234567

**Chicago/Turabian Style**

Mfana, Madodana, Ali N. Hasan, and Ali Ahmed.
2019. "Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications" *Energies* 12, no. 23: 4567.
https://doi.org/10.3390/en12234567