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Article

A Practical Approach to the Design of a Highly Efficient PSFB DC-DC Converter for Server Applications

1
Infineon Technologies Austria AG, Siemenstraße 2, 9500 Villach, Austria
2
Department of Electronics and Computers Technology, University of Granada, 18071 Granada, Spain
*
Author to whom correspondence should be addressed.
Energies 2019, 12(19), 3723; https://doi.org/10.3390/en12193723
Received: 10 September 2019 / Revised: 23 September 2019 / Accepted: 26 September 2019 / Published: 29 September 2019
(This article belongs to the Section F: Electrical Engineering)

Abstract

:
The phase shift full bridge (PSFB) is a widely known isolated DC-DC converter topology commonly used in medium to high power applications, and one of the best candidates for the front-end DC-DC converter in server power supplies. Since the server power supplies consume an enormous amount of power, the most critical issue is to achieve high efficiency. Several organizations promoting electrical energy efficiency, like the 80 PLUS, keep introducing higher efficiency certifications with growing requirements extending also to light loads. The design of a high efficiency PSFB converter is a complex problem with many degrees of freedom which requires of a sufficiently accurate modeling of the losses and of efficient design criteria. In this work a losses model of the converter is proposed as well as design guidelines for the efficiency optimization of PSFB converter. The model and the criteria are tested with the redesign of an existing reference PSFB converter of 1400 W for server applications, with wide input voltage range, nominal 400 V input and 12 V output; achieving 95.85% of efficiency at 50% of the load. A new optimized prototype of PSFB was built with the same specifications, achieving a peak efficiency of 96.68% at 50% of the load.

Graphical Abstract

1. Introduction

As the number of devices connected to the Internet and the available services increase, the volume of data transferred and processed by server systems is growing exponentially. The amount of data centers is rising consequently. Therefore, the server power systems are under continuous development. Since the server power supplies consume massive amounts of power, the most critical matter is to achieve high efficiency [1]. To promote electrical energy efficiency of server systems several organizations have setup initiatives like climate-savers-computing-initiative (CSCI) [2] and 80 PLUS [3] which certifies individual power supplies corresponding to their performance level. CSCI and 80 PLUS keep introducing higher efficiency certifications such as Gold, Platinum, and Titanium with growing requirements extending also to light loads (Table 1). Noticeably, the required efficiency at 50% load condition for each certification is the highest and the most difficult to achieve, based on the redundant configuration of the server power system. The redundant structure is widely used in the server power supply applications because of the very high reliability demand characteristics of the application. A redundant structure means parallel power supplies sharing the total load and capable of taking over in case of a fault in one of the supplies [4,5]. Moreover, low power consumption of the server system in idle/sleep is becoming increasingly important. This is confirmed by efficiency requirements extending down to 10% load in 80 PLUS Titanium [6]. Meanwhile the power rating of the power supply unit (PSU) tends to increase to maximize the performance of the server system. A smaller volume requirement allows a greater processing power at a lower cost in the building infrastructure [7]. This leads to very high power density server PSU because the server system is required to reduce its mechanical size [6].
A server PSU is primarily composed of two stages: a back-end power factor correction (PFC) AC-DC stage powered by universal AC input (90~265 VAC rms) followed by a front-end DC-DC isolated step-down converter [8]. Among these parts, the front-end DC-DC converter stage has the biggest impact on the efficiency of the server power system because of its high conversion ratio of voltages and currents, and the required isolation transformer, which results in large power losses [1]. The output voltage typically ranges between 12 VDC to 48 VDC. In the literature many different topologies have been proposed for this application. The DC-DC stage can be a single switch isolated converter like a fly-back for low power applications (under 250 W), and half bridge converter or full bridge converter for higher power applications [8,9].
Half bridge LLC resonant converter is a popular isolated DC-DC topology. This is mostly due to its high efficiency and simple circuit structure, which helps to achieve high power density. However, the switching frequency (Fsw) span of the LLC is very wide, especially when a wide gain range of operation is required [10,11]. DC-DC converters with a wide gain range capability are common in many power conversion applications. Server power supplies have demanding requirements on continuity and reliability which includes hold-up time operation. During hold-up time the AC input of the back-end AC-DC converter is lost, while the DC-DC should maintain a stable output. During this time the intermediate storage capacitor continues to provide the energy while the DC bus voltage drops considerably. Therefore, the DC-DC converter needs to work normally with a wide input voltage range [10].
The other most common alternative for high efficiency and high power density DC-DC converters in server PSU is the PSFB with synchronous rectifier (SR) MOSFETs, external resonant inductor and clamping diodes, shown in Figure 1. Its most remarkable characteristic is the wide zero-voltage-switching (ZVS) range from mid to full load [6], nearly suppressing switching losses, which are especially high for high voltage (HV) devices in hard-switched converters [12]. Moreover, the constant switching frequency allows a simple control and EMI design [9,13]. One of the major advantages of PSFB over other resonant soft-switching topologies is the comparatively lower rms currents through the converter thanks to the output filter inductance. However, hold-up time regulation requirements means the PSFB converter cannot to be operated with its maximum effective duty in nominal conditions and causes a long freewheeling period [14]. The freewheeling period increases circulating currents and conduction losses [1].
The design of the DC-DC converter has many degrees of freedom which complicates the selection of the components values resulting in the best solution. Finding the design solution with the highest power density and/or efficiency and/or cost requires an optimization procedure based on comprehensive analytical models and equations considering the losses in the converter components [9,15]. With this procedure, the optimal design parameters could be determined. In [13] a design process is presented to reach the point of highest efficiency ηmax and highest power density ρmax for a 5 kW PSFB DC-DC converter. The design process is based on an automatic optimization procedure which finds the optimal component values of the converter system. The space of solutions is limited by a curve in the η-ρ-plane, called the Pareto front, which presents the optimal points for varying weights of the efficiency and of the power density [13]. However, the automated process obscures the nature of the design parameters influence on the converter behavior, the design parameter interdependencies and limits the design engineer understanding of the converter.
In this work we present a complete losses model of the PSFB, which should prove useful for practicing engineers in their understanding on the origin of losses in the converter. The provided set of equations is based on a simplified model of the PSFB: all capacitances are linear; it does not include the clamping diodes; and it does not include the secondary side rectifiers’ capacitance. Furthermore, possible improvements in the calculation of losses will be discussed. Those and other additional considerations have been included by the authors in an extended set of equations, excluded from this document for clarity. The design criteria for a semi-automated design process presented in the following section has been performed on the authors’ extended version of the model. The losses model is tested, and the design criteria is demonstrated with the design of a PSFB DC-DC 1.4 kW 12 V output converter for server applications. The optimized PSFB design is compared to a reference converter with the same specifications. The rest of this paper is organized as follows: In Section 2 we propose a comprehensive losses model for the PSFB converter. The model is later used in Section 3 to analyze the influence of several of the design parameters in the converter performance. Section 3 also includes design guidelines or criteria for a semi-automated design procedure. In Section 4 the losses model and the design criteria have been applied to optimize a 1.4 kW PSFB DC-DC converter with 12 V output for server applications. Section 5 presents a summary of results comparing a previous reference design of PSFB with the new optimized prototype. Finally, Section 6 presents a summary of conclusions from this work.

2. Losses Model

A sufficiently detailed and accurate losses analysis model is necessary in order to perform efficiency optimization. The losses model and the design procedure should be a trade-off between accuracy and usability. Excessively precise and accurate estimations may lead to heavy computation requirements and long calculation times which makes the design process, iterative by nature, slow and tedious. Moreover, the complexity of the problem and the difficulty of estimating the real values of parameters in the circuit makes a precise estimation impractical. Ideally, the losses model is updated later on or corrected based on the results of the real hardware, giving more accurate results for each design iteration. The power losses analysis is discussed in this section to help understand where the losses are originated. There are three types of power losses for a switching power converter, as follows [15]: conduction losses, switching losses (including gate-driving power losses), and magnetic core losses.
The PSFB converter’s operation can be classified into discontinuous conduction mode (DCM), if the output filter inductor current ripple is higher than the average output or continuous conduction mode (CCM) otherwise. The circuit analysis in CCM is quite different from that in DCM because of the different operation modes [15]. In this work we will consider only the CCM working mode (the proposed losses model does not include DCM operation). The high-efficiency designs operate in CCM in all load ranges of interest. Moreover, the DCM control of the SRs could be challenging. Therefore, the PSFB converter is normally preferred not to operate in DCM [16].

2.1. Conduction Losses

These losses are caused by the currents passing through the parasitic resistances in the circuit, such as on the resistance of the switches RDS(on), the transformer, and inductor winding resistance. These losses can be calculated with the equivalent resistance and the rms current value in the different components of the converter [15].

2.1.1. Transformer Conduction Losses

The principles of operation of the PSFB converter have been already widely covered in the literature [17]. Briefly, the PSFB converter has three main working modes, which can be identified in Figure 2:
  • Effective duty (Deff). In this mode the primary side bulk voltage (Vin) is applied to the resonant inductance Lr and the primary side of the transformer. Power is being transferred from primary to secondary through the transformer (overlap of current and voltage of same sign).
  • Duty losses (Dloss). Before the next power transfer the current has to reverse polarity on the primary side of the transformer. The current through the resonant inductance (Lr) and leakage of the transformer (Llkg) require a certain time to reach the reflected output current with reverse sign.
  • Freewheeling duty (Dfrew). During the remaining time the current recirculates on the primary side without effective power transfer (there is no overlap of current and voltage on the primary side of the transformer) while it freewheels on the secondary side.
Figure 2 shows a simplified representation of the primary side current in a PSFB converter: all capacitances are linear; it does not include the clamping diodes; and it does not include the secondary side rectifiers’ capacitance. The enclosed area between iTr and iLm corresponds to the reflected secondary current during Deff, while power is being transferred from the primary to the secondary. The enclosed shaded areas correspond to currents recirculating on the primary side without effective power being delivered to the secondary side. From Figure 2 it can be inferred that two parameters have the most impact on the circulating currents: the effective duty (Deff) and the magnetizing current (iLm).
The current passing through the primary side of the transformer, excluding the effect of the magnetizing inductance, can be calculated with Equations (1)–(4). The secondary side reflected current could be calculated from Equations (1)–(4) by multiplying the turns ratio of transformer n.
{ iT r = V in L r + L lkg t - IT r , lag ,    t [ 0 , D loss T 2 ] iT r = ( V in V o n ) L r + L lkg + L o n 2 ( t D loss T 2 ) + IT r , pwr ,    t [ D loss T 2 , ( D eff + D loss ) T 2 ] iT r = V o n L r + L lkg + L o n 2 ( t - ( D eff + D loss ) T 2 ) + IT r , lead ,    t [ ( D eff + D loss ) T 2 , T 2 ]
n = N p N s
IT r , pwr = n ( IL o , avg Δ IL o 2 )
IT r , lead = n ( IL o , avg + Δ IL o 2 )
The magnetizing current is proportional to the input voltage and inversely proportional to the magnetizing inductance. It can be calculated with Equations (5) and (6):
{ iL m = - IL m , pk ,    t [ 0 , D loss T 2 ] iL m = V in L m + L r + L lkg ( t D loss T 2 ) IL m , pk ,    t [ D loss T 2 , ( D eff + D loss ) T 2 ] iL m = IL m , pk ,    t [ ( D eff + D loss ) T 2 , T 2 ]
iL m , pk = D eff V in T 2 ( L m + L r + L lkg ) D eff V in T 2 L m
Taking into account the magnetizing current the resulting primary side current can be calculated with Equations (7)–(9):
{ i p = V in L r + L lkg t - I p , lag ,    t [ 0 , D loss T 2 ] i p = i Tr + i m + I p , pwr ,    t [ D loss T 2 , ( D eff + D loss ) T 2 ] i p = i Tr + i m + I p , lead ,    t [ ( D eff + D loss ) T 2 , T 2 ]
I p , pwr = IT r , pwr IL m , pk
I p , lead = IT r , lead + IL m , pk
The rms current of the primary side of the transformer and secondary side of the transformer can be calculated from the previous equations which result in Equations (10)–(12):
I p , rms 2 = 2 T [ 0 D loss T 2 i p 2 dt + D loss T 2 ( D eff + D loss ) T 2 i p 2 dt + ( D eff + D loss ) T 2 T 2 i p 2 dt ]
I p , rms 2 = 1 3 ( ( I p , pwr 2 + I p , lead 2 + I p , pwr I p , lead ) D eff    + ( I p , lag 2 + I p , lead 2 + I p , lag I p , lead ) D frew    + ( I p , lag 2 + I p , pwr 2 + I p , pwr I p , lag ) D loss )
I s , rms 2 = n 2 3 ( ( IT r , pwr 2 + IT r , lead 2 + IT r , pwr IT r , lead ) D eff    + ( IT r , lag 2 + IT r , lead 2 + IT r , lag IT r , lead ) D frew    + ( IT r , lag 2 + IT r , pwr 2 + IT r , pwr IT r , lag ) D loss )
The conduction losses of the transformer can be estimated with the rms currents and Equation (13), where RTr,p stands for the primary side equivalent resistance of the transformer, Lr,ESR for the equivalent resistance of the resonant inductance, and RTr,s for the equivalent resistance of the secondary side of the transformer. Additionally, the contribution to conduction losses of the printed circuit board (PCB) could be added both in the primary and in the secondary of the converter, which have a noticeable impact in high output current converters.
P cond , Tr = I p , rms 2 ( R Tr , p + L r , ESR ) + I s , rms 2 R Tr , s
The skin and proximity effects increase the equivalent resistance of the windings and should be included for an accurate estimation of the transformer conduction losses. The magnetic fields generated by the alternating currents through the windings reduce the effective conduction area of the conductor itself (skin) and of other surrounding conductors (proximity). The studies in [18] show that the proximity effect dominates at high frequencies.
In the authors’ extended model, the AC resistance RAC of the primary and secondary windings of the transformer was estimated at different frequencies with finite element analysis (FEA) software [19]. The spectrum of the transformer’s primary and secondary currents was calculated from the previously analyzed waveforms. The total conduction losses was approximated by the sum of the rms current for each of the frequency components multiplied by the RAC at that frequency.

2.1.2. Primary Side HV MOSFETs

As suggested in [20] the power losses of the leading and lagging legs, which is dependent on MOSFETs current and voltage waveforms, should be analyzed separately. Therefore, the key waveforms for the MOSFETs in both of the primary side full bridge legs are shown in Figure 3 and will be described analytically. The proposed loss model is precise enough and easily computable using datasheet parameters.
The current waveform for the lagging leg (Q1, Q2 in Figure 1) can be calculated with Equation (14):
{ i Q 1 = V in L r + L lkg t - I p , lag ,    t [ 0 , D loss T 2 ] i Q 1 = ( V in V o n ) L r + L lkg + L o n 2 ( t D loss T 2 ) + I p , pwr ,    t [ D loss T 2 , ( D eff + D loss ) T 2 ] i Q 1 = 0 ,    t [ ( D eff + D loss ) T 2 , T ]
The current waveform for the leading leg (Q3, Q4 in Figure 1) can be calculated with Equation (15):
{ i Q 3 = V o n L r + L lkg + L o n 2 ( t - ( D eff + D loss ) T 2 ) - I p , lead ,    t [ ( D eff + D loss ) T 2 , T 2 ] i Q 3 = V in L r + L lkg ( t - T 2 ) - I p , lag ,    t [ T 2 , T 2 ( 1 + D loss ) ] i Q 3 = ( V in V o n ) L r + L lkg + L o n 2 ( t - ( 1 + D loss ) T 2 ) + I p , pwr ,    t [ T 2 ( 1 + D loss ) , T 2 ( 1 + D loss + D eff ) ]
The rms currents of both legs are equal in this simplified model, calculated from the previous formulas and resulting in Equation (16):
I Q 1 - 4 , rms 2 = 1 6 ( ( I p , pwr 2 + I p , lead 2 + I p , pwr I p , lead ) D eff    + ( I p , lag 2 + I p , lead 2 + I p , lag I p , lead ) D frew    + ( I p , lag 2 + I p , pwr 2 + I p , pwr I p , lag ) D loss ) = I Q 3 , rms 2
The conduction losses of the HV switches can be estimated from their rms currents with Equation (17), where RDS(on) stands for the equivalent resistance of the MOSFETs. Note that the RDS(on) of MOSFETs increases with temperature and it is also influenced by the gate driving voltage. Most of the conduction losses, like in MOSFETs, increase with temperature. This should be taken into account in the computation of the equivalent resistance of the components.
P cond , HV = 4 I Q 1 4 , rms 2 R DS ( on ) , p
In the authors’ extended model, the equivalent resistance of MOSFETs is estimated at the operating junction temperature TJ from their temperature coefficient, available in the manufacturer’s datasheet. Since the conduction losses are consequently updated, the temperature is recalculated until the solution of the equations converge. The process is also performed for other converter components: transformer windings, transformer core, secondary side rectifiers, PCB and output inductor windings. The iterative calculation can be easily automated in a computer (e.g., in a calculation sheet).
The estimations of components’ temperature require additional values for the thermal impedances, for example from junction to air for the HV and the low voltage (LV) MOSFETs. This was estimated with thermal simulation tools and thermal captures of the real hardware.
Additionally, the conduction losses of the HV MOSFETs body diode could be estimated accounting for the turn on delay of the switches, so-called dead times. Not included here for simplicity, since for a reasonably well-adjusted control of the dead times the body diode contribution is minor in silicon devices. Moreover, because of the strong non-linearity of the output capacitance in modern super-junction MOSFETs, the equivalent Coss in the depletion region is big, which enables relatively high tolerance for the turn on delay prior to the body diode conducts.

2.1.3. Secondary Side Rectifier LV MOSFETs

The Schottky barrier diode (SBD) or fast recovery diode (FRD) are commonly used as secondary side rectification devices in PSFB DC-DC converters because of their low cost and simplified control of the converter. However, the forward voltage drop of diodes cause relatively high conduction losses. By replacing the diode with an active switching element, the so called synchronous rectifier (SR), the losses can be notably reduced [21].
The rectification stage may have different configurations: center tapped, current doubler or full bridge [17]. Although these alternatives have no major impact on the working principles of the converter, they do have a significant impact on the current and voltage stress over the rectification devices and their related conduction and switching losses. The blocking voltage of the secondary side devices is two times the transformer reflected secondary voltage for center tapped and current doubler, or one time the transformer reflected secondary voltage for full bridge. However, the effective RDS(on) is twice as big for full bridge rectification [22]. Therefore, current doubler and center tapped rectifiers are the most appropriate for low voltage and high current applications. In [23] both configurations are analyzed and compared. The center tapped rectifier presents only one output inductor, which operates at double the switching frequency of the semiconductors, becoming an interesting alternative at low and medium current applications.
The current of the SRs (Q5, Q6 in Figure 1) is plotted in Figure 4 and can be calculated with Equations (18)–(21):
{ i Q 5 = IL o , pwr D loss T 2 ,    t [ 0 , D loss T 2 ] i Q 5 = ( V in n V o ) L r + L 1 kg n 2 + L o ( t D loss T 2 ) + IL o , pwr ,    t [ D loss T 2 , ( D eff + D loss ) T 2 ] i Q 5 = V o L r + L lkg + L o n 2 ( t - ( D eff + D loss ) T 2 ) + IL o , lead ,    t [ ( D eff + D loss ) T 2 , T 2 ]
IL o , pwr = n ( IL o , avg Δ IL o 2 )
Δ IL o = T 2 ( V in n V o ) D eff L r + L lkg n 2 + L o
IL o , lead = n ( IL o , avg + Δ IL o 2 )
The rms currents of both legs are equal in this ideal case and can be calculated from the previous formulas as expressed by Equation (22):
I Q 5 6 , rms 2 = 1 6 ( IL o , pwr 2 D loss + ( IL o , pwr 2 + IL o , lead 2 + IL o , pwr IL o , lead ) D eff + ( IL o , pwr 2 + IL o , lag 2 + IL o , pwr IL o , lag ) D frew ) = I Q 6 , rms 2
Out of the rms currents the conduction losses of the secondary side rectifiers can be estimated with Equation (23) where RDS(on),SR stands for the equivalent resistance of the secondary side switches:
P cond , SR = 2 I Q 5 6 , rms 2 R DS ( on ) , SR
Additionally, the conduction losses of the body diode of the secondary side rectifiers could be estimated accounting for the unavoidable turn on and turn off delays of the switches. Not included here for simplicity, since for a good adjusted control of the SRs the body diode contribution is minor in silicon devices.

2.1.4. Input and Output Filter

The output filter includes the output choke Lo and the output capacitance of the converter Co. The input filter includes the bulk capacitance between the back-end AC-DC converter and the front-end DC-DC converter. In reality part of the current ripple through the input filter caused by the DC-DC stage is cancelled by the output current ripple of the AC-DC converter but, for simplicity, we will only consider the rms current of the DC-DC as a stand-alone converter.
The current of the output choke is plotted in Figure 5 and can be calculated with Equation (24):
{ iL o = IL o , avg - Δ IL o 2 + ( V in n V o ) L r + L lkg n 2 + L o ( t D loss T 2 ) ,    t [ D loss T 2 , ( D eff + D loss ) T 2 ] iL o = IL o , avg + Δ IL o 2 V o ( t ( D eff + D loss ) T 2 ) L r + L lkg n 2 + L o ,    t [ ( D eff + D loss ) T 2 , ( 1 + D loss ) T 2 ]
The rms current through the output choke can be estimated with Equation (25):
IL o , rms 2 = 1 3 ( ( IL o , avg Δ IL o 2 ) 2 + ( IL o , avg + Δ IL o 2 ) 2 + ( IL o , avg Δ IL o 2 ) ( IL o , avg + Δ IL o 2 ) )
The current of the output capacitor can be calculated with Equation (26):
{ iC o = + ( V in n V o ) L r + L lkg n 2 + L o ( t D loss T 2 ) - Δ IL o 2 , t [ D loss T 2 , ( D eff + D loss ) T 2 ] iC o = Δ IL o 2 V o ( t ( D eff + D loss ) T 2 ) L r + L lkg n 2 + L o , t [ ( D eff + D loss ) T 2 , ( 1 + D loss ) T 2 ]
The rms current through the output capacitor can be estimated with Equation (27):
IC o , rms 2 = 1 3 ( Δ IL o 2 ) 2
The current through the input capacitor can be calculated with Equations (28) and (29):
{ iC in = I p , lag I in , avg V in L r + L lkg t , t [ 0 , D loss T 2 ] iC in = I p , pwr I in , avg ( V in V o n ) L r + L lkg + L o n 2 ( t D loss T 2 ) , t [ D loss T 2 , ( D eff + D loss ) T 2 ] iC in = I in , avg , t [ ( D eff + D loss ) T 2 , T ]
I in , avg = [ ( I p , lag + I p , pwr 2 I p , pwr ) D loss + ( I p , lead I p , pwr 2 I p , lead ) D eff ]
The rms current through the input capacitor can be estimated with Equation (30):
IC in , rms 2 = 1 3 [ ( ( I p , lag + I in , avg ) 2 + ( I in , avg I p , pwr ) 2    + ( I p , lag + I in , avg ) ( I in , avg I p , pwr ) ) D loss    + ( ( I in , avg I p , lead ) 2 + ( I in , avg I p , pwr ) 2    + ( I in , avg I p , lead ) ( I in , avg I p , pwr ) ) D eff ] + I in , avg 2 D frew
The conduction losses of the input and output filter can be estimated with the rms currents and Equation (31) where Cin,ESR stands for the equivalent resistance of the input capacitor, Co,ESR stands for the equivalent resistance of the output capacitor, and Lo,ESR stands for the equivalent series resistance of the output choke:
P cond , filter = IL o , rms 2 L o , ESR + IC in , rms 2 C in , ESR + IC o , rms 2 C o , ESR

2.2. Switching and Driving Losses

The voltage and current crossover during switching transitions results in switching power losses. Additionally, charging and discharging of the MOSFETs gate capacitance causes gate-driving power losses [15].

2.2.1. Primary Side HV MOSFETs Switching and Driving Losses

If the primary side MOSFETs operate under zero voltage switching, then there is no overlap between voltage and current, and transitions could be considered near lossless. However, it is known that in modern super-junction devices the charging and discharging of the device output capacitance shows a hysteresis which is the source of additional power losses that should be considered [24].
The minimum energy required to achieve ZVS transitions for the lagging and the leading leg can be estimated with Equations (32) and (33), with Cleading equal to the sum of capacitances C3 and C4, and Clagging equal to the sum of C1 and C2. The lumped capacitance of the transformer CTr constitutes an important contribution to the leading leg transition but it does not have an influence on the lagging leg.
V in 2 2 ( C leading + C tr ) ( IL r , lead 2 2 L r + IL lkg , lead 2 2 L lkg + IL o , lead 2 2 L o )
V in 2 2 C lagging ( IL r , lag 2 2 L r + IL lkg , lag 2 2 L lkg )
An efficiency optimized PSFB design operates in full or nearly full ZVS in all load ranges. The ZVS is especially important at light and medium loads, where the switching losses become dominant [15,25]. During partial ZVS the capacitance of the switches is not fully discharged when the device turns on. For modern HV super-junction MOSFETs the remaining losses are not significative [26]. The use of an external resonant inductance (Lr) in the primary side of a PSFB, while increasing the component count, helps achieving ZVS in light to medium load conditions and thus increases the overall efficiency of the converter. Although it is possible to increase the leakage of the transformer for the same purpose, using an external resonant inductance on the primary side of the converter and placing clamping diodes between the transformer and Lr helps to reduce the secondary side rectifiers overshoot as well as reduce their switching/commutation-related losses [27,28]. The solution, previously reported in the literature, is analyzed in detail in [29].
To achieve full ZVS, whenever there is enough energy available, a minimum dead time is also required for the transition of the drain voltage. The time it takes for the transition to happen depends on the transfer of energy from the inductances to the capacitances involved in the resonance. The output capacitance of modern MOSFETs is non-linear, and an accurate estimation of the transition times is not straightforward. A simple approximation can be estimated with Equation (34), where the capacitance is modeled by an equivalent time related fixed value of capacitance (Co(tr)) and the current from the inductances is considered also as a constant current source. Co(tr) is a parameter often provided by the manufacturer in the datasheet of the device.
T ZVS 2 C O ( tr ) IL V in
However, if there is not enough energy to achieve full ZVS, the transition time could be better approximated by the resonance between the inductors and the capacitors (Equations (35) and (36)). Since the reflected value of Lo is relatively big the transition of the leading leg can be well approximated by the previous linear model in all working conditions of the converter. However, for the lagging leg, the dead time has to match one fourth of the resonance period to switch at the minimum possible voltage.
T ZVS , leading 1 4 ω 1 = π 2 2 C o ( tr ) ( L lkg + L r + L o n 2 )
T ZVS , lagging 1 4 ω 1 = π 2 2 C o ( tr ) ( L lkg + L r )
Assuming the dead time to be always optimum (with the devices switching at the minimum possible drain voltage), the switching losses can be estimated with Equation (37) where EOFF is a function of the current and voltage overlap during the turn off transition. In general, for modern super-junction MOSFETs EOFF is relatively small, but not zero.
P SW , p = P SW , ZVS E OFF ( i , v ) F SW   ,   v = V DS 0
If the energy is not enough to achieve the ZVS part or all the energy stored in the output capacitance is dissipated, then the switching losses become Equation (38) where EON is a function of the current and drain voltage overlap and the EOSS is the stored energy in the output capacitance of the switch, which is also a function of the drain voltage.
P SW , p = P SW , HARD ( E ON ( i , v ) + E OSS ( v ) ) F SW   ,   v = V DS 0
The switching losses could be calculated, measured or simulated and tabulated for different values of current and switching voltages. The switching losses are computationally costly to calculate accurately. Moreover, it is difficult to estimate the real layout parasitics which have a relatively big impact on the losses. Therefore, in the authors’ extended model, the switching losses were interpolated from a table extracted from experimental measurements and characterization.
The driving losses are a function of the driving voltage Vdrive and the switching frequency. The reader may note that the gate charge differs in soft switching (ZVS) (Equation (39)) and hard switching (Equation (40)). In ZVS, the Qgd is supplied by the power stage during the resonant transition prior to the charge of the switch input capacitance from the driver path.
P drive , p = 4 ( Q g Q gd ) V drive F SW η bias   ,   v = V DS > 0
P drive , p = 4 Q g V drive F SW η bias   ,   v = V DS 0

2.2.2. Secondary Side LV MOSFETs Switching and Driving Losses

It was mathematically demonstrated in [30,31] that charging a capacitor inevitably causes energy losses. When charged through a resistive path the resistor dissipates energy equal to the one eventually stored (Equations (41)–(43)). The analysis shows that a capacitor can be charged with only a modest energy loss in a series RLC circuit only if the source is disconnected after ½ resonance cycle. Otherwise the remaining energy is dissipated during the dampening of the resonance and the energy loss becomes also equal to the stored. Their analysis is consistent with the formula for the estimation of switching losses in SRs in [32].
E sourced = E stored + E loss = ( 2 Q oss + 2 Q rr ) V in n
E loss = ( Q oss + 2 Q rr ) V in n ,   E stored = Q oss V in n
P sw = 2 F sw ( Q oss + 2 Q rr ) V in n
When using clamping diodes on the primary side of the converter part of the energy of the resonance is recovered. During the charge of Qrr and Qoss of the secondary side rectification devices an equal energy is stored in the inductances along the charging path (Lr, Llkg). It follows that the larger Lr is in relation to Llkg, the more energy it stores comparatively. Due to the action of the primary side clamping diodes, the energy in Lr is actually recirculated on the primary side of the converter and does not contribute to the secondary side commutation resonance. Therefore, the switching losses calculated in Equations (41)–(43) are reduced down to the energy calculated in Equations (44)–(46) where Eclmp stands for the conduction losses of the clamping diodes which can be estimated from their average current (Equation (45)).
E loss = V in n ( Q oss L lkg L r + Q rr ( 1 + L lkg L r ) ) + E clmp
E clmp = 2 V F , clmp I avg , clmp
P SW , SR = F SW E loss
Qrr is not constant but depends on the average forward current of the diode, the conduction time, the temperature of the device and the slope of the current among other factors [32,33]. This was taken into consideration in the complete and more accurate model where Qrr is a linear fitting function of the average current and the slope (Equation (47)). The coefficients of the relation were extracted from experimental measurements and characterization of the devices.
Q rr I a v g   a n d   Q rr di d t
Driving losses is a function of the driving voltage and the switching frequency (Equation (48)). Since the SRs are operated in ZVS, we can exclude the plateau charge (Qgd) from the driving losses. Notice that the driving voltage Vdrive is not necessarily equal to the driving voltage of the HV MOSFETs. Due to the higher gate charge of the LV MOSFETs in high current output converters, it is usually desirable to lower their driving voltage always in accordance to the device characteristics.
P drive , SR = 2 Q g V drive F SW η bias

2.2.3. Core Losses

The empirical methods based on measurement results are one major group of core losses calculations. A widely used empirical method is the Steinmetz equation (Equation (47)) [15]. The frequency of the flux variation Fcore in Equation (49) is the switching frequency Fsw for the main transformer and the resonant inductance but two times the switching frequency for the output choke 2Fsw. Vcore is the volume of the core, Bpk is the peak magnetic flux density, and k, a and b are called the Steinmetz coefficients, which are material parameters generally found empirically from the materials B–H hysteresis curves. The coefficients for the Steinmetz equations are frequently given by the magnetic core manufacturers.
P Core = V Core F Core a B pk b k
The temperature of the cores also influences the core losses, with some materials having an optimum operating temperature. The relation of core-losses to temperature is often found in the material datasheets. In the authors’ extended model, the core losses of the transformer are recalculated until the solution converges, also taking into account the transfer of heat from the windings.
The Steinmetz equation accuracy is frequently discussed. In [34] an improved core-loss calculation is proposed. However, there is currently no agreement on a better estimation method. Moreover, manufacturers frequently provide the Steinmetz coefficients or only experimental data for pure sinusoidal excitation at several flux and frequency conditions. In the authors’ extended model, the core losses are interpolated from the manufacturer’s experimental data for the main frequency component of the flux.

2.3. Other Losses

2.3.1. Control Circuitry and Fan

The control circuitry in server PSU is generally powered by an auxiliary supply. The efficiency of the auxiliary bias (a converter itself) has to be taken into account in the power consumption of the control circuitry. Moreover, an internal PSU fan is also commonly supplied from the bias. Therefore, the efficiency of the bias has to be also considered in this case (Equation (50)).
P bias = ( P ctrl + P fan ) η bias     ,   η bias [ 0 , 1 ] .
Alternatively, the fan or the control circuitry could be supplied by the main converter itself. This is especially convenient in server PSU because their output voltage is commonly equal to the control and fan supplies (12 V). Since the efficiency of the main converter is normally higher than the small auxiliary converter, this technique slightly improves the overall efficiency of the system. In contrast to the reference converter in this document, in the optimized prototype the fan is supplied by the main converter.

2.3.2. Capacitors Leakage

In addition to the previously analyzed conduction losses for the input and output capacitors there is an additional contribution from their current leakage (Equation (51)). The values of current leakage can be often found in the manufacturer’s datasheet.
P cap , leak = V in IC in , leak + V o IC o , leak

2.4. Overall Losses

The overall losses of the converter include all previously analyzed contributions that should be evaluated for each of the load points Po of interest (Equations (52) and (53)):
P cond ( P o ) = P cond , Tr ( P o ) + P cond , HV ( P o ) + P cond , SR ( P o ) + P cond , filter ( P o )
P total ( P o ) = P cond ( P o ) + P SW , p ( P o ) + P drive , p ( P o ) + P SW , SR ( P o ) + P drive , SR ( P o ) + P bias ( P o ) + P Core ( P o ) + P cap , leak ( P o )
Since the distribution of losses is load dependent, some different losses mechanisms are dominant at different load points. More interestingly, reducing the conduction losses at full load often impacts negatively on the switching and core losses at light load and vice versa. Achieving the highest efficiency at mid load is the greatest challenge, because most of the losses’ contributions have a noticeable impact in that range. Therefore, a converter with the highest efficiency at mid load will have balanced light and full load efficiencies, so-called the flat efficiency curve.

3. Design Criteria

Following the Platinum 80 PLUS requirements, the objective for the proposed design was to achieve maximum efficiency at 50% of the load of the converter while having balanced light (20%) and full load (100%) performances. The volume is constrained by the standard PSU height (1 U). Additionally, the converter should have a reasonable bill of materials (BOM) and/or production cost.
In this section we analyze the impact on the converter’s efficiency of the most influential design parameters. In the analysis, the effects of the parameters are described sequentially, in the preferred order of design, and isolated from the other parameters’ effects. However, the design process is an iterative process and normally with more than one optimal solution. Due to the complex interrelations between the parameters, the possible alternative might be constrained by previous design choices. It is therefore convenient to explore the full space of solutions.

3.1. Clamping Diodes Position

The ZVS range of the converter can be extended by adding an external resonant inductance (Lr) to the leakage of the transformer. However, the additional inductance causes loss of effective duty cycle and limits the maximum power of the converter at the minimum required input voltage [15,25]. On the other hand, the secondary side overshoot induced during the commutation of the SRs can be effectively reduced by the usage of clamping diodes between the transformer and Lr, as is suggested in [28].
When using clamping diodes on the primary side of the converter part of the energy of the resonance is recovered. During the charge of Qrr and Qoss of the secondary side rectification devices an equal energy is stored in the inductances along the charging path (Lr, Llkg). It follows that the larger Lr is in relation to Llkg, the more energy it stores comparatively. Due to the action of the primary side clamping diodes, the energy in Lr is actually recirculated on the primary side of the converter and does not contribute to the secondary side commutation resonance.
The position of the clamping diodes and the external resonant inductance Lr influences the current waveforms of the converter and on the overall efficiency of the system [28]. The clamping diodes in the leading position notably reduces the conduction losses along all the load range of the converter (Figure 6). However, the available energy for the ZVS transition of the leading leg is heavily reduced which has a major impact on the switching losses, in the reliability and the control of the converter: the non-linearity of the output capacitance of the HV super-junction MOSFETs makes it challenging to track the optimum dead time for the leading leg, which ultimately increases the switching losses.
In summary, the leading leg configuration of the clamping diodes is not recommended. In the new optimized design, the clamping diodes have been placed in the lagging leg position, as in Figure 1, whereas in the reference design the diodes were placed in the leading leg position.

3.2. Rectification Stage Configuration

Figure 7 shows a comparison between full bridge rectification and center tapped rectification configurations in low voltage server applications. Twice as many switches are required in full bridge configuration to achieve an equivalent RDS(on) because the current passes always through two devices along the rectification path. Although the figure of merit (FOM) of the lower voltage class MOSFETs is better, it is not near twice as better. Therefore, overall the switching and driving losses increase in the full bridge configuration. Moreover, the high number of rectification devices is not practical from power density and cost point of view.

3.3. Transformer Turns Ratio Selection

In the PSFB converter, like in other isolated topologies, the blocking voltage of the secondary side devices depends on the rectification stage configuration. However, unlike other resonant topologies, the secondary reflected voltage of the transformer does not depend on the output voltage Vo and it is always necessarily higher than it. The reflected voltage is proportional to the transformer turns ratio and the input voltage, as expressed in Equation (54) where VE and VD represent the amplitude of the output voltage of the rectification stage, and NP and NS represent the primary and secondary turns of the main transformer, respectively.
V E , max = V D , max = V in , max N S N P = V in , max n ,     N S N P = n
In the PSFB converter the output voltage of the rectification stage is a square wave of duty cycle Deff, with the amplitude of the transformer reflecting the voltage and average value Vo (Equation (55)). Deff is necessarily less than or equal to one and, in practical converters, commonly much smaller, as the transformer turns ratio n is constrained by the input and output voltage range requirements: the converter should be capable of regulation at the minimum specified input voltage Vin,min and maximum specified output voltage Vo,max.
V o = V in D eff n = V D D eff = V E D eff
Wide input voltage is required, for example, during hold-up time conditions [8,10,35]. The power supply needs to maintain its output voltage during a time period of 20 ms (Thold) after the input AC line is lost. The resulting minimum input voltage at the end of Thold depends on the power supply intermediate storage capacity Cbulk, the nominal operating voltage, the maximum power of the DC-DC converter Po,max and its efficiency ηDCDC (Equation (56)). A simple solution to hold-up is to increase the amount of intermediate storage, however this increases the cost and reduces the power density.
C bulk V in , nom 2 V in , min 2 2 = P o , max η DCDC T hold
The wide regulation requirement makes the PSFB converter not to be operated with its maximum duty in the nominal state. The turns ratio of the transformer is constrained by Vin,min and Vo,max. Additionally, because of the time it takes for the current through the transformer to reverse polarity, part of the otherwise available duty is lost (Dloss), which further constrains the maximum possible transformer turn ratio (Equations (57)–(61)). During the remaining duty, the so-called freewheeling (Dfrew), the primary current recirculates without transferring energy to the output of the converter.
D loss = 2 F sw ( L r + L lkg ) V in Δ IL r , 1
Δ IL r , 1 2 IL o , avg n ,   L o   in   CCM
D loss , max = 4 F sw ( L r + L lkg ) V in , min IL o , avg , max n
D eff + D frew + D loss = 1
D frew 0 yields V in , min ( n V o , max + 4 F sw ( L r + L lkg ) IL o , avg , max n )
On the other hand, the realizable transformer turns ratio is constrained by its mechanical construction: the available room for the windings, the wire size, and the amount of interleaving between primary and secondary windings. A planar construction reduces the transformer leakage which impacts the secondary side overshoot and consequently the required rectifier’s voltage class. The bigger transformer capacitance in planar construction does not have a big impact on the ZVS capability but does have an impact on the EMI performance. For isolated power converters, the inter-winding capacitance of the transformer is a critical coupling path for common mode (CM) noise. The (CM) noise model of PSFB converter is analyzed in detail in [36,37]. However, the capacitance can be adjusted with low dielectric constant isolation between primary and secondary windings. In both of the designs analyzed in this work the transformers have a planar or semi-planar construction:
  • In the reference design the primary winding of the transformer is made of 44 turns built in PCB and distributed in three sections and the secondary winding of the transformer is made of four times two plus two turns (center tapped) interleaved with the primary in four sections.
  • In the new design the primary winding of the transformer is made of two times twenty-one turns of Litz wire distributed in six sections and the secondary winding of the transformer is made of four times one plus one turns interleaved with the primary in eight sections.
Figure 8 shows a comparison among the reference design turns ratio (44:2:2), the new design turns ratio (21:1:1) and some possible similar variants (24:1:1 and 18:1:1). To fulfill the input wide range requirements of the converter Lr was adjusted consequently for each of the turn ratios. From the results in Figure 8 we can extract some conclusions:
  • More primary turns reduce the core losses of the transformers which helps to improve the light load efficiency. However, it also increases the conduction losses at mid and full load because of the extra winding length and the relatively reduced wire size.
  • A larger turns ratio decreases the transformer secondary side reflected voltage, which reduces the freewheeling time and circulating currents. Potentially it could also enable a lower voltage class for the secondary side devices. However, it limits the maximum possible Lr which in turn limits the ZVS range of the lagging leg. This can be noticed by the comparison among the 24:1:1 and 21:1:1 variants, where the higher ratio performs worse at light load because of the extra switching losses.
In summary, primary side turns should be as high as possible without compromising conduction losses and turns ratio high enough to fit the best possible SRs’ voltage class. Additionally, increasing the primary winding number of turns also helps to implement a bigger magnetizing inductance Lm. Increasing the magnetizing inductance helps reduce the primary side circulating currents, reduce conduction losses and improve overall efficiency (Figure 9).
On the other hand, a compromise in Lm value is required since reducing the magnetizing inductance increases the available energy for the ZVS transition of the primary side HV switches. As shown in Figure 10, this enables full ZVS for the lagging leg at very light loads.

3.4. External Resonant Inductance and Leakage.

Figure 11 shows the impact of increasing and decreasing the external resonant inductance with the reference being the nominal Lr value of the optimized prototype. The inductance is modified by changing the gap size between the ferrite cores but keeping the same amount of turns. A larger resonant inductance decreases the conduction losses because the circulating currents are effectively reduced, however the hold-up time regulation cannot be fulfilled unless the transformer turns ratio or the amount of bulk capacitance is adjusted in consequence. Additionally, a larger Lr increases ZVS energy at light load, which potentially reduces switching losses or enables a lower HV MOSFETs RDS(on).

4. Output Filter Inductor

The output filter inductor selection is constrained by the output current ripple and the maximum output voltage ripple requirements. The output current ripple can be calculated with Equation (62), which has an impact on the rms losses in the output capacitors (Equation (63)). The maximum output voltage ripple is also a function of the total amount of output capacitance and its parasitic equivalent resistance (Equations (64)–(66)). Moreover, a small value of inductance at the output makes the secondary side rectifiers operate in DCM at light loads. When operating with SRs this can introduce additional complexity and reliability issues [29].
Δ IL o T 2 ( V in n V o ) D eff L o
{ iC o ( V in n V o ) L o t Δ IL o 2 ,   t [ 0 , D eff T 2 ] iC o Δ IL o 2 V o ( t D eff T 2 ) L o ,   t [ D eff T 2 , T 2 ]
vC o , ripple = C o , E S R iC o + 0 t iC o C o dt + V o , ripple | t = 0
VC o , ripple , min = ( V o n V in ) ( 16 C o 2 C o , ESR 2 + D eff 2 T 2 ) 32 C o L o n
VC o , ripple , max = V o ( 4 C o 2 C o , ESR 2 + D eff 2 T 2 ) 8 C o L o
A side effect of the Lo value is the available energy for the ZVS transitions on the primary side of the converter. In the simplified model, not considering the effect of the clamping diodes, because Ip,lead increases and Ip,lag decreases for bigger output current ripples, the ZVS range of the lagging leg is extended for larger values of Lo. However, because of the effect of the clamping diodes in the lagging position, both Ip,lead and Ip,lag increase for larger output current ripples, and the ZVS range of the lagging leg can be further extended with smaller values of Lo (Figure 12).
In the realization of Lo a low permeability core is preferred because it maintains a more stable value of inductance along the load and the core losses are normally lower. For a given core geometry and core material the core losses and copper losses can be balanced adjusting the number of turns and the number of parallel wires. However, the available winding room in the core limits the possible combinations. In Figure 13 we compare the effect of only changing the number of turns in the output choke of the optimized prototype design: 1.88 µH corresponds to five turns of five parallel wires of the prototype; 2.70 µH corresponds to six turns and five parallel wires; 1.20 µH corresponds to four turns and five wires; and 3.68 µH to seven turns and five wires. For the estimation of losses in Figure 13 the number of wires or their diameter has not been adjusted, but the impact on the conduction losses is already visible because of the variations in winding length.

4.1. Primary Dide HV MOSFETs and Secondary Side SRs LV MOSFETs

The balance of switching losses and conduction losses for the different RDS(on) allows the balance of the efficiency curve. The possible values are limited to the available portfolio of the selected MOSFET technology. Unfortunately, there have been reports of failures of the primary HV MOSFETs during load jumps, light-load operation and start-up of the converter. The failure modes are linked to the incomplete clearance of the reverse recovery charge of the intrinsic body diode followed by the turn-on of the opposite half bridge device, the so called hard-commutation. The remaining charge creates a large current at turn-on which may cause the failure of the MOSFET. To overcome this problem the use of MOSFETs with reduced Qrr and a rugged body diode has been suggested in [38]. Therefore, the most recommendable choice for the primary side HV MOSFETs is CoolMOS™ CFD7.
The available RDS(on) also depends on the package selection (the package itself contributes to the equivalent resistance). In the optimized prototype all semiconductors are surface mount devices (SMD). The selected RDS(on) for the final design is 140 mΩ. The resulting efficiency for a few of the available RDS(on) is compared in Figure 14. Due to the large availability of ZVS energy of the converter, 115 mΩ is performing nearly better in all load ranges. The final selection of RDS(on) is a matter of cost.

4.2. Secondary Side SRs LV MOSFETs

The voltage class selection of the SRs is key for the final performance of the system. The voltage class influences heavily on the MOSFET characteristics, frequently benchmarked by their figure of merit (FOM) [39]. A summary of the characteristics of two devices with similar RDS(on) in Table 2 shows the influence of the blocking voltage in their characteristic charges and forward voltage drop, which ultimately affects the switching and conduction losses. A lower voltage class is enabled by a proper design of the transformer turns ratio, a reduction in the leakage combined with a big external resonant inductance and clamping diodes [29]. Any additional overshoot above the nominal blocking voltage would require further increasing the maximum limits of the blocking voltage capabilities of the rectification devices; or alternatively to use clamping or snubbering mechanisms that bring additional power losses, complexity and costs [22,25]. Furthermore, it is a common practice in the design of switched mode power supplies (SMPS), to limit the maximum stress on the components (voltage, current, temperature) to a rated percentage of their safe maximum limits under any normal working conditions of the converter [40]. The rating percentage depends on the application, lifetime and reliability requirements, but 80% is a common choice. For semiconductor devices the commonly rated parameters are the maximum drain voltage and the working temperature.
Figure 15 shows the impact of the selection of voltage class between the former reference design, with 80 V MOSFETs, and the selection of the optimized prototype design, with 60 V devices. The losses both at light load and full load are higher, which indicates an increase in both the switching and conduction losses that cannot be balanced by RDS(on) or paralleled devices. Like for the HV MOSFETs, the selection of the SRs RDS(on) can balance the efficiency between light and full load by modifying the distribution of switching to conduction losses.
The number of paralleled devices adds another degree of freedom, at the expense of the extra cost and PCB area. Figure 15 compares the efficiency of different numbers of rectification devices, which effectively decrease the equivalent resistance of the rectification stage.
The Si-MOSFETs have been widely used to improve power density and efficiency. However, the SiC MOSFET and the GaN HEMT are promising alternatives to achieve high efficiency and high switching frequency. The advantages of wide band gap (WBG) devices are lower parasitic capacitances, lower equivalent RDS(on), zero reverse recovery charge and higher operating temperature capabilities. In [41] the efficiency of 2 kW PSFB designs based on Si and SiC MOSFETs is measured and compared. In [21] the efficiency improvement in a 500 W PSFB converter with GaN HEMT SRs is verified experimentally.

4.3. Input and Output Capacitance

The previous analysis demonstrates the influence of the input and output capacitances in the hold-up time operation and the output voltage ripple. However, the capacitors occupy a large volume and are costly, which will ultimately constraint their selection. Although the leakage current of the capacitors adds some losses, these losses are relatively small and in general can be dismissed.

4.4. Switching Frequency Selection. Balance of Losses

The switching frequency is a key parameter to be optimized for the converter. A specific frequency achieves its maximum efficiency only under a given set of operating conditions. In [15] a variable switching frequency control method has been adopted in a PSFB DC-DC converter to improve the efficiency. This method implies wide variations in switching frequency, which makes it difficult to design, filter and control circuits, so these techniques are hard to implement in the PSFB converter.
For the two designs in this document the switching frequency was selected to be in the range of 100 kHz and all the other design variables chosen consequently. The transformer construction and the magnetics volume have the major impact in the resulting range of optimum switching frequencies for the converter, and/or vice versa. Figure 16 plots the efficiency patterns of the optimized prototype for different switching frequencies. For the point of load of interest (50%) the estimated peak efficiency is reached around the target switching frequency.
Figure 16 compares the overall system efficiency along the load range only modifying the switching frequency in the optimized prototype design, which was designed for peak efficiency at 50% of the load at 100 kHz Fsw. In the estimation of efficiencies Lr was also modified to account for the different freewheeling times available when the switching frequency changes. As depicted on Figure 17 the efficiency at 100% of the load peaks at 90 kHz Fsw, like previously reported in Figure 16.

4.5. Thermal Management.

Although the fan consumption is normally not taken into account while measuring efficiency for the 80 PLUS certification, the temperature of the converter has a major impact on the performance. Most of the losses contributions have a positive coefficient in relation to the temperature: the RDS(on) of MOSFETs increases with temperature, as does the resistance of the metallic conductors. However, some of the losses have a negative temperature coefficient: the forward voltage drop of diodes decreases with temperature; and the core losses of some magnetic materials has a minimum at a relatively high temperature. Controlling the temperature, or the fan speed, could impact notably the efficiency along the load ranges.

4.6. Input and Output Voltage

Whereas the output voltage depends on the application and it is usually fixed to a certain value, the nominal input voltage can be adjusted taking into account the previously discussed hold-up time requirements. Moreover, other system restrictions apply: the bulk voltage has to be higher than the maximum VAC peak voltage for the PFC functionality to work (the front end is most commonly a boost converter). For the PSFB DC-DC converter the efficiency is higher for lower input voltages mostly because of the reduction in switching, core losses and magnetizing currents. For the results in Figure 18 and Figure 19 the converter design was fixed only varying the input voltage operating point and the output voltage operating point, consequently the freewheeling time and the circulating currents are also reduced.
Increasing the output voltage operation point has a similar effect to reducing the input voltage, freewheeling time and the circulating currents. However, this is usually fixed by the application requirements. In the intended application, in server power supplies are typically 12 V.

5. Comparison of Two PSFB Converter Designs

In this section two different designs of DC-DC PSFB converters for server applications are compared. Both converters have a maximum power of 1.4 kW, the same input voltage range, nominal input voltage 400 V and 12 V output voltage. The first design serves as a reference with state-of-the-art performance levels. The second converter has been designed with the provided loss model and design criteria. The new design improves the performance of the reference design in all working conditions while also achieving a higher power density.

5.1. Summary of Specifications

For a fair comparison, both converters have the same basic requirements, summarized in Table 3, targeting the front-end DC-DC converter of a full PSU for server applications. The nominal operating voltage is 400 V, while the converters should be capable of regulation at full load down to 360 V required during hold-up time. The nominal output voltage is 12 V. During dynamic load jumps the overshoot and undershoot should fall within less than ±5% of the nominal output voltage. The load jumps are defined from 5% to 50% of the load and from 50% of the load up to 100% of the load with a di/dt of 1 A/µs.

5.2. Summary of Design Data

Both designs use the same HV MOSFETs technology, 600 V CoolMOS™ CFD7 from Infineon Technologies AG. The reference design mounts through-hole devices, which are capable of higher power dissipation. The optimized design mounts all semiconductor switches in the SMD. Although the power dissipation could be more challenging, an SMD solution easily achieves a higher power density with less building complexity. In the new design the RDS(on) of the HV MOSFETs is slightly reduced (Table 4 and Table 5) taking advantage of the higher amount of energy available for the ZVS transitions at light loads.
The voltage class of the secondary side rectifier MOSFETs has been improved from 80 V in the reference design down to 60 V in the new optimized design. The improved transformer construction (less leakage), improved PCB layout, bigger value of external resonant inductance together with novel control techniques ensure that the drain voltage overshoot remains well within the rated limits in all working conditions of the new converter. The better figure of merit of the 60 V technology enables the usage of lower RDS(on) and a higher number of devices without sacrificing light or medium load efficiency thanks to the comparative reduction in switching and driving losses.
The transformer turns ratio is very similar in both cases (44:2:2) and (21:1:1). The higher number of primary turns of the reference design reduces notably the core losses at light and medium loads, furthermore aided by the smaller core volume (Table 6 and Table 7). However, the high number of turns and the smaller room for the windings penalize heavily on the conduction losses at full load. The new design has a more balanced relation between core and conduction losses among light, medium and full loads. Moreover, the novel mechanical construction improves the coupling and reduces the leakage without excessive impact on the intra-winding and inter-winding capacitances thanks to the usage of an isolation with low dielectric constant.
The nominal magnetizing inductance is equal in both designs, aiming to reduce the circulating currents. The external resonant inductance, however, is twice as big in the optimized design, which extends the full ZVS range for the lagging leg down to almost no load, whereas in the former reference design the lagging leg is partially hard switched up to near full load (further exacerbated by the clamping diodes position).
In the new design the output inductance value has been reduced using a core with lower permeability material but improved core losses (Table 8 and Table 9). The balance of core losses to conduction losses is also improved reducing the number of turns and increasing the wire diameter. Furthermore, the smaller output inductance provides additional energy for the lagging leg ZVS, as previously analyzed.
The stacked magnetic structure integrated by the transformer and the external resonant inductance has a bigger core volume in the new design, which incurs in higher core losses and impacts in the light and medium load converter losses. On the other hand, there is more room for the windings which enables a larger conduction area and decreases the conduction losses at medium and full load.

6. Results

Two prototypes of PSFB converters, one of the reference design [42] and one of the new optimized design [43], were built and tested to compare their performance. Figure 20 shows a capture of both converters. While the reference design operates with an open frame, the new design operates within an enclosure, not shown in Figure 20 for clarity. Many of the building components among the two converters are the same and have no impact on the difference in performance: input capacitor (size and model), output capacitors (size and model, but not number), fan, auxiliary bias supply and controller. The overall dimensions of the reference designs are 150 mm × 70 mm × 44 mm, which results in a power density in the range of 3.03 W/cm3 (49.66 W/in3). The overall dimensions of the new design are 133 mm × 64.5 mm × 44 mm, which results in a power density in the range of 3.70 W/cm3 (60.78 W/in3).

6.1. Summary of Performance

Figure 21 shows the measure efficiency of the reference and the new design. The efficiency was notably improved in all load ranges. Table 10 is a summary of the requirements for the back-end PFC AC-DC converter, which may accompany the new PSFB design in a full PSU achieving one of the 80 PLUS certification levels (Table 1). This demonstrates the impact of the efficiency of the front-end DC-DC stage in the final efficiency of the system and/or the imposed constraints on the back-end stage by a poorly designed DC-DC. The efficiency levels for the AC-DC PFC stage listed in Table 10 for the 80 PLUS Platinum can be achieved with a classic continuous conduction mode (CCM) boost converter with passive diode bridge rectification. This confirms the suitability of the design for an 80 PLUS Platinum server PSU. However, the required PFC efficiency levels for the 80 PLUS Titanium listed in Table 10 are beyond the levels commonly achieved with classic topologies.
The calculated efficiency was based on the losses model presented previously in this document which was further adjusted based on the measurements of efficiency and temperature of the different components in the converter. The losses model and its adjustment based on the measurements of the real hardware allows for estimation of the losses’ distribution of the two converters for the different load points. The estimated distribution of losses is summarized in Figure 22. From the estimations, in both designs the main losses contribution corresponds to the stacked magnetic structure integrated by the transformer and the external resonant inductance. Table 11 and Table 12 details the previous Figure 22 numerically.
At full load, the difference in losses between the reference design and the new design is near 25 W. The extra losses make it much more difficult to cool down the converter. This is confirmed by the position of the fan in the reference design, directly blowing over the integrated magnetic structure and the SRs.
Table 13 details the difference between the component losses of the reference design and the improved design. Although in some of the losses contribution the losses actually have increased, the overall result is a general improvement in all points of the load. In Table 13 it can be observed that the main improvements come from the transformer conduction and the SRs (conduction and switching), the output inductor (conduction and core), Lr conduction, the fan and the HV bridge (conduction and switching).

6.2. Waveforms Reference Design

The steady state operation of the reference design was tested and summarized in the captures in this section.
The different energy available for the ZVS transitions of the leading and the lagging leg of the primary side bridge was already analyzed in the previous sections. Figure 23 shows captures of the leading leg drain and gate voltages at different loads. Whereas Figure 24 shows captures of the lagging leg drain and gate voltage also operating at different loads.
The leading leg operates in full ZVS in all load ranges of the converter, which can be observed in the gate voltages in Figure 23, where the drain voltage is zero prior to the gate voltage rising and no Miller plateau can be observed. The full bridge is driven with an isolated pulse transformer which outputs ±Vdrive. Only during the dead time is the gate voltage zero. Certain Cgd feedback can be observed at higher loads where the dv/dt of the VDS transition increases because of the higher starting currents involved in the resonant transition.
The lagging leg achieves full ZVS only at full load (Figure 24). The main reasons for the lack of energy for the ZVS transitions are the small external resonant inductance and the position of the clamping diodes. The reference design mounts the clamping diodes in the leading leg. The clamping diodes in the leading leg reduces circulating currents and conduction losses all along the load range of the converter. However, it also reduces the current through Lr at the end of the freewheeling stage, which directly impacts the energy available for ZVS.
The lack of energy for the ZVS transitions of the leading leg increases the switching losses. Moreover, because of the non-linearity of the output capacitance of super-junction MOSFETs, the optimum dead time varies non-linearly with the load. The non-linear variation of the dead times makes it difficult to optimize the control with may further increase the switching losses. This is further aggravated by the variation of capacitances and inductances between the components in different converters.
Moreover, the fast dv/dt induced by the partial hard switching of the leading leg impacts on the secondary side overshoot at light loads. It can be observed in Figure 25 how the overshoot of the SRs is higher at the light load in the former converter, exceeding the 80% rating of the 80 V breakdown limit.
These results corroborate the drawbacks of the clamping diodes on the leading leg position and support the recommendation of placing them in the lagging leg instead.
Figure 26 shows in more detail the secondary side overshoot of the SRs in steady state and the effect on the primary side current of the clamping diodes on the leading leg position.

6.3. Waveforms of New Optimized Design

The leading leg of the new design achieves full ZVS above 20% of the load (Figure 27). Moreover, it achieves nearly full ZVS down to no load. The lagging leg, like in the reference design, also achieves full ZVS along all load ranges. However, the Cgd feedback effects on the gate voltage at full load are less noticeable thanks to the improved layout and driving scheme.
The overshoot on the secondary side rectifiers is very much improved in the all load range, and well within the 80% rated limit of the 60 V breakdown voltage (Figure 28).
Near no load, both the reference design and the optimized design, implement burst mode operation. The burst mode operation enables soft switching at no load operation. Figure 29 shows captures of the drain voltage overshoot on the primary side devices and the secondary side devices of the optimized converter. Also, in burst mode operation the drain and gate voltages remain well within their rated limits.
Load jumps are usually considered critic for the PSFB topology. Figure 30 shows a capture of dynamic load jumps where the reader can observe that the drain voltage of the primary and secondary switches is well within the limits.

7. Conclusions

Since the server power supplies consume an enormous amount of power, the most critical issue is high efficiency. In order to implement a high efficiency and high power density server PSU, a PSFB converter with SRs MOSFETs, external resonant inductor and clamping diodes is the perfect topology for the DC-DC stage. Its main characteristic is the wide ZVS operation from mid to full load, nearly suppressing switching losses. Moreover, the constant switching frequency allows a simple control and EMI design. One of the major advantages of PSFB over other resonant soft-switching topologies is the comparatively lower rms currents through the converter thanks to the output filter inductance. However, hold-up time regulation requirements make PSFB converter not to be operated with its maximum effective duty in nominal conditions and causes a long freewheeling period.
The design of a high efficiency PSFB converter is a complex problem with many degrees of freedom which requires a sufficiently accurate modeling of the losses of the converter and of efficient design criteria. In this work a losses model of the converter has been proposed as well as design guidelines for the efficiency optimization of the PSFB converter. The losses model and the criteria have been tested with the redesign of an existing reference PSFB DC-DC converter for server applications that achieved 95.85% of efficiency at 50% of the load. The new converter was designed following the same specifications as the reference: 1400 W of maximum power; 400 V nominal input voltage; hold-up regulation down to 360 V input voltage; and 12 V output. The new optimized prototype of the PSFB converter was built and tested achieving a peak efficiency of 96.68% at 50% of the load, notably exceeding the performance of the reference converter in all load ranges and operating conditions.
The main differences between both designs are related to the magnetics construction, with an improved balance of core and conduction losses along the load range of the converter. Furthermore, the transformer turns ratio and the dimensioning of the external resonant inductance enabled lower RDS(on) in the primary side HV devices and lower voltage class (and consequently also lower RDS(on)) in the secondary side LV devices. Moreover, all semiconductors in the new optimized design are SMD, which together with the high efficiency at full load enables a power density in the range of 3.70 W/cm3 (60.78 W/in3).
In summary, the key of an efficient and reliable DC-DC PSFB converter in this power range and output voltage is in the magnetics design, more specifically the transformer and the external resonant inductance. This demonstrates that the PSFB converter is a relatively simple and efficient topology for DC-DC converter applications at the level of fully resonant topologies.

Author Contributions

Conceptualization, M.E., M.-A.K. and D.M.; supervision, N.R. and D.P.M.; validation, M.E.; writing—original draft, M.E.; writing—review, discussion and editing, M.-A.K., D.M., N.R. and D.P.M.

Funding

This research was financed by Infineon Technologies AG.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Phase shift full bridge (PSFB) converter with center tapped rectification stage, external resonant inductance and clamping diodes.
Figure 1. Phase shift full bridge (PSFB) converter with center tapped rectification stage, external resonant inductance and clamping diodes.
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Figure 2. Primary side current and PWM control signals of a simplified model of a PSFB converter.
Figure 2. Primary side current and PWM control signals of a simplified model of a PSFB converter.
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Figure 3. Primary side HV MOSFETs current and PWM control signals of a simplified model of a PSFB converter.
Figure 3. Primary side HV MOSFETs current and PWM control signals of a simplified model of a PSFB converter.
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Figure 4. Secondary side LV MOSFETs current and PWM control signals of a simplified model of a PSFB converter.
Figure 4. Secondary side LV MOSFETs current and PWM control signals of a simplified model of a PSFB converter.
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Figure 5. Input capacitor, output choke and output capacitor currents of a simplified model of a PSFB converter.
Figure 5. Input capacitor, output choke and output capacitor currents of a simplified model of a PSFB converter.
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Figure 6. Efficiency for different clamping diodes’ configuration and the effect on switching voltage of the primary side HV MOSFETs and the primary side circulating currents: (a) differential efficiencies; (b) differential losses; (c) leading and lagging leg switching voltages with the clamping diodes on the lagging leg position; (d) leading and lagging leg switching voltages with the clamping diodes on the leading leg position; (e) primary side and clamping diodes current with clamping diodes in the lagging leg; (f) primary side and clamping diodes current with clamping diodes in the leading leg.
Figure 6. Efficiency for different clamping diodes’ configuration and the effect on switching voltage of the primary side HV MOSFETs and the primary side circulating currents: (a) differential efficiencies; (b) differential losses; (c) leading and lagging leg switching voltages with the clamping diodes on the lagging leg position; (d) leading and lagging leg switching voltages with the clamping diodes on the leading leg position; (e) primary side and clamping diodes current with clamping diodes in the lagging leg; (f) primary side and clamping diodes current with clamping diodes in the leading leg.
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Figure 7. Performance comparison for different rectification stage configuration of equivalent RDS(on). Full bridge rectification with 24 units of 40 V class devices in blue, and the center tapped with 12 units of 60 V class devices in red. (a) Differential efficiency; (b) differential losses.
Figure 7. Performance comparison for different rectification stage configuration of equivalent RDS(on). Full bridge rectification with 24 units of 40 V class devices in blue, and the center tapped with 12 units of 60 V class devices in red. (a) Differential efficiency; (b) differential losses.
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Figure 8. Performance comparison for different transformer turns ratios. The value of Lr is adjusted to maintain the required input voltage range. The original reference converter had a turn ratio of 44:2:2. The optimized converter has a turn ratio of 21:1:1. (a) Differential efficiency of the converter with the different configurations; (b) differential power loss of the converter with the different configurations.
Figure 8. Performance comparison for different transformer turns ratios. The value of Lr is adjusted to maintain the required input voltage range. The original reference converter had a turn ratio of 44:2:2. The optimized converter has a turn ratio of 21:1:1. (a) Differential efficiency of the converter with the different configurations; (b) differential power loss of the converter with the different configurations.
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Figure 9. Performance comparison for different magnetizing inductances: (a) differential efficiency; (b) differential losses.
Figure 9. Performance comparison for different magnetizing inductances: (a) differential efficiency; (b) differential losses.
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Figure 10. Available energy for the zero-voltage-switiching (ZVS) transitions depending on the value of the magnetizing inductance with the converter operating at 10% of the load.
Figure 10. Available energy for the zero-voltage-switiching (ZVS) transitions depending on the value of the magnetizing inductance with the converter operating at 10% of the load.
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Figure 11. Performance comparison for different external resonant inductances: (a) differential efficiency; (b) differential losses.
Figure 11. Performance comparison for different external resonant inductances: (a) differential efficiency; (b) differential losses.
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Figure 12. Available energy for the ZVS transitions depending on the value of the output inductor Lo at 10% of the load. (a) Simplified model without clamping diodes; (b) with primary side clamping diodes in the lagging leg.
Figure 12. Available energy for the ZVS transitions depending on the value of the output inductor Lo at 10% of the load. (a) Simplified model without clamping diodes; (b) with primary side clamping diodes in the lagging leg.
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Figure 13. Performance comparison for different numbers of turns of the output inductor: (a) differential efficiency; (b) differential losses.
Figure 13. Performance comparison for different numbers of turns of the output inductor: (a) differential efficiency; (b) differential losses.
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Figure 14. Efficiency for different HV MOSFETs RDS(on): (a) differential efficiencies; (b) differential losses.
Figure 14. Efficiency for different HV MOSFETs RDS(on): (a) differential efficiencies; (b) differential losses.
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Figure 15. Efficiency for different LV MOSFETs voltage class and number of devices: (a) differential efficiencies; (b) differential losses.
Figure 15. Efficiency for different LV MOSFETs voltage class and number of devices: (a) differential efficiencies; (b) differential losses.
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Figure 16. Efficiency plot of the system as a function of the switching frequency. Not including fan. Keeping the wide input design maintaining a minimum freewheeling time (Lr is updated for each frequency in consequence).
Figure 16. Efficiency plot of the system as a function of the switching frequency. Not including fan. Keeping the wide input design maintaining a minimum freewheeling time (Lr is updated for each frequency in consequence).
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Figure 17. Performance comparison for different switching frequencies: (a) differential efficiencies; (b) differential losses.
Figure 17. Performance comparison for different switching frequencies: (a) differential efficiencies; (b) differential losses.
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Figure 18. Performance comparison for different nominal input voltages: (a) differential efficiency; (b) differential losses.
Figure 18. Performance comparison for different nominal input voltages: (a) differential efficiency; (b) differential losses.
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Figure 19. Performance comparison for different nominal output voltages: (a) differential efficiency; (b) differential losses.
Figure 19. Performance comparison for different nominal output voltages: (a) differential efficiency; (b) differential losses.
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Figure 20. Prototypes of PSFB DC-DC converter for server applications: (a) original reference design; (b) optimized design.
Figure 20. Prototypes of PSFB DC-DC converter for server applications: (a) original reference design; (b) optimized design.
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Figure 21. Overall efficiency of the converters, including fan consumption. (a) Original reference design. (b) New optimized design.
Figure 21. Overall efficiency of the converters, including fan consumption. (a) Original reference design. (b) New optimized design.
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Figure 22. Overall estimation of losses based on the loss model and the experimental results. (a) Reference design. (b) Optimized design.
Figure 22. Overall estimation of losses based on the loss model and the experimental results. (a) Reference design. (b) Optimized design.
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Figure 23. Turn on switching waveforms of the low side switch of the leading leg at different loads (Io,avg). (a) 25 A; (b) 60 A; (c) 75 A; (d) 117 A.
Figure 23. Turn on switching waveforms of the low side switch of the leading leg at different loads (Io,avg). (a) 25 A; (b) 60 A; (c) 75 A; (d) 117 A.
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Figure 24. Turn on switching waveforms of the low side switch of the lagging leg at different loads (Io,avg). (a) 25 A of load; (b) 60 A of load; (c) 75 A of load; (d) 117 A of load (100%).
Figure 24. Turn on switching waveforms of the low side switch of the lagging leg at different loads (Io,avg). (a) 25 A of load; (b) 60 A of load; (c) 75 A of load; (d) 117 A of load (100%).
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Figure 25. SRs drain voltage overshoot: (a) Working at 140 W of output power (10% of load); (b) working at 1400 W of output power (full load).
Figure 25. SRs drain voltage overshoot: (a) Working at 140 W of output power (10% of load); (b) working at 1400 W of output power (full load).
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Figure 26. Detail on the SRs overshoot and the primary side current with the clamping diodes on the leading leg position.
Figure 26. Detail on the SRs overshoot and the primary side current with the clamping diodes on the leading leg position.
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Figure 27. Primary side HV MOSFETs ZVS: (a) ZVS at 20 A of load; (b) ZVS at full load.
Figure 27. Primary side HV MOSFETs ZVS: (a) ZVS at 20 A of load; (b) ZVS at full load.
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Figure 28. SRs drain voltage overshoot: (a) Working at 140 W of output power (10% of load); (b) working at 1400 W of output power (full load).
Figure 28. SRs drain voltage overshoot: (a) Working at 140 W of output power (10% of load); (b) working at 1400 W of output power (full load).
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Figure 29. SRs and HV bridge MOSFETs overshoot during burst: (a) SRs drain voltage overshoot; (b) HV bridge overshoot.
Figure 29. SRs and HV bridge MOSFETs overshoot during burst: (a) SRs drain voltage overshoot; (b) HV bridge overshoot.
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Figure 30. SRs overshoot during load jump.
Figure 30. SRs overshoot during load jump.
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Table 1. Summary of efficiency requirements of 80 PLUS certification for redundant power supplies.
Table 1. Summary of efficiency requirements of 80 PLUS certification for redundant power supplies.
80 PLUS Certification230 V Internal Redundant (Complete Power Supply Unit (PSU))
% of Rated Load10%20%50%100%
80 PLUS Bronze-81%85%81%
80 PLUS Silver-85%89%85%
80 PLUS Gold-88%92%88%
80 PLUS Platinum-90%94%91%
80 PLUS Titanium90%94%96%91%
Table 2. Si LV MOSFETs.
Table 2. Si LV MOSFETs.
ParameterBSC026N80NS5BSC027N60LS5
VDS,max80 V60 V
RDS(on),max2.6 mΩ at 25 °C2.7 mΩ at 25 °C
Qoss88 nC43 nC
Qrr92 nC36 nC
Table 3. Summary of converter design specifications.
Table 3. Summary of converter design specifications.
ParameterMinimumNominalMaximum
Vin360400415
Vout11.51212.5
Iout0-117
Table 4. Primary side HV MOSFETs and synchronous rectifiers (SRs) MOSFETs in reference design.
Table 4. Primary side HV MOSFETs and synchronous rectifiers (SRs) MOSFETs in reference design.
DesignatorPart NumberUnitsV(BR)DSSRDS (on)
Bridge (Q1–Q4)IPP60R170CFD74600 V170 mΩ
SR (Q5–Q6)BSC026N80NS5880 V2.6 mΩ
Table 5. Primary side HV MOSFETs and SRs MOSFETs in optimized design.
Table 5. Primary side HV MOSFETs and SRs MOSFETs in optimized design.
DesignatorPart NumberUnitsV(BR)DSSRDS (on)
Bridge (Q1–Q4)IPL60R140CFD74600 V140 mΩ
SR (Q5–Q6)BSC016N60NS51260 V1.6 mΩ
Table 6. Inductance values and their winding realization in reference design.
Table 6. Inductance values and their winding realization in reference design.
DesignatorInductanceTurnsWindingsStrandsDiameter
Lm1.2 mH44110.35 mm
Lr12 µH611050.071 mm
Lo5.65 µH6511.25 mm
Table 7. Inductance values and their winding realization in optimized design.
Table 7. Inductance values and their winding realization in optimized design.
DesignatorInductanceTurnsWindingsStrandsDiameter
Lm1.2 mH21270.3 mm
Lr29.5 µH811400.1 mm
Lo1.88 µH5511.45 mm
Table 8. Magnetic core selection in reference design.
Table 8. Magnetic core selection in reference design.
DesignatorPart NumberManufacturerMaterialPermeability
Tr. CoreEQ30TDGTP4A2400 µ
Lr. CoreEQ30TDGTP4A2400 µ
Lo. CoreC058930A2MagneticsHigh Flux125 µ
Table 9. Magnetic core selection in optimized design.
Table 9. Magnetic core selection in optimized design.
DesignatorPart NumberManufacturerMaterialPermeability
Tr. CorePQ35/28DMEGCDMR953300 µ
Lr. CorePQI35/23DMEGCDMR953300 µ
Lo. CoreHP 270Chang SungHP60 µ
Table 10. Summary of efficiency requirements for back-end power factor correction (PFC) AC-DC stage.
Table 10. Summary of efficiency requirements for back-end power factor correction (PFC) AC-DC stage.
80 PLUS Certification230 V Internal Redundant (PFC AC-DC stage)
% of Rated Load10%20%50%100%
80 PLUS Bronze-84.5%87.7%84.6%
80 PLUS Silver-88.7%91.9%88.8%
80 PLUS Gold-91.8%95.0%91.9%
80 PLUS Platinum-93.9%97.0%95.1%
80 PLUS Titanium96.9%98.1%99.1%95.1%
Table 11. Summary of the distribution of losses in the reference design.
Table 11. Summary of the distribution of losses in the reference design.
Contribution100% Load50% Load20% Load
Bias0.96 W0.96 W0.96 W
Fan3.45 W3.45 W3.45 W
Tr. Core0.53 W1.28 W1.59 W
Tr. Conduction29.98 W6.53 W1.07 W
Lr Core0.18 W0.08 W0.02 W
Lr Conduction1.20 W0.26 W0.04 W
Lo Core0.58 W0.58 W0.58 W
Lo Conduction9.65 W2.17 W0.33 W
Bridge Conduction11.24 W2.29 W0.33 W
Bridge Switching0.42 W0.42 W1.29 W
Bridge Driving0.18 W0.18 W0.18 W
SRs Conduction10.29 W2.63 W0.48 W
SRs Switching4.33 W3.70 W3.35 W
SRs Driving0.89 W0.89 W0.89 W
Clamping Diodes0.9 W1.30 W1.50 W
Capacitors3.28 W1.13 W0.53 W
PCB10.32 W2.58 W0.41 W
Total88.38 W30.43 W17.00 W
Table 12. Summary of the distribution of losses in the optimized design.
Table 12. Summary of the distribution of losses in the optimized design.
Contribution100% Load50% Load20% Load
Bias0.96 W0.96 W0.96 W
Fan3.45 W1.55 W0.60 W
Tr. Core2.37 W2.37 W2.37 W
Tr. Conduction13.04 W3.61 W0.96 W
Lr Core0.30 W0.15 W0.05 W
Lr Conduction0.64 W0.17 W0.04 W
Lo Core0.39 W0.39 W0.39 W
Lo Conduction6.18 W1.43 W0.23 W
Bridge Conduction10.05 W2.51 W0.53 W
Bridge Switching0.49 W0.42 W0.42 W
Bridge Driving0.22 W0.22 W0.22 W
SRs Conduction5.19 W1.28 W0.25 W
SRs Switching3.26 W2.10 W1.40 W
SRs Driving1.17 W1.17 W1.17 W
Clamping Diodes1.47 W1.67 W1.77 W
Capacitors3.65 W1.25 W0.58 W
PCB12.33 W3.09 W0.50 W
Total65.16 W24.34 W12.44 W
Table 13. Summary of difference of losses between the optimized and the reference designs.
Table 13. Summary of difference of losses between the optimized and the reference designs.
Contribution100% Load Difference50% Load Difference20% Load Difference
Bias0 W0 W0 W
Fan0 W−1.9 W−2.85 W
Tr. Core1.84 W1.09 W0.78 W
Tr. Conduction−16.94 W−2.92 W−0.11 W
Lr Core0.12 W0.07 W0.03 W
Lr Conduction−0.56 W−0.09 W0 W
Lo Core−0.19 W−0.19 W−0.19 W
Lo Conduction−3.47 W−0.74 W−0.1 W
Bridge Conduction−1.19 W0.22 W0.2 W
Bridge Switching0.07 W0 W−0.87 W
Bridge Driving0.04 W0.04 W0.04 W
SRs Conduction−5.1 W−1.35 W−0.23 W
SRs Switching−1.07 W−1.6 W−1.95 W
SRs Driving0.28 W0.28 W0.28 W
Clamping Diodes0.57 W0.37 W0.27 W
Capacitors0.37 W0.12 W0.05 W
PCB2.01 W0.51 W0.09 W
Total−23.22 W−6.09 W−4.56 W

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Escudero, M.; Kutschak, M.-A.; Meneses, D.; Rodriguez, N.; Morales, D.P. A Practical Approach to the Design of a Highly Efficient PSFB DC-DC Converter for Server Applications. Energies 2019, 12, 3723. https://doi.org/10.3390/en12193723

AMA Style

Escudero M, Kutschak M-A, Meneses D, Rodriguez N, Morales DP. A Practical Approach to the Design of a Highly Efficient PSFB DC-DC Converter for Server Applications. Energies. 2019; 12(19):3723. https://doi.org/10.3390/en12193723

Chicago/Turabian Style

Escudero, Manuel, Matteo-Alessandro Kutschak, David Meneses, Noel Rodriguez, and Diego P. Morales. 2019. "A Practical Approach to the Design of a Highly Efficient PSFB DC-DC Converter for Server Applications" Energies 12, no. 19: 3723. https://doi.org/10.3390/en12193723

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