## 2. Proposed Converter

The basic circuit structure of a DC microgrid is given in

Figure 1. The bidirectional AC/DC converters are used between the AC utility system and the DC microgrid to stabilize the DC bus voltage. Renewable energy sources from solar cell panels and wind power generators provide clear energy to the DC microgrid system through the unidirectional DC/DC converters and the AC/DC converters. Energy storage units are used to store/release energy from/to the DC microgrid through the bidirectional DC/DC converters in order to stabilize the DC bus voltage. In order to increase the voltage reliability, the bipolar voltage system (+

V_{dc}, −

V_{dc} and neutral line) can be adopted on the DC microgrid. When a fault condition in one of the DC poles occurs, the DC power is still suppled to the local load by the other two wires and an auxiliary converter. It is clear that the reliability of the DC mircogrid system is increased during fault condition. Therefore, three voltage levels (2

V_{dc}, +

V_{dc} and −

V_{dc}) can be used to provide industry and transportation with the 2

V_{dc} voltage level and future residential and commercial buildings with the +

V_{dc} or −

V_{dc} voltage level. To keep two voltage levels (+

V_{dc} and −

V_{dc}) balanced during unbalanced loads, a voltage balancing circuit is normally needed to realize this goal. The DC/DC converter can be used to convert a high input voltage to a low output voltage and it does not relate to the bipolar voltage system. For a DC light rail vehicle, the input voltage is normally around 760 V. Power devices such as the 1500 V IGBT can be adopted in two-level power converters to supply auxiliary low voltage power for control units, telecommunication units and lighting systems in the light rail vehicle. The MOSFETs with a 600 V rating can be adopted in the three-level power converter to achieve the same goal but with a much higher switching frequency to reduce converter size. The studied converter is concentrated on power conversion for light rail vehicle applications.

Figure 2a shows the basic block diagrams of power distribution in a conventional light rail vehicle. First, 750

V_{dc} is converted to the three-phase AC voltage 380

V_{ac} by the DC/AC inverter. Second, the AC/DC converter is adopted to convert 380

V_{ac} to a low DC voltage in an auxiliary power distribution system to supply a necessary amount of DC voltage for the battery bank, lighting equipment, door equipment, control power units and communication equipment in a light rail vehicle system. The AC/DC/AC converter is also adopted to convert 380

V_{ac} to a variable AC voltage output for the AC motor drive. If the power of the DC light rail vehicle is supplied directly from the DC microgrid, then some power conversion stages can be saved to reduce costs and increase circuit efficiency. The basic power distribution diagrams in the proposed light rail vehicle are illustrated in

Figure 2b. The auxiliary power in a light rail vehicle is directly converted from 760 V through a DC/DC converter. The AC motor drive and the air compressor are controlled by the DC/AC converters. Therefore, the AC/DC conversion can be saved to reduce costs and increase circuit efficiency and reliability.

The studied DC/DC converter is given in

Figure 3. It directly converts a 760 V voltage input from the DC microgrid to a low voltage output by using low voltage rating power MOSFETs to provide auxiliary power in a light rail vehicle. The studied converter includes three HB circuits connected in a primary-series secondary-parallel with a single transformer. The primary sides of the HB circuits are connected in a series so that the voltage stress of the power switches

Q_{1}~

Q_{6} is reduced to

V_{in}/3 and the low turn-on resistance of power MOSFETs is adopted to reduce conduction losses and increase circuit efficiency. Each HB circuit provides

P_{o}/3 to the output load. Flying capacitors are widely used in a multilevel inverter to reduce voltage stress and balance input split voltages. Thus, two flying capacitors

C_{f}_{1} and

C_{f}_{2} are used on the high voltage side to achieve an input voltage balance of

V_{C}_{1}~

V_{C}_{3}. The current doubler rectifier is used on the low voltage side to reduce the output ripple current. The driving signals of each HB circuit use asymmetric pulse-width modulation. Due to the resonant behavior between the output capacitor of the power MOSFETs and the primary leakage inductor at switch on/off instant, the power MOSFETs can be turned on at zero-voltage switching to reduce the switching loss.

Figure 4 shows the timing sequence of switches

Q_{1}~

Q_{6} and the main PWM waveforms in the proposed converter. The operation principle and circuit analysis of the studied circuit are assumed under the following conditions: (1) the output capacitor

C_{o} is large enough to be treated as a constant voltage

V_{o}, (2) power devices

Q_{1}~

Q_{6},

D_{1} and

D_{2} are ideal, (3)

C_{f}_{1} =

C_{f}_{2} =

C_{f},

C_{b}_{1} =

C_{b}_{2} =

C_{b}_{3} =

C_{b},

L_{r}_{1} =

L_{r}_{2} =

L_{r}_{3} =

L_{r}, and

L_{m}_{1} =

L_{m}_{2} =

L_{m}_{3} =

L_{m}, (4)

n_{1} =

n_{2} =

n_{3} =

n_{p}/

n_{s}, and (5)

V_{Cb}_{1} =

V_{Cb}_{2} =

V_{Cb}_{3} =

V_{Cb} and

V_{C}_{1} =

V_{C}_{2} =

V_{C}_{3} =

V_{Cf}_{1} =

V_{Cf}_{2} =

V_{in}/3. The duty cycles of

Q_{1},

Q_{3} and

Q_{5} are

d. Conversely, the duty cycles of

Q_{2},

Q_{4} and

Q_{6} are 1 −

d. The equivalent circuits of the operating steps in the proposed circuit are shown in

Figure 5. There are eight operating stages for every switching period.

**Step 1 [t**_{0}~t_{1}]: Before step 1, power switches Q_{1}, Q_{3} and Q_{5} are conducting and the output current freewheels through D_{1} and D_{2}. After time t_{0}, i_{D}_{1} is decreased to zero and D_{1} becomes reverse biased. i_{o} flows through D_{2}. Power is transferred from V_{in} to R_{o} in this step. In step 1, V_{Cf}_{1} = V_{C}_{1}, V_{Cf}_{2} = V_{C}_{2}, v_{Q}_{2,ds} = V_{C}_{1}, v_{Q}_{4,ds} = V_{C}_{2}, v_{Q}_{6,ds} = V_{C}_{3}, v_{Lm}_{1} ≈ V_{C}_{1} − v_{Cb}_{1}, v_{Lm}_{2} ≈ V_{C}_{2} − v_{Cb}_{2}, v_{Lm}_{3} ≈ V_{C}_{3} − v_{Cb}_{3}, ${v}_{Lo1}\approx [{V}_{C1}-{v}_{Cb1}]/{n}_{1}-{V}_{o}$ and ${v}_{Lo2}=-{V}_{o}$. Thus, i_{p}_{1}~i_{p}_{3} and i_{Lo}_{1} increase and i_{Lo}_{2} decreases. Since all circuit components in three HB circuits are identical and n_{1} = n_{2} = n_{3} = n_{p}/n_{s}, it can obtain v_{Lm}_{1} = v_{Lm}_{2} = v_{Lm}_{3} = nv_{ns} and i_{p}_{1} = i_{p}_{2} = i_{p}_{3} ≈ i_{s}/(3n_{1}). Since i_{Lo}_{1} increases and i_{Lo}_{2} decreases in this step, the ripple current of i_{Lo}_{1} + i_{Lo}_{2} is reduced.

**Step 2 [****t**_{1}~**t**_{2}**]****:** When Q_{1}, Q_{3} and Q_{5} are turned off at time t_{1}; the positive primary currents i_{p}_{1}~i_{p}_{3} rapidly discharge C_{Q}_{2}, C_{Q}_{4} and C_{Q}_{6}, respectively. On the other hand, C_{Q}_{1}, C_{Q}_{3} and C_{Q}_{5} are charged by i_{p}_{1}~i_{p}_{3} respectively. The secondary winding voltage v_{ns} is decreased in this step.

**Step 3 [t**_{2}~t_{3}]: When C_{Q}_{2}, C_{Q}_{4} and C_{Q}_{6} are discharged to v_{Cb}_{1}, v_{Cb}_{2} and v_{Cb}_{3} respectively, then the secondary winding voltage v_{ns} = 0. Then the output current i_{o} freewheels through D_{1} and D_{2}. In this operation step, v_{Lo}_{1} = v_{Lo}_{2} = −V_{o} and i_{Lo}_{1} and i_{Lo}_{2} decrease.

**Step 4 [t**_{3}~**t**_{4}**]:** At time

t_{3},

C_{Q}_{2},

C_{Q}_{4} and

C_{Q}_{6} are discharged to zero voltage. Since

i_{p}_{1}(

t_{3})~

i_{p}_{3}(

t_{3}) are all positive, the body diodes

D_{Q}_{2},

D_{Q}_{4} and

D_{Q}_{6} are forward biased. Therefore,

Q_{2},

Q_{4} and

Q_{6} can be turned on at this moment to realize a zero-voltage turn-on. Because

i_{o} is still freewheeling through

D_{1} and

D_{2}, it can obtain

v_{ns} = 0,

v_{Lo}_{1} =

v_{Lo}_{2} = −

V_{o},

v_{Lr}_{1} = −

v_{Cb}_{1},

v_{Lr}_{2} = −

v_{Cb}_{2} and

v_{Lr}_{3} = −

v_{Cb}_{3}.

i_{p}_{1}~

i_{p}_{3},

i_{Lo}_{1} and all

i_{Lo}_{2} decrease. This step is ended when

i_{D}_{2} = 0. During this freewheeling interval, the currents

i_{Lr}_{1}~

i_{Lr}_{3} are decreased from

i_{Lo}_{1}/(3

n_{1}) to −

i_{Lo}_{2}/(3

n_{1}) and the current variation on

L_{r}_{1}~

L_{r}_{3} is about

I_{o}/(3

n_{1}). The duty loss in step 4 is obtained as (1) shows:

**Step 5 [t**_{4}~t_{5}]: After t_{4}, i_{D}_{2} is decreased to zero so that D_{2} is reverse biased. i_{o} flows through D_{1}, L_{o}_{1} and L_{o}_{2}. In step 5, power is transferred from V_{in} to R_{o}, V_{Cf}_{1} = V_{C}_{2}, V_{Cf}_{2} = V_{C}_{3}, v_{Q}_{1,ds} = V_{C}_{1}, v_{Q}_{3,ds} = V_{C}_{2}, v_{Q}_{5,ds} = V_{C}_{3}, v_{Lm}_{1} ≈ −v_{Cb}_{1}, v_{Lm}_{2} ≈ −v_{Cb}_{2}, v_{Lm}_{3} ≈ −v_{Cb}_{3}, ${v}_{Lo1}=-{V}_{o}$ and ${v}_{Lo2}\approx {v}_{Cb1}/{n}_{1}-{V}_{o}$. Thus, i_{p}_{1}~i_{p}_{3} and i_{Lo}_{1} decrease and i_{Lo}_{2} increases.

**Step** **6 [t**_{5}~t_{6}]: When Q_{2}, Q_{4} and Q_{6} turn off at time t_{5}, the negative primary currents i_{p}_{1}~i_{p}_{3} rapidly charge C_{Q}_{2}, C_{Q}_{4} and C_{Q}_{6}, respectively. On the other hand, C_{Q}_{1}, C_{Q}_{3} and C_{Q}_{5} are discharged by i_{p}_{1}~i_{p}_{3} respectively. The secondary winding voltage v_{ns} is increased in this step.

**Step 7 [t**_{6}~t_{7}]: When C_{Q}_{2}, C_{Q}_{4} and C_{Q}_{6} are charged to v_{Cb}_{1}, v_{Cb}_{2} and v_{Cb}_{3} respectively at t_{6}, it can obtain v_{ns} = 0. Thus, i_{o} freewheels through D_{1} and D_{2} in this step and v_{Lo}_{1} = v_{Lo}_{2} = −V_{o}.

**Step 8 [t**_{7}~t_{0} + T_{sw}]: When

C_{Q}_{1},

C_{Q}_{3} and

C_{Q}_{5} are discharged to zero voltage at

t_{7}, the body diodes

D_{Q}_{1},

D_{Q}_{3} and

D_{Q}_{5} are forward biased. Power switches

Q_{1},

Q_{3} and

Q_{5} can be turned on at this moment to realize zero-voltage turn-on. Since

i_{o} still freewheels through

D_{1} and

D_{2}, it can obtain

v_{ns} = 0,

v_{Lo}_{1} =

v_{Lo}_{2} = −

V_{o} and

v_{Lr}_{1} =

v_{Lr}_{2} =

v_{Lr}_{3} =

V_{in}/3 −

v_{Cb}_{1}. Thus,

i_{p}_{1}~

i_{p}_{3} increase and

i_{Lo}_{1} and

i_{Lo}_{2} decrease. This step is ended when

i_{D}_{1} = 0. During this freewheeling interval,

i_{Lr}_{1}~

i_{Lr}_{3} increase from −

i_{Lo}_{2}/(3

n_{1}) to

i_{Lo}_{1}/(3

n_{1}). The duty loss in step 8 is obtained as (2) shows.

At time t_{0} + T_{sw}, i_{D}_{1} is decreased to zero and this switching period is completed. Since the duty cycle of all switches equals 0.5, the voltage balance of C_{1}, C_{2} and C_{3} is well achieved with two balance capacitors C_{f}_{1} and C_{f}_{2}. If Q_{1}, Q_{3} and Q_{5} are in the on-state and Q_{2}, Q_{4} and Q_{6} are in the off-state, it obtains v_{Cf}_{1} = V_{C}_{1} and v_{Cf}_{2} = V_{C}_{2}. If V_{C}_{1} > V_{C}_{2} or V_{C}_{1} < V_{C}_{2}, then C_{1} charges or discharges C_{f}_{1} through Q_{1} and Q_{3}. When Q_{1}, Q_{3} and Q_{5} are in the off-state and Q_{2}, Q_{4} and Q_{6} are in the on-state, it obtains v_{Cf}_{1} = V_{C}_{2} and v_{Cf}_{2} = V_{C}_{3}. If V_{C}_{1} > V_{C}_{2} or V_{C}_{1} < V_{C}_{2}, C_{f}_{1} charges or discharges C_{2} through Q_{2} and Q_{4}. In a similar way, C_{f}_{2} can be used to balance V_{C}_{2} and V_{C}_{3}. Therefore, V_{C}_{1}~V_{C}_{3} are all controlled at V_{in}/3.

## 3. Circuit Characteristics

The asymmetric PWM scheme is adopted to drive

Q_{1}~

Q_{6}. Based on the flux balance of primary inductors such as (

L_{r}_{1} and

L_{m}_{1}), (

L_{r}_{2} and

L_{m}_{2}) and (

L_{r}_{3} and

L_{m}_{3}), the DC capacitor voltages

V_{C}_{1}~

V_{C}_{3} in a steady state can be obtained as

${V}_{Cb1}={V}_{Cb2}={V}_{Cb3}=d{V}_{in}/3$, where

d is the duty cycle of

Q_{1},

Q_{3} and

Q_{5}. In the same way, the output voltage can be derived from the flux balance of output inductors

L_{o}_{1} and

L_{o}_{2} in a steady state.

where

V_{f} is the voltage drop on

D_{1} and

D_{2}.

Since the average winding currents

i_{p}_{1}~

i_{p}_{3} equal zero and

I_{L}_{o}_{1} +

I_{L}_{o}_{2} =

I_{o}, the average inductor currents

I_{Lo}_{1} and

I_{Lo}_{2} are derived as

I_{Lo}_{1} = (1 −

d)

I_{o} and

I_{Lo}_{2} =

dI_{o}. The ripple currents on

L_{o}_{1} and

L_{o}_{2} are given in (4) and (5).

The asymmetric PWM is adopted to regulate load voltage. From

Figure 4, the turn-on time of

D_{1} is related to the duty cycle of

Q_{2} and the turn-on time of

D_{2} is related to the duty cycle of

Q_{1}. Therefore, the average diode currents

I_{D}_{1} and

I_{D}_{2} are expressed as

I_{D}_{1} = (1 −

d)

I_{o} and

I_{Lo}_{2} =

dI_{o}. The voltage stress of diodes

D_{1} and

D_{2} is related to the secondary winding voltage. The secondary winding voltage

v_{ns} is dependent on the input voltage

V_{in} and clamped voltage

V_{Cb}_{1}. Thus, the voltage stress of

D_{1} and

D_{2} can be given in (6) and (7).

The conduction losses on rectifier diodes

D_{1} and

D_{2} are approximately equal to

I_{o}V_{f}. If the transformer is constructed, then the magnetizing inductances

L_{m}_{1}~

L_{m}_{3} are given. Thus, the ripple currents

i_{Lm}_{1}~

i_{Lm}_{3} are obtained in (8).

Three HB circuits are connected in a series on the high voltage side to reduce the voltage stress of active switches. Therefore, it is able to obtain the voltage stress of each active switch clamped at

V_{in}/3. If the ripple currents on magnetizing inductors and output inductors are neglected, the root-mean-square (

rms) currents

i_{Q}_{1,rms}~

i_{Q}_{1,rms} can be derived as (9) and (10) show.

The conduction losses on

Q_{1}~

Q_{6} are approximately equal to

$d(1-d){I}_{o}^{2}{R}_{on}/(3{n}_{1}^{2})$, where

R_{on} is turn-on resistance of

Q_{1}~

Q_{6}. The positive peak currents of

i_{p}_{1}~

i_{p}_{3} at time

t_{1} are given in (11).

Likewise, the negative peak currents of

i_{p}_{1}~

i_{p}_{3} at time

t_{5} are given in (12).

The minimum primary current to realize zero-voltage turn-on switching of

Q_{1},

Q_{3} and

Q_{5} is given in (13).

Similarly, the minimum primary current to realize zero-voltage turn-on switching of

Q_{2},

Q_{4} and

Q_{6} is given in (14).

where

C_{Q} =

C_{Q}_{1} =

C_{Q}_{2} =

C_{Q}_{3} =

C_{Q}_{4} =

C_{Q}_{5} =

C_{Q}_{6}.

## 4. Experimental Results

A laboratory prototype with 1.44 kW rated power was constructed and tested in order to verify the feasibility of the studied converter to supply the auxiliary power in a light rail vehicle from the DC microgrid system. The experimental circuit diagram of the developed converter is provided in

Figure 6. The TL431 voltage regulator and photocoupler PC817 are used to regulate load voltage. The PWM UCC2893 is used to achieve asymmetric pulse-width modulation (APWM) generation. Pulse transformers are adopted to achieve electrical isolation and gate drive. The specifications of the experimental prototype are given in

Table 1. The power rating of the magnetic transformer is the same as the transformer in the three-level converter and the two-level full-bridge converter. The turns-ratio of the transformer in the developed converter is one-third of the turns-ratio in the two-level full-bridge converter. The magnetizing voltage and primary turns of the transformer in the studied converter are only one-third of the magnetizing voltage and primary turns in the two-level full-bridge converter. The PC40 EER-42 magnetic core is used with 15 primary turns and 8 secondary turns to build the isolated transformer. The experimental results of the proposed converter while it supplies 1.44 kW to the output load under a 760 V input are shown in

Figure 7,

Figure 8,

Figure 9,

Figure 10,

Figure 11 and

Figure 12. Based on the test results, the measured waveforms agree well with the theoretical waveforms as given in

Figure 4.

Figure 7 shows the gate voltages of

Q_{1}~

Q_{6} at 20% and 100% loads. It is clear that

Q_{1},

Q_{3} and

Q_{5} have the same PWM waveforms. In the same manner,

Q_{2},

Q_{4} and

Q_{6} have the same PWM waveforms. The input split voltages and balance capacitor voltages at a full load are shown in

Figure 8. From the experimental results, the input split voltages and two flying voltages are balanced well. The primary side currents of three HB circuits are illustrated in

Figure 9. It is observed that the three primary currents are balanced well.

Figure 10 gives the measured waveforms of three DC block capacitor voltages. It can be observed that the three voltages are balanced and the capacitor voltages are related to the duty cycle of

Q_{1},

Q_{3} and

Q_{5}.

Figure 11 shows the experimental waveforms of the secondary side currents. The ripple currents on

L_{o}_{1} and

L_{o}_{2} partially cancel each other so that the resultant ripple current on the load side is reduced.

Figure 12 shows the test results of

Q_{1} and

Q_{2} at 20% and 100% loads. Before the switch is turned on, the switch current is negative to discharge the output capacitor

C_{Q} to zero voltage. Thus, the mechanism of the zero-voltage turn-on switching is clearly achieved for both

Q_{1} and

Q_{2} from a 20% load. It can also be observed that all drain voltages of

Q_{1} and

Q_{2} are clamped at

V_{in}/3. Since the PWM signals of the three HB circuits are identical and the input split voltages are also balanced,

Q_{3}~

Q_{6} can also be turned on at zero-voltage from a 20% load.

Figure 13 shows the circuit efficiency of the studied converter under different load cases. The measured maximum efficiency is about 93.6%. The main advantage of the studied converter is the lower voltage rating of power switches compared to the conventional three-level converter with eight MOSFETs and the two-level full-bridge converter with four IGBTs. Considering the turns-ratio of the transformer, the root-mean-square current of the studied converter is the same as the three-level and two-level converters. However, the lower conduction resistance of MOSFETs with lower voltage rating is used in the developed converter. Therefore, the total conduction losses (six MOSFETs) in the studied converter can be reduced compared to the three-level converter with eight MOSFETs and the full-bridge converter with four IGBTs.