1. Introduction
Electric vehicles (EVs) have gained popularity in recent years, for their inherent environmental benefits of reduced gas emissions [
1,
2]. Battery systems and charging techniques are the most critical technology supporting EV market penetration [
3]. As a new wireless power transfer technology, the resonant wireless power transfer (WPT) technology, which is based on magnetic field coupling between the transmitting and receiving coils, has been seen development in recent years [
4]. Compared with the traditional charging method (e.g., plug-in), the WPT technology eases drivers from the problem of cable-exposure, tripping hazards, and risks on the snowy or rainy days [
5]. In addition, with the characteristics of flexible application, safety, and reliability, WPT technology has been applied to various applications, such as medical implantation equipment, underwater robots, and electric vehicle (EV) charging [
6,
7].
A typical EV WPT system consists of AC/DC (PFC and BUCK circuit), DC/AC (inverter circuit), resonant compensation network, transmitting coil and receiving coil, rectifier, and battery [
8]. The inverter circuit is used to transfer DC power into high frequency square wave voltage, which is key for the compensation network to achieve resonance. This paper adopts a full-bridge inverter circuit to meet high power EV charging conditions. In the inverter, if the upper and lower leg of the MOSFET are switched on at the same time, it will lead to short circuit, once the input voltage is too high, the MOSFET will be damaged. Therefore, it is required that a pair of the MOSFETs be switched on until another pair of MOSFETs are completely switched off, which means there should be dead-time between the drive signals.
Therefore, to improve the efficiency of the WPT system, it is necessary to adopt an optimal dead-time. Most previous work on the dead-time focused on the buck or boost circuit [
9], all of which are required to sample the load current or voltage, increasing the complexity of control. Other work [
10] has analyzed the relation between the optimal dead-time and turn-off related switching parameter, but it did not focus on the resonant compensation network. In [
8], the double-sided LCC resonant compensation network and its tuning method was proposed, which realizes unity power factor at both the input and output. Moreover, tuning the secondary series capacitor
C2 provides the zero-voltage switching (ZVS) condition for the MOSFET of the inverter, however, the paper did not propose a specific dead-time design method. Therefore, in this paper, a dead-time design method is proposed, by tuning the secondary series capacitor
C2 to ensure the circuit is inductive. Considering the parasitic capacitor of the MOSFET, it is crucial to adopt the optimal dead-time to improve the power and efficiency of the WPT system. An inappropriate dead-time will lead to damage of MOSFETs.
In this paper, the dead-time optimization method of ZVS is studied in the double-sided LCC resonant compensation network. The mathematical equivalent model of the double-sided LCC resonant compensation network is established, and the relation between the equivalent impedance phase of the primary side and the incremental capacitance of the secondary side capacitor
C2 is obtained in
Section 2.
Section 3 analyzes the process of charge and discharge of the parasitic capacitor of the MOSFET in a switching period, then the influence of the dead-time on the soft-switching is discussed. In the case of fixed secondary series compensation capacitor
C2, the optimization method of the dead-time is proposed in
Section 4. Experimental results verify the feasibility and correctness of the proposed method in
Section 5. Finally,
Section 6 concludes this paper.
2. Analysis of Double-Sided LCC Resonant Compensation Network Equivalent Characteristic
The configuration of the double-sided LCC resonant WPT system is shown in
Figure 1. The inverter consists of four MOSFETs (
S1~
S4) and parasitic capacitors (
Cs1~
Cs4), parasitic antiparallel diodes (
D1~
D4).
L1 and
L2 are the self-inductances of the transmitting and receiving coils, respectively.
Lp,
Cp, and C
1 are the primary side compensation inductor and capacitors.
Ls,
Cs, and
C2 are the secondary side compensation components, the secondary side is symmetrical to the primary side. M is the coefficient inductance of the two main coils. The rectifier consists of fast recovery diodes (
D5~
D8), a filtering capacitor
Co, and a filtering inductor
Lo.
For the convenience of analysis, the parasitic resistance of the capacitors, inductors, and coils are ignored. The primary and secondary resonant compensation equivalent network is shown in
Figure 2 [
11]. Where
. Where RL represents the equivalent impedance of the battery and rectifier. According to [
8], the receiving terminal can realize the unity power factor, thus, the equivalent impedance can be represented as a pure resistance, defined as
,
Pout is the output power of the WPT system.
The equivalent impedance of the secondary side circuit is
where
is the resonant frequency.
The equivalent impedance of secondary side
Zr was reflected to the primary side by the mutual inductance
M of the coils,
Zr is defined as
Therefore, the equivalent impedance of the primary side is defined as
According to [
5], the parameters of double-sided LCC resonant compensation network are designed by the following equations
Substitute (2) and (4) into (1) and (3), the equivalent impedance of the equivalent double-sided LCC compensation network is given by
It is a pure resistant load. In this case, the inverter output voltage is in phase with the output current, and unity power factor achieves, but it is not a suitable condition for MOSFETs to achieve ZVS. According to [
8], by tuning the secondary series capacitor
C2, making the circuit be inductive and thus providing conditions for the MOSFET to achieve ZVS.
After tuning the
C2, the equivalent impedance of the primary side circuit is
here Δ
C2 is the incremental value,
,
.
As is known, the ZVS condition mainly depends on the variation of load resistance and mutual inductance, in this paper, by using the equivalent resistance Zin, which relates to the load resistance RL and mutual inductance M, as (5) and (6) shown above. It is a simple method to integrate various conditions into one variable.
3. Time Domain Analysis of the Double-Sided LCC Compensation Network
3.1. Time Domain Analysis of Switching Mode
To facilitate the analysis, the following assumptions are made [
12]:
All the MOSFETs and diodes are ideal;
All the capacitors, inductors and coils are ideal;
Cs1 = Cs2 = Cs3 = Cs4 = Coss, where Coss is the output capacitor of the MOSFET;
Considering the dead-time, the main operating waveform is shown in
Figure 3.
A switching cycle can be divided into four stages. The first half switching cycle is analyzed.
Mode 1 (t0, t1): before the S1 and S4 are turned on, the inverter output current iLp is freewheeling through D1 and D4, Cs1 and Cs4 has been discharged to zero voltage. At the moment t1, S1, and S4 achieve zero voltage turn-on. UAB = Uin at this time.
Mode 2 (t1, t2): at t1, both the S1 and S4 are turned off, the inverter output current iLp (the instantaneous current when MOSFET turned off is called cut-off current) is charging the capacitor Cs1 and Cs4 to voltage Uin, while capacitors Cs2 and Cs3 are discharged to zero voltage.
The mode 3 and mode 4 are similar to mode 1 and mode 2, respectively. By tuning the capacitor C2 and dead-time optimization, the turn-off current can be minimized and reduce the MOSFET turn-off loss.
3.2. The Influence of Dead-Time on Soft-Switching
From the above analysis, the inverter output current charges and discharges the parasitic capacitors of the MOSFET during the dead-time. If the dead-time is set inappropriately, it will lead to a lower transmitting power and efficiency. Therefore, the dead-time setting is crucial for MOSFET to achieve ZVS.
Take the left arm of the inverter as an example, if the dead-time is set too short, the S1 will be turned on before the parasitic capacitor completely discharged, at the moment S1 is turned on, the parasitic capacitor short-circuits and produces an impulse current on the MOSFET, if the impulse current is larger than the pulsed drain current of the MOSFET, the MOSFET will break down.
If the dead-time is set too long, when the parasitic capacitor C1 has been discharged completely, while the S1 do not be turned on, C1 is involved in the circuit resonant, and to be charged again, making S1 fail to achieve ZVS. It is found that there is a positive current on the S1 before the S1 is switched on, which will also produce an impulse current on the S1.
5. Experiment Results
In order to validate the optimization method of dead time of switching devices in double-sided LCC resonant WPT system, a prototype is established, the experimental platform is shown in
Figure 5.
The input voltage
Uin = 100 V, output voltage
Uo = 48 V, resonant frequency
f = 95 kHz, the transfer gap h = 150 mm. The parameter of the double-sided LCC resonant WPT system are listed in
Table 1.
By increasing the capacity of C2, the WPT system circuit is inductive, the specific capacity of C2 can be set according to practical application, for convenience, in this paper we set ΔC2 = 1 nF.
In this work, Infineon IPW60R070C6 CoolMOS MOSFET is chosen as the inverter switches, its turn-off time is 88 ns, output capacitor
Coss = 215 pF. From the above analysis and parameters, it can be calculated that the dead-time should meet with the expression:
Considering the increase of MOSFET temperature, which may lead to the increase of MOSFET turn-on and turn-off time, the optimal dead-time is set 500 ns.
Figure 6 shows the voltage and current of MOSFET when
tDT = 500 ns,
tDT = 1.2 us, respectively.
From
Figure 6a, before MOSFET turned on, there is negative current on the MOSFET because of the diode freewheeling, when the drive voltage
UGS go rise to 90%, the MOSFET has forward current (
ID) and the MOSFET achieve zero voltage switch on. From
Figure 6b, because of the long dead-time, before the MOSFET is turned on, there is positive current on the MOSFET, even after the MOSFET is turned off, the voltage of the switch drops sharply to zero.
Figure 7 shows the voltage and current of inverter when
tDT = 500 ns,
tDT = 1.2 us, respectively.
From
Figure 7b, if the dead-time is too large, there is high frequency oscillation of the inverter. From the experimental results, a dead-time setting that is too short or too long will lead to distortion output voltage and current of the inverter, causing a lower efficiency and transmitting power of the WPT system.
It is known that the longer the dead time, the less effective value of the inverter voltage. When the input power is about 100 W, in
Figure 8, the conduction loss of both the dead-time situations is about 0.02 W, much less than the switching loss. It also shows that the turning on/off loss is much smaller if the proper dead time is chosen. By selecting the optimal dead time, the MOSFETs can achieve ZVS and eliminate voltage and current distortion, promoting transmitting efficiency.