A PFM-Based Calibration Method for Low-Power High-Linearity Digital Pixel

Abstract

The nonlinearity problem of digital pixels restricts the reduction in power consumption at the pixel-level circuit. The main cause of nonlinearity is discussed in this article and low power consumption is attained by reducing the static current in capacitive transimpedance amplifiers (CTIAs) and comparators. Linearity was successfully improved through the use of an off-chip calibration method. A 64 × 64 array prototype digital readout integrated circuit (DROIC) was fabricated using a 0.18 μm 1P6M CMOS process. Experimental results indicated that the post-calibration linearity reached 99.6% with an input current of up to 1.5 μA. The static power consumption per digital pixel was 6 μW.

1. Introduction

In recent years, infrared detection technology has been increasingly utilized in various applications, such as security systems, driving assistance systems, and military equipment [1,2,3,4]. Among various infrared detector materials, PbSe has gained attention due to its unique properties. As a mid-wave infrared (MWIR) detector material [5], PbSe responds to the 3–5 µm spectral range, and by adjusting the material composition, even broader spectral response ranges can be achieved. At room temperature (300 K) [6], PbSe exhibits high detectivity and a response speed on the microsecond timescale. This makes PbSe suitable for detecting fast-moving objects, such as in autonomous driving and missile detection applications [7,8]. Since it operates at room temperature without the need for cooling devices, it significantly reduces the size and power consumption of detection systems. Another characteristic of PbSe is its higher output current range compared to other materials [9,10], requiring the readout circuit to have greater charge handling capability.

For conventional readout integrated circuits (ROICs), pixel output analog signals are converted to digital through column-level analog-to-digital converters (ADCs) [11]. The charge handling capability is limited by pixel area and swing, while the frame rate is constrained by ADC speed and array size, making it difficult to meet the high-speed, high-current characteristics of PbSe. Due to their advantages of high dynamic range and high frame rate, digital pixels have been widely reported [12,13,14]. Generally, there are two methods of achieving digital outputs: in-pixel ADC and pulse frequency modulation (PFM). The former integrates ADCs at the pixel level, which increases the frame rate but does not improve the charge handling capacity. The latter generates reset signals internally to clear charges on integration capacitors, thereby enhancing charge handling capability. PFM-based designs have demonstrated a superior signal-to-noise ratio (SNR) and dynamic range performance [6,8].

PbSe is a photoconductive detector, and a capacitive transimpedance amplifier (CTIA) is used as the input stage for PFM-based digital pixels [15], due to its ability to provide a more stable bias and higher injection efficiency. A comparator is used to compare the integrated voltage and generate a reset signal. The frequency of the reset signal is proportional to the input signal current [16]. Dealing with higher input currents requires operational amplifiers and comparators with greater bandwidth. However, this leads to an increase in power consumption. Insufficient bandwidth can lead to nonlinear output [17]. To address this, a soft reset mechanism has been introduced [18]. The soft reset mechanism involves the use of non-overlapping phases and an additional capacitor, which inevitably increases area and power consumption [15].

In this study, an analysis of the nonlinearity of PFM digital pixels was conducted, and an off-chip calibration method was proposed to mitigate these nonlinearities. Analysis revealed a linear relationship between the difference in reset voltages and flip voltages and the input current. Taking advantage of this property, an off-chip calibration was implemented in this paper. A prototype in the form of a 64 × 64 DROIC array was fabricated to validate the calibration method. The proposed method offers the benefit of reduced power consumption and improved linearity, and is particularly applicable to detectors that generate large currents.

2. PFM-Based Digital Pixel and Nonlinearity

A schematic of a conventional PFM-based digital pixel is shown in Figure 1a. In the operation of the digital pixel, the CTIA output is initially set to the reference voltage ($V_R$) during the reset phase. As the exposure phase begins, the current $I_s$ is integrated into the capacitor ($C_{int}$). When the voltage $V_{int}$ reaches the flip voltage $V_F$, the comparator generates the self-reset (SR) signal for the CTIA and also serves as an input for the counter. Ideally, the SR signal resembles a series of pulses with a frequency directly related to the magnitude of $I_s$ [19], as shown in Figure 1b. The counter will accumulate the SR signals during the exposure time $T_{int}$ and store the data in SRAM for subsequent readout. Under ideal conditions, the digital output can be expressed as

$$N={\displaystyle \frac{T_{int}·I_s}{∆V·C_{int}}}$$

(1)

where $V$ means the difference between $V_F$ and $V_R$. In an ideal case, $∆V=V_F-V_R={∆V}_S$, and there is a linear relationship between the input current and the output count.

In practice, it is a challenge to implement a comparator without delay, which means the comparator may not flip precisely when $V_{int}$ reaches $V_F$, as shown in Figure 1c. $V_{int}$ will continue to integrate and exceed $V_F$ to a new level (denoted as $V_{FA}$), at which point the SR pulse will be generated. The over-integrated voltage will increase with the input current increasing. Once the self-reset signal is triggered, $V_{int}$ will rapidly decrease. The short reset time for the CTIA necessitates that AMP1 has a wide gain–bandwidth product (GBW) to ensure that $V_{int}$ can be discharged precisely to the baseline voltage $V_R$. If the GBW of AMP1 is limited, the reset voltage may not return exactly to $V_R$, leading to a new voltage difference, which is referred to as ${∆V}_A$ in this paper.

Based on the analysis, the over-integrated voltage $V_{FA}$ can be written as

$$V_{FA}=V_F+{\displaystyle \frac{I_S\times t_p}{C_{int}}}$$

(2)

where $t_p$ is the delay of comparator, as expressed in [20].

$$t_p={\tau }_C\times \ln {\displaystyle \frac{2k}{2k-1}}$$

(3)

$$k={\displaystyle \frac{∆V}{V_{min,comp}}}$$

(4)

$$V_{min,comp}={\displaystyle \frac{V_{OH}-V_{OL}}{A_{VC}}}$$

(5)

where ${\tau }_C=1/{\omega }_C$, ${\omega }_C$ is −3 dB bandwidth, $V_{OH}$ and $V_{OL}$ represent the output voltage of high level and low level, and $A_{VC}$ is the open-loop gain. By utilizing Taylor series expansion and neglecting higher-order terms, Equation (3) can be rewritten as

$$t_p={\tau }_C\times \left({\displaystyle \frac{2k}{2k-1}}-1\right)={\displaystyle \frac{{\tau }_C}{2k-1}}.$$

(6)

Once the self-reset signal is generated, the system goes into discharge state. The discharge equation is given by

$$V_{int}\left(t\right)=V_{FA}\times e^{-{\displaystyle \frac{t}{{\tau }_A}}}$$

(7)

where ${\tau }_A=1/{\omega }_A$, and ${\omega }_A$ is the unity gain bandwidth of AMP1. We assume the discharge time is $t_H$; then, $V_{RA}$ is found as

$$V_{RA}=V_{FA}\times e^{-{\displaystyle \frac{t_H}{{\tau }_A}}}.$$

(8)

Thus,

$${{{∆V}_A=V}_{FA}-V}_{RA}=V_{FA}\times \left(1-e^{-{\displaystyle \frac{t_H}{{\tau }_A}}}\right).$$

(9)

Substituting Equation (2) into Equation (9),

$${∆V}_A=V_F\times \left(1-e^{-{\displaystyle \frac{t_H}{{\tau }_A}}}\right)+{\displaystyle \frac{{\tau }_C}{C_{int}\times \left(2k-1\right)}}\times \left(1-e^{-{\displaystyle \frac{t_H}{{\tau }_A}}}\right)\times I_S.$$

(10)

The formula shows that ${∆V}_A$ is related to the comparator speed, operational amplifier bandwidth, and input current. There is a linear relationship between ${∆V}_A$ and the input current, and when the comparator and operational amplifier are faster, the slope of this linear relationship becomes smaller. It can be observed that the amount of charge corresponding to each integration reset process increases as the integration current increases. When power consumption is limited or the input current is large, if $∆V$ in Equation (1) is not corrected, the resulting count value will deviate from the actual value. And as the input current increases, the output nonlinearity becomes more evident. This is the main cause of nonlinearity when dealing with large input currents. Schematic-level simulation is performed and linear fitting is applied to the ${∆V}_A$ data. Simulation data also confirm the linear relationship between ${∆V}_A$ and $I_S$, as shown in Figure 2.

3. DROIC Design

The prototype DROIC is fabricated using a 0.18 μm 1-poly 6-metal CMOS process. The block diagram of DROIC is shown in Figure 3. The core of the DROIC consists of a 64 × 64 array of PFM-based digital pixels, column and row selectors, and an output buffer. Additionally, an Analog Buffer & MUX module is used to acquire the data for calibration.

The digital pixels are based on Figure 1. A current source is used to imitate the detector. The current level is set to be adjustable based on the PbSe detector. The telescopic cascode structure is chosen for the AMP1 and comparator because it can achieve high gain and wide GBW at low currents. The tail current for the AMP1 and comparator is 1.8 μA and 1.5 μA, respectively. Under a power supply of 1.8 V, the static power consumption of the digital pixel is approximately 6 μW. The pixel layout is shown in Figure 4. The pixel size is 50 μm × 50 μm, with a 50 fF integrated capacitor, a 12-bit counter, and SRAM. Most of the pixel size is occupied by digital circuits.

To obtain the data for the calibration method, the $V_{int}$ signal of some pixels can be output externally through the Analog Buffer & MUX module. A total of 10 pixels of $V_{int}$ in the pixel array are connected to this module. One of the $V_{int}$ outputs is selected by MUX and sent outside the chip to measure ${∆V}_A$.

To achieve a higher frame rate, the prototype can operate in integration-while-read (IWR) mode, with the timing diagram shown in Figure 5. Before integration begins, the RST signal resets the circuit to its initial state. When the INT signal arrives, integration and counting start. At the end of integration, the WR signal writes the counter value to the SARM. When the integration signal for the next frame begins, the data from the previous frame are transferred to the output buffer and read out by controlling the ROW and COL signals. The readout time of the data is shorter than the integration time to ensure that the data from the previous frame are fully read out before the next WR signal arrives.

4. Measurement Results

$V_R$ and $V_F$ were generated by the bias circuit, with values of 0.8 V and 1 V, respectively. Different input currents from 10 nA to 1500 nA were applied to the pixels and the resulting ${∆V}_A$ was measured as shown in Figure 6. A similar linear relationship exists between the measured data and the simulation results, which indicates a consistent behavior of the system.

The average value of the data was used to calibrate the obtained digital code, as shown in Figure 6, and the calibration formula is as follows:

$$N_c=N_A\times {\displaystyle \frac{\overline{∆V_A}}{∆V_S}}$$

(11)

where $\overline{∆V_A}$ is the average value of the measured data. $N_A$ is the digital output of the pixel array. The data before and after calibration are shown in Figure 7.

Five pixels inside the array were selected for calibration, which were located at the center and four corners of the array. Figure 7a demonstrates that the nonlinear trends were successfully calibrated. The differences between the five calibrated pixels may be attributed to the mismatch in the pixel array and in the current mirror used to provide the input current. In Figure 7b, we use the average value of 64 × 64 array before and after calibration. The coefficient of determination of the linear fitted curve for the post-calibration data is 0.9991, indicating a high correlation between the average data points and the fitted curve. This value suggests that the calibration process was highly effective in reducing nonlinearity and improving the accuracy of the system response.

When the input current is low or the integration time is short, meaning the total input charge is small, the count value will be relatively low, leading to less significant nonlinearity. As shown in Figure 7, the difference in digital number before and after calibration is small. To demonstrate the applicability of the calibration method proposed in this paper, a set of data with a long integration time was measured, where the integration time was 1 ms. Linear fitting was applied to the data as shown in Figure 8. The data represent the average value of 4096 pixels. The coefficient of determination of the fitted curve before and after calibration is 0.9979 and 0.9999, respectively. Since the deviation of $∆V_A$ is smaller at low input current than at high input current, the nonlinearity is less significant at lower currents. However, the calibration method proposed in this paper remains effective.

Table 1. Comparison of DROIC performance.

	[15]	[21]	[22]	This Work
Array Size	128 × 128	640 × 512	640 × 512	64 × 64
Pixel Size (μm)	50 × 50	25 × 25	15 × 15	50 × 50
Input Structure	CTIA	CTIA	DI	CTIA
Pixel Type	Digital	Digital	Analog	Digital
Max Input Current	2 μA	60 nA	-	1.5 μA
Resolution (bits)	10	13	-	12
Capacity (Me−)	-	350	4.5	560
Frame Rate (fps)	4000	730	300	4000
Static Power	10 μW/pixel	-	100 mW	6 μW/pixel

shows the performance comparison of this work and some reported DROICs for IRFPAs. For the PbSe photoconductive detector, a CTIA is typically used as the input stage. Although it consumes more power than a DI, it can provide a more stable voltage bias. This work uses the most classic PFM structure, and through the correction methods, it maintains linearity in the output at a maximum input current of 1.5 μA, thereby reducing the power consumption of the readout circuit at high current inputs. A soft reset circuit was added within the pixel in [15], achieving good linearity under large current conditions. However, its static power consumption was about 1.6 times that of the proposed work. Additionally, the integration capacitor used was 200 fF, and a larger integration capacitor reduces the auto-reset frequency, resulting in lower power consumption compared to the 50 fF integration capacitor used in this work. The calibration method proposed in this paper demonstrates a more significant reduction in power consumption. When the pixel operates in IWR mode, the chip’s frame rate can reach 4000 fps (frames per second), better addressing the response speed of PbSe.

5. Conclusions

A 64 × 64 array prototype fabricated in a 180 nm CMOS process shows the practical implementation of the calibration method. The effectiveness of the proposed technique is demonstrated by measuring $∆V_A$ and successfully calibrating the nonlinearity outside the chip. The nonlinear calibration method introduced for the conventional PFM structure represents a significant advancement in pixel array design. This approach reduces power consumption and improves linearity without the need for assisting circuits within each pixel. Leveraging the simple PFM structure, the prototype achieves a high input range, high linearity, and low static power consumption of 6 μW per pixel.