# 0.3-Volt Rail-to-Rail DDTA and Its Application in a Universal Filter and Quadrature Oscillator

^{1}

^{2}

^{3}

^{4}

^{5}

^{*}

## Abstract

**:**

_{pp}@ 84.47 Hz input voltage. The slight modification of the filter yields a quadrature oscillator. The condition and the frequency of oscillation are orthogonally controllable. The frequency of oscillation can also be controlled electronically. The THD for a 67 Hz oscillation frequency was around 1.2%. The circuit is designed and simulated in a Cadence environment using 130 nm CMOS technology from United Microelectronics Corporation (UMC). The simulation results confirm the performance of the designed circuits.

## 1. Introduction

## 2. DDTA and Its CMOS Structure

_{1}–M

_{6}, and the class-A output stage, M

_{9}–M

_{10}. The capacitance C

_{C}is used for frequency compensation. Its value can be calculated in the same way as that for a two-stage operational amplifier. The input stage of the DDCC circuit can be seen as a non-tailed differential pair with an additional partial positive feedback (PPF) circuit. The solution, first presented in [2] and experimentally validated in [3], has been adopted here. The transistors, M

_{7}and M

_{8}, generate negative conductances, -g

_{m}

_{7}and -g

_{m}

_{8}, which partially compensate for the positive conductances of the diode-connected transistors, M

_{2A,B}(≈g

_{m}

_{2}), thus increasing the resistances at the gate-drain nodes of these transistors, and consequently the voltage gain from inputs to the gate terminals of M

_{1A,B}. This improves the overall transconductance and voltage gain of the first stage.

_{1A,B}have been replaced by bulk-driven MI-MOST transistors. The symbol and CMOS realization of these devices are shown in Figure 3. This approach allows design simplification and the decreasing of the total dissipation power by removing one differential stage of the conventional DDCC. This is the result of the fact that summation of input signals is realized using the passive voltage divider/summing circuit composed of the capacitances C

_{Bi}(see Figure 3b). The capacitances are shunted by large resistances, R

_{MOSi}, that allow proper DC biasing of the bulk terminals of M

_{1A,B}. The resistors are realized as the antiparallel connection of two MOS transistors operating in a cutoff region, as shown in Figure 3c.

_{m}is the transconductance of the input differential stage given by:

_{Bi}are equal to each other and the input capacitance of the MOS transistor from its bulk terminal can be neglected. The factor m represents the absolute value of the ratio of negative to positive conductances at the gate/drain nodes of M

_{2A,B}:

_{m}as well as the voltage gain A

_{vo}tend to infinity, as m tends to unity, namely, when the negative conductances generated by M

_{7}and M

_{8}fully compensate the positive conductances of M

_{2}, thus leading to infinite voltage gain from inputs to the drain/gate nodes of M

_{2A,B}. However, when the difference between g

_{m}

_{2}and g

_{m}

_{7,8}is decreasing, namely when m is increasing to unity, then the circuit sensitivity to transistor mismatch is increasing as well, which limits the maximum value of m. The second limitation is associated with the location of the parasitic pole associated with the PPF circuit, which is given by the formula

_{∑}is the total capacitance associated with the gate/drain nodes of M

_{2A,B}. Note that the frequency of this pole decreases with increasing m, namely, as the total resistance at the gate/drain nodes of M

_{2}increases with increasing positive feedback. For stable operation, the pole should be located well above the GBW product of the internal DDA, which is

_{vo}. The 3 dB frequency of this function is approximately equal to ω

_{GBW}. The low-frequency output resistance at the W terminal is given as follows:

_{outW}is also improved (decreased) thanks to the larger value of A

_{vo}.

_{B}is identical with M

_{3}and M

_{4}, the DC transfer characteristic of the TA in Figure 2 can be described by the formula [4]

_{p}is the subthreshold slope factor for a p-channel MOS, U

_{T}is the thermal potential, and η = (n

_{p}− 1) = g

_{mb}

_{1,2}/g

_{m}

_{1,2}is the bulk-to-gate transconductance ratio for transistors M

_{1}and M

_{2}.

_{set}, while still maintaining good linearity of its transfer characteristic.

_{m}of the TA in the general case is

_{m}

_{1,2}), it is equal to 4g

_{mb}

_{1,2}/3.

## 3. Proposed Applications

#### 3.1. Proposed Universal Filter

_{in}

_{1}, V

_{in}

_{2}, V

_{in}

_{3}, V

_{in}

_{4}, and V

_{in}

_{5}provide high-input impedances, and the terminals V

_{o}

_{1}and V

_{o}

_{3}low-output impedances, whereas the terminals V

_{o}

_{2}and V

_{o}

_{4}require external buffer circuits if a low-impedance load is applied.

#### 3.2. Proposed Quadrature Oscillator

_{o}

_{3}and V

_{o}

_{4}provide quadrature output signals. It can be confirmed by the relationship between V

_{o3}and V

_{o4}:

_{o}

_{3}and V

_{o}

_{4}is 90°. After setting s = jω

_{0}into (24) and taking into account Equations (22) and (23) and the condition g

_{m}

_{1}= g

_{m}

_{2}, the ratio (24) is one; thus, if oscillation condition (22) is accomplished, the oscillator provides equal amplitudes of both quadrature signals independently of the oscillation frequency.

#### 3.3. Non-Idealities Analysis

_{o}and resistance R

_{o}at o-terminal. In the frequency range near the cutoff frequency, ${g}_{mni}$ can be approximated as [48]

_{m}asserts its influence, then (26) should be used to refine the error analysis.

## 4. Simulation Results

_{DD}= −V

_{SS}= 0.15 V), the bias current of the DDCC I

_{B}= 50 nA, and the nominal value of the setting current of the TA I

_{set}= 500 nA. The nominal power consumption of the DDTA is 357.4 nW (DDCC = 70.21 nW, TA = 287.2 nW). The input and compensation capacitors are highly linear metal–isolator–metal capacitors (MIM). The linear resistor R is a high-resistance poly-resistor.

_{W}/V

_{Y1}(=V

_{W}/V

_{Y3}) and V

_{W}/V

_{Y2}is 14 mdB and 57.29 mdB, while the −3 dB bandwidth is 22.24 kHz and 22.23 kHz, respectively.

_{set}= 0.5 µA and 20 pF load capacitance are shown in Figure 8. The low DC gain is 23.2 dB, and the bandwidth (BW) is 19.65 kHz, while the phase error is 3.8°.

_{in}(V

_{in}= V

_{+}− V

_{y4}) for the TA for I

_{set}= 0.125 µA, 0.25 µA, and 0.5 µA. The rail-to-rail operation with high linearity is evident.

_{DD}− V

_{SS}) ± 10%, and the temperature corners were −20 °C and 70 °C. Table 3 and Table 4 show the results of the minimum, nominal, and maximum values of the gain, −3 dB BW for the DDCC, and gain and phase error for the TA. The impact of the PVT corners in all cases is acceptable.

_{1}= C

_{2}= 5 nF, which are off-chip capacitors. The magnitude characteristics of the LPF, HPF, BPF, BSF, and APF are shown in Figure 12. The simulated natural frequency (f

_{o}) is around 81.47 Hz. It is worth mentioning that, due to the limited value of the output resistance of the TA, which is around 5.1 MΩ, the attenuations of the HPF and BPF are degraded at low frequencies. Therefore, if an application demands higher attenuation, then the output resistance could be increased, employing the MOS transistor self-cascode technique.

_{in}= 100 mV

_{pp}@ 81.47 Hz. The waveforms of the input and output voltages are shown in Figure 13a. The spectrum of the output signal is shown in Figure 13b, where the total harmonic distortion (THD) of the BPF output is 0.5%.

_{set}= 0.125, 0.25, 0.5, and 0.75 µA, is shown in Figure 14. The f

_{o}was in the range of 21.11 Hz, 41.63 Hz, 81.47 Hz, and 115.74 Hz, respectively.

_{3}and V

_{4}are 1.2% and 1.29%, respectively.

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 9.**The DC output current (

**a**) and transconductance g

_{m}(

**b**) characteristics of the TA versus input voltage.

**Figure 10.**The DDCC histogram of the gain V

_{w}/V

_{Y1}(

**a**), V

_{w}/V

_{Y2}(

**b**), and the −3 dB BW V

_{w}/V

_{Y1}(

**c**), and V

_{w}/V

_{Y2}(

**d**).

**Figure 14.**Magnitude characteristics showing the tuning capability of the LPF (

**a**), BPF (

**b**), HPF (

**c**), and BSF (

**d**) with different bias currents.

Filtering Function | Input | Output | |
---|---|---|---|

LP | Non-inverting | ${V}_{in4}={V}_{in5}$ | ${V}_{o1}$ |

Non-inverting | ${V}_{in5}$ | ${V}_{o2}$ | |

Inverting | ${V}_{in1}={V}_{in4}$ | ${V}_{o2}$ | |

Non-inverting | ${V}_{in5}$ | ${V}_{o3}$ | |

Non-inverting | ${V}_{in1}$ | ${V}_{o4}$ | |

Non-inverting | ${V}_{in2}$ | ${V}_{o4}$ | |

Inverting | ${V}_{in4}={V}_{in5}$ | ${V}_{o4}$ | |

BP | Non-inverting | ${V}_{in3}$ | ${V}_{o1}$ |

Inverting | ${V}_{in4}$ | ${V}_{o1}$ | |

Non-inverting | ${V}_{in1}$ | ${V}_{o2}$ | |

Non-inverting | ${V}_{in2}$ | ${V}_{o2}$ | |

Inverting | ${V}_{in4}={V}_{in5}$ | ${V}_{o2}$ | |

Non-inverting | ${V}_{in1}$ | ${V}_{o3}$ | |

Non-inverting | ${V}_{in2}$ | ${V}_{o3}$ | |

Non-inverting | ${V}_{in4}$ | ${V}_{o4}$ | |

Inverting | ${V}_{in3}$ | ${V}_{o4}$ | |

Inverting | ${V}_{in1}={V}_{in5}$ | ${V}_{o4}$ | |

HP | Non-inverting | ${V}_{in1}={V}_{in4}$ | ${V}_{o1}$ |

Inverting | ${V}_{in3}$ | ${V}_{o3}$ | |

Non-inverting | ${V}_{in4}$ | ${V}_{o3}$ | |

BS | Non-inverting | ${V}_{in4}={V}_{in5}$ | ${V}_{o3}$ |

AP | Non-inverting | $-{V}_{in2}={V}_{in4}={V}_{in5}$ | ${V}_{o3}$ |

Device | W/L (µm/µm) |
---|---|

M_{1A}, M_{2A}, M_{1B}, M_{2B} | 20/3 |

M_{7}, M_{8} | 15/3 |

M_{3}–M_{6}, M_{B} | 10/3 |

M_{9} | 6 × 10/3 |

M_{10} | 6 × 20/3 |

M_{R} | 5/3 |

MIM capacitor: C_{B} = 0.2 pF, Cc = 4 pF | |

Poly-resistor R = 90 kΩ |

DDCC | min. | nom. | max. |
---|---|---|---|

P/V/T | P/V/T | ||

Gain V_{W}/V_{Y1} [mdB] | −75.3/9.8/−224 | 14 | 29.4/14/14 |

Gain V_{W}/V_{Y2} [mdB] | −14.1/45.8/−75 | 57 | 101/67.3/57 |

−3 dB V_{W}/V_{Y1} [kHz] | 20.2/22/21 | 22.24 | 25.2/22.1/23.7 |

−3 dB V_{W}/V_{Y2} [kHz] | 20.1/22/20.8 | 22.23 | 25/22.7/23.4 |

TA | min. | nom. | max. |
---|---|---|---|

P/V/T | P/V/T | ||

Gain [dB] | 23/20.6/21.9 | 23.19 | 23.2/25.2/24 |

Phase error [°] | 3.7/2.9/3.4 | 3.8 | 3.8/5.1/4.3 |

G_{m} [µS] | 2.2/2.2/2.2 | 2.48 | 2.5/2.5/2.4 |

Features | Proposed | Ref. [23] | Ref. [41] | Ref. [42] | Ref. [44] | Ref. [46] | Ref. [47] |
---|---|---|---|---|---|---|---|

Active and passive elements | 2 DDTA, 2 C | 5 OTA, 2 C | 5 OTA, 2 C | 4 OTA, 2 C | 3 CFOA, 2 C, 4 R | 3 VDBA, 2 C, 1 R (Figure 2) | 8 OTA, 2 C (Figure 3) |

Realization | CMOS structure (130 nm) | CMOS structure (180 nm) & commercial IC | commercial IC | commercial IC | CMOS structure (180 nm) | CMOS structure (180 nm) | CMOS structure (180 nm) |

Filter type | MIMO | MISO | MIMO | MIMO | MOMO | MISO | MIMO |

Number of filtering functions | 22 (VM) | 11 (VM) | 13 (VM) | 9 (VM) | 5 (VM) | 20 (Mixed-mode) | 20 (Mixed-mode) |

Offer universal filter and oscillator | Yes | Yes | Yes | Yes | Yes | No | No |

Electronic control of parameter ${\omega}_{o}$ | Yes | Yes | Yes | Yes | No | Yes | Yes |

Natural frequency (kHz) | 0.08147 | 1 | 217 | 144.7 | 757.88. | 16.631 × 10^{3} | 5.77 |

Total harmonic distortion (%) | 0.5@100 mV_{pp} | 1.67@600 mV_{pp} | 1.93@200 mV_{pp} | 3.83@170 mV_{pp} | [email protected] V_{pp} | <3@500 mV_{pp} | <2@200 mV_{pp} |

Power supply voltages (V) | 0.3 | 1.2 | ±15 | ±15 | ±0.9 | ±1.25 | ±0.3 |

Simulated power consumption (µW) | 0.715 | 96 | 860 × 10^{3} | 0.92 × 10^{6} | 5.4 × 10^{3} | 5.482 × 10^{3} | 5.77 |

Verification of result | Sim | Sim/Exp | Sim/Exp | Sim/Exp | Sim/Exp | Sim/Exp | Sim |

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**MDPI and ACS Style**

Khateb, F.; Kumngern, M.; Kulej, T.; Biolek, D.
0.3-Volt Rail-to-Rail DDTA and Its Application in a Universal Filter and Quadrature Oscillator. *Sensors* **2022**, *22*, 2655.
https://doi.org/10.3390/s22072655

**AMA Style**

Khateb F, Kumngern M, Kulej T, Biolek D.
0.3-Volt Rail-to-Rail DDTA and Its Application in a Universal Filter and Quadrature Oscillator. *Sensors*. 2022; 22(7):2655.
https://doi.org/10.3390/s22072655

**Chicago/Turabian Style**

Khateb, Fabian, Montree Kumngern, Tomasz Kulej, and Dalibor Biolek.
2022. "0.3-Volt Rail-to-Rail DDTA and Its Application in a Universal Filter and Quadrature Oscillator" *Sensors* 22, no. 7: 2655.
https://doi.org/10.3390/s22072655