Mao, X.; Yang, F.; Wei, F.; Shi, J.; Cai, J.; Cai, H.
A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA. Sensors 2022, 22, 2306.
https://doi.org/10.3390/s22062306
AMA Style
Mao X, Yang F, Wei F, Shi J, Cai J, Cai H.
A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA. Sensors. 2022; 22(6):2306.
https://doi.org/10.3390/s22062306
Chicago/Turabian Style
Mao, Xiangyu, Fei Yang, Fang Wei, Jiawen Shi, Jian Cai, and Haiwen Cai.
2022. "A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA" Sensors 22, no. 6: 2306.
https://doi.org/10.3390/s22062306
APA Style
Mao, X., Yang, F., Wei, F., Shi, J., Cai, J., & Cai, H.
(2022). A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA. Sensors, 22(6), 2306.
https://doi.org/10.3390/s22062306