# Design of a High-Efficiency DC-DC Boost Converter for RF Energy Harvesting IoT Sensors

^{*}

## Abstract

**:**

## 1. Introduction

#### 1.1. Main Contribution

#### 1.2. Organization

## 2. Previous DC-DC Boost Converters for Energy Harvesting

## 3. Efficiency Problem and System Model of DC-DC Boost Converter

#### 3.1. Efficiency Problem in Boost Converter for RF Energy Harvesting

#### 3.2. System Model of DC-DC Boost Converter

_{1}, PMOS switch M

_{2}, and a control circuit that drives the switches.

_{L}) waveform of the DC-DC boost converter. The DCM operation of the DC-DC boost converter has three stages: on time (T

_{ON}), off time (T

_{OFF}), and dead time (T

_{DEAD}). During the on-time phase, the NMOS switch M

_{1}turns on and the PMOS switch M

_{2}turns off. In this phase, the current through the inductor I

_{L}increases at a constant slope up to the peak inductor current (I

_{P}), so magnetic energy is stored in the inductor. As the output capacitor C is discharged by the constant load current source, the output voltage decreases with a constant slope. During the off-time phase, switch M

_{1}turns off and switch M

_{2}turns on. In this phase, the output capacitor is not only discharged by the constant load current but also charged by the current flowing through the inductor. Thus, the energy in the inductor is transferred to the output load current (I

_{LOAD}) and output capacitor, and the inductor current decreases with a constant slope from I

_{P}to zero. During the dead-time phase, the PMOS switch M

_{2}opens and the NMOS switch M

_{1}remains open. In this phase, both the voltage across the inductor and the inductor current flowing through it are zero because both switches are open. The output of the converter is in the same state as the on-time phase, and the output voltage decreases with a constant slope as the output capacitor is discharged by the constant load current source. In DCM operation, the switching frequency is expressed in terms of inductance L and peak inductor current I

_{P}for given V

_{IN}, V

_{OUT}, and I

_{LOAD}conditions as

_{LOAD}is the load current.

_{IN}and P

_{OUT}are the input and output power of the converter, respectively, and P

_{TOTAL}represents the total losses of the converter including conduction loss due to equivalent series resistance (ESR) of the inductor, conduction loss due to switches, switching loss of NMOS and PMOS, and switching loss of buffer stages. The proposed design methodology to obtain the maximum PCE by minimizing the total loss according to different input voltages in a wide input voltage range is based on the loss analysis and modeling of an inductor-based DC-DC boost converter.

## 4. Loss Analysis and Modeling of DC-DC Boost Converter

_{ESR,L}, of the inductor is expressed as:

_{1}and M

_{2}, R

_{M1}and R

_{M2}, respectively, and the losses due to the leakage current per unit width of the switches M

_{1}and M

_{2}, I

_{LEAK,M}

_{1}and I

_{LEAK,M}

_{2}, respectively. The conduction loss due to the switches is expressed as:

_{M}

_{1}and W

_{M}

_{2}are the widths of M

_{1}and M

_{2}, respectively.

_{1}and M

_{2}, C

_{GD,M}

_{1}and C

_{GD,M}

_{2}, respectively, with the Miller effect, the drain–body capacitances per unit width of M

_{1}and M

_{2}, C

_{DB,M}

_{1}and C

_{DB,M}

_{2}, respectively, and the parasitic capacitance of the inductor, C

_{L,PAR}, expressed as:

_{GS,M}

_{1}and C

_{GS,M}

_{2}, respectively, additional power is consumed by the buffer stages. The switching loss of the buffer stages is proportional to the gate equivalent capacitance of M

_{1}and M

_{2}with the Miller effect and is expressed as:

_{IN}= 0.1 V, V

_{OUT}= 1 V, I

_{LOAD}= 1 mA, W

_{M1}= W

_{M2}= 20 mm, and I

_{P}= 30 mA. The inductor is designed as an off-chip component and the DCR of the inductor is modeled as a resistance value that increases with L. As shown in Figure 4, as the inductance increases, conduction loss of the inductor increases and switching loss and buffer loss decrease.

_{1}and M

_{2}switches using (3)–(6) when V

_{IN}= 0.1 V, V

_{OUT}= 1 V, I

_{LOAD}= 1 mA, L = 10 μH, and I

_{P}= 30 mA. As shown in Figure 5, as the width of the MOSFET switches increases, conduction loss of the switches decreases and the switching loss and buffer loss increase.

_{P}using (3)–(6) when V

_{IN}= 0.1 V, V

_{OUT}= 1 V, I

_{LOAD}= 1 mA, W

_{M1}= W

_{M2}= 20 mm, and L = 10 μH. As the peak inductor current increases, conduction loss of the inductor and switches increase and switching loss and buffer loss decrease.

## 5. Proposed Efficiency Optimization Design

_{PWM}) is used to drive the switch transistor M

_{1}through the buffer. The time delay controlled by the digital gates and C

_{DELAY}compensates for the time delay between the switch control signals V

_{N}and V

_{P}so that transistor M

_{2}turns on quickly enough after transistor M

_{1}turns off. The output of the OR gate drives the gate of the switch transistor M

_{2}through a buffer. Current sensing for switch transistor M

_{2}is performed by a comparator and the comparator’s output signal is used to sense when the current through switch transistor M

_{2}goes to zero.

_{TOTAL}) as a function of inductance L using (7) for input voltages of 0.1 V, 0.2 V, and 0.4 V, respectively, when V

_{OUT}= 1 V, I

_{LOAD}= 1 mA, W

_{M}

_{1}= W

_{M}

_{2}= 20 mm, and I

_{P}= 30 mA. Figure 9 shows the modeled power conversion efficiency (PCE) as a function of the inductance L using (7) for input voltages of 0.1 V, 0.2 V, and 0.4 V, respectively. As the input voltage increases, the optimum inductance to achieve the minimum total loss increases. At an input voltage of 0.1 V, a maximum efficiency of 96.5% is achieved when L is 6.8 μH. At input voltages of 0.2 V and 0.4 V, maximum efficiencies of 97.7% and 98.5% are achieved when L is 10 μH, respectively.

_{TOTAL}) as a function of peak inductor current I

_{P}using (7) for input voltages of 0.1 V, 0.2 V, and 0.4 V, respectively, when V

_{OUT}= 1 V, I

_{LOAD}= 1 mA, L = 10 μH, W

_{M}

_{1}= W

_{M}

_{2}= 20 mm. Figure 11 shows the PCE according to the peak inductor current (I

_{P}) for input voltages of 0.1 V, 0.2 V, and 0.4 V, respectively. As the input voltage increases, the optimum peak inductor current to achieve the minimum total loss increases. At an input voltage of 0.1 V, a maximum efficiency of 96.6% is achieved when I

_{P}is 29 mA. At an input voltage of 0.2 V, a maximum efficiency of 97.7% is achieved when I

_{P}is 31 mA, and at an input voltage of 0.4 V, a maximum efficiency of 98.7% is achieved when I

_{P}is 33 mA.

## 6. Simulation Results and Comparison

_{N}and V

_{P}, internal node voltage V

_{X}, output voltage V

_{OUT}, and inductor current I

_{L}for an input voltage of 0.1 V.

_{N}and V

_{P}are the output signals of the control circuit to control the switch on-off of the converter. When V

_{N}and V

_{P}are high at the same time, the inductor is connected to ground during on time so that I

_{L}increases from 0 mA to 29 mA and the load capacitor is discharged by the load current and V

_{OUT}decreases. When V

_{N}and V

_{P}are low at the same time, the inductor is connected to the output during off time and the output capacitor is not only discharged by the constant load current but also charged by the inductor current, so that V

_{OUT}increases. Conduction losses mainly occur as current flows during on time and off time. During the dead time when V

_{N}is low and V

_{P}is high, no current flows through the inductor and, as in the on-time period, the output capacitor is discharged by constant load current and V

_{OUT}decreases. Ringing occurs due to the resonance of the inductor and parasitic capacitor during dead time.

_{OUT}= 1 V, I

_{LOAD}= 1 mA, W

_{M}

_{1}= W

_{M}

_{2}= 20 mm, and I

_{P}= 30 mA. As the inductance decreases, the switching frequency increases and the switching losses of NMOS and PMOS increase. On the other hand, as the inductance increases, the ESR of the inductor increases and conduction loss of the inductor increases. Therefore, there is an optimal inductance value that minimizes the total loss. It shows that the modeled total loss of the boost converter agrees well with the circuit simulation results, with a minimum loss of 36.4 μW achieved for an L of 6.8 μH. Figure 14 shows the PCE of the converter according to L for an input voltage of 0.1 V and compares the circuit simulation results with the proposed modeling results. A maximum efficiency of 96.5% is achieved at an optimum L of 6.8 μH and the proposed model accurately predicts the optimal L value to obtain the maximum PCE.

_{1}and M

_{2}switches for an input voltage of 0.1 V and compares the circuit simulation results with the proposed modeling results when V

_{OUT}= 1 V, I

_{LOAD}= 1 mA, L = 10 μH, and I

_{P}= 30 mA. As the NMOS and PMOS switches’ width decreases, the on resistance increases and the conduction losses of the switches increase. On the other hand, as the switches’ width increases, the capacitances increase and the switching losses of the NMOS and PMOS increase. Therefore, there is an optimal switch width that minimizes the total loss. The modeled total loss agrees well with the circuit simulation results and a minimum loss of 36.3 μW is achieved when the switch width is 20 mm. Figure 16 shows the PCE of the boost converter according to the width of M

_{1}and M

_{2}switches for an input voltage of 0.1 V and compares the circuit simulation results with the proposed modeling results. A maximum efficiency of 96.5% is achieved at an optimum switch width of 20 mm and the proposed model accurately predicts the optimal switch width to obtain the maximum PCE.

_{P}for an input voltage of 0.1 V and compares the circuit simulation results with the proposed modeling results when V

_{OUT}= 1 V, I

_{LOAD}= 1 mA, L = 10 μH, and W

_{M}

_{1}= W

_{M}

_{2}= 20 mm. As the peak inductor current decreases, the switching frequency increases and the switching losses of the NMOS and PMOS increase. On the other hand, as the peak inductor current increases, conduction losses in the switches and inductor increase. Therefore, there is an optimal peak inductor current that minimizes total losses. The modeled total loss agrees well with the circuit simulation results, with a minimum loss of 35.6 μW achieved at an I

_{P}of 29 mA. Figure 18 shows the PCE of the boost converter according to the peak inductor current I

_{P}for an input voltage of 0.1 V and compares the circuit simulation results with the proposed modeling results. A maximum efficiency of 96.6% is achieved at an optimum I

_{P}of 29 mA and the proposed model accurately predicts the optimal I

_{P}to obtain the maximum PCE.

_{OUT}= 1 V, I

_{LOAD}= 1 mA, and W

_{M}

_{1}= W

_{M2}= 20 mm. Based on the proposed optimal design methodology to achieve the maximum PCE, the optimal values of inductance and peak inductor current are designed differently according to the input voltage. As the input voltage increases, the optimum inductance and peak inductor current to achieve the minimum total loss increase. At an input voltage of 0.1 V, a maximum PCE of 96.5% is achieved when L is 6.8 μH and I

_{P}is 29 mA. On the other hand, at an input voltage of 0.4 V, a maximum PCE of 98.4% is achieved when L is 10 μH and I

_{P}is 33 mA. The PCE modeling results achieved from the proposed efficiency optimization design method based on loss analysis and modeling are in good agreement with circuit simulation results over a wide input voltage range. By deriving the optimal design parameters including inductance and peak inductor current for different input voltages, the maximum PCE is achieved over a wide input voltage range.

## 7. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## Abbreviations

Symbol/Notation | Description |

f_{SW} | switching frequency |

I_{P} | peak inductor current |

I_{LOAD} | load current |

L | inductance |

W_{M1} and W_{M}_{2} | width of the switches M_{1} and M_{2} |

PCE | power conversion efficiency |

P_{TOTAL} | total loss of the converter |

P_{COND,DCR} | conduction loss due to the resistance of inductor |

P_{COND,SW} | conduction loss due to the switches |

P_{SW} | switching loss of the NMOS and PMOS switches |

P_{BUFFER} | switching loss of the buffer stages |

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**Figure 1.**Block diagram of RF energy harvesting system consisting of RF energy harvesting RF-DC rectifier and DC-DC boost converter.

**Figure 5.**Modeling results of each loss component according to the width of M

_{1}and M

_{2}switches.

**Figure 12.**Waveforms of the switch control signals V

_{N}and V

_{P}, internal node voltage V

_{X}, inductor current I

_{L}, and output voltage V

_{OUT}for an input voltage of 0.1 V.

**Figure 13.**Total loss according to inductance for an input voltage of 0.1 V and comparison with the modeling results.

**Figure 14.**PCE according to inductance for an input voltage of 0.1 V and comparison with the modeling results.

**Figure 15.**Total loss according to the switch width for an input voltage of 0.1 V and comparison with the modeling results.

**Figure 16.**PCE according to switch width for an input voltage of 0.1 V and comparison with the modeling results.

**Figure 17.**Total loss according to the peak inductor current for an input voltage of 0.1 V and comparison with the modeling results.

**Figure 18.**PCE according to the peak inductor current for an input voltage of 0.1 V and comparison with the modeling results.

Reference | [18] | [19] | [20] | [23] | This Work |
---|---|---|---|---|---|

CMOS technology | 130 nm | 180 nm | 65 nm | 180 nm | 65 nm |

Output voltage | 1.1 V | 0.8–1.1 V | 1–1.1 V | 0.9–1.4 V | 1 V |

Load current | 0.22 μA | – | – | – | 0.1–1 mA |

Inductance | 10 μH | 47 μH | 10 μH | 47 μH | 6.8 μH @ 0.1 V 10 μH @ 0.4 V |

PCE @ Min. V _{IN} | 30% @ 0.05 V | 48% @ 0.02 V | 10% @ 0.04V | 60% @ 0.02 V | 96.5% @ 0.1 V |

Max. PCE @ V _{IN} | 83% @ 0.3 V | 53% @ 0.06 V | 75% @ 0.2 V | 90.8% @ 0.18 V | 98.4% @ 0.4 V |

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**MDPI and ACS Style**

Kim, J.; Kwon, I.
Design of a High-Efficiency DC-DC Boost Converter for RF Energy Harvesting IoT Sensors. *Sensors* **2022**, *22*, 10007.
https://doi.org/10.3390/s222410007

**AMA Style**

Kim J, Kwon I.
Design of a High-Efficiency DC-DC Boost Converter for RF Energy Harvesting IoT Sensors. *Sensors*. 2022; 22(24):10007.
https://doi.org/10.3390/s222410007

**Chicago/Turabian Style**

Kim, Juntae, and Ickjin Kwon.
2022. "Design of a High-Efficiency DC-DC Boost Converter for RF Energy Harvesting IoT Sensors" *Sensors* 22, no. 24: 10007.
https://doi.org/10.3390/s222410007