0.5 V, nW-Range Universal Filter Based on Multiple-Input Transconductor for Biosignals Processing

Abstract

This paper demonstrates the advantages of the multiple-input transconductor (MI-G_m) in filter application, in terms of topology simplification, increasing filter functions, and minimizing the count of needed active blocks and their consumed power. Further, the filter enjoys high input impedance, uses three MI-G_ms and two grounded capacitors, and it offers both inverting and non-inverting versions of low-pass (LPF), high-pass (HPF), band-pass (BPF), band-stop (BS) and all-pass (AP) functions. The filter operates under a supply voltage of 0.5 V and consumes 37 nW, hence it is suitable for extremely low-voltage low-power applications like biosignals processing. The circuit was designed in a Cadence environment using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). The post-layout simulation results, including Monte Carlo and process, voltage, temperature (PVT) corners for the proposed filter correlate well with the theoretical results that confirm attractive features of the developed filter based on MI-G_m.

1. Introduction

The innovations in circuit design techniques for low-voltage supply and low-power consumption for portable electronics, energy harvesting, biomedical monitoring, and autonomous sensor applications are vital [1,2,3,4]. For biosignal processing electronics, where the bio-signals spectrum lies between sub-hertz up to 10 kHz, the extremely low-voltage supply and low-power consumption of such electronics are rather beneficial since it prolongs the operating lifetime of these applications. Figure 1 shows a conceptual diagram of biosignals processing, where the biosignals with very low amplitude (in the range from µV up to mV) are sensed by actuators/sensors. Then, the sensed signals are amplified by a low-noise amplifier (preamplifier), and the unwanted noise is removed by a suitable analog filter, which is the target of this paper. Next, the digital signal processing includes an analog-to-digital converter (ADC) and a central processing unit (CPU). The resulting data are displayed or wirelessly transmitted.

The operational transconductance amplifier (OTA), also known as the transconductor (G_m stage), is a basic block for electronic applications like filters and oscillators [5,6,7,8,9,10]. Unlike the standard and well-known single-input OTA, the multiple-input OTA/transconductor (MI-OTA/MI-G_m) offers increased arithmetic operation at the input that results in a reduced number of active elements, power consumption, and simplification of the filter topology. It is worth noting that for designers in CMOS, it is a challenge to design a circuit operating with supply voltage V_DD around or even below the threshold voltage V_TH of the MOS transistor without scarifying the performance of the circuit. The use of multiple-input transconductors to reduce the number of components in the design of OTA-C filters was confirmed in the literature [5,6]. It was shown that the multiple-input OTA can reduce the number of components, silicon area, and power dissipation by approximately factor k, where k is the number of OTA inputs [5]. Multiple-input transconductor can be obtained by the following techniques: 1. using extra differential pairs [5,6], or 2. using a multiple-input floating-gate transistor (MIFG) [7,8,9,10]. While the first technique increases the count of transistors, current branches, and the complexity of the design, the second technique suffers from the high-voltage offset, incapability of processing DC signals, and becomes unsuitable for modern deep-nanoscale CMOS technology with gate leakage [11]. A promising technique that offers multiple-input OTA without the above-mentioned limitations is the multiple-input MOS transistor (MI-MOS), firstly presented and experimentally confirmed in [12,13,14]. The multiple-input MOS transistor is shown in Figure 2. The multiple-input terminals V₁, V₂, etc. can be obtained from: a. the gate while the bulk is biased by voltage V_BB, b. from the bulk while the gate is biased by V_BG, c. from the bulk-gate (known as dynamic threshold MOS transistor “DTMOS”) without biasing or d. from the bulk-gate (known as quasi-floating-gate “QFG”) with different biasing voltages V_BB and V_BG for bulk and gate, respectively [15].

The realization of the multiple-input with bulk-driven MOS device is shown in Figure 3. The multiple-input is constructed by a capacitive summing circuit using capacitors C_i (i = 1,…,N) connected to the bulk terminal of a MOS transistor. To provide proper biasing of the bulk terminal for DC operation, the high resistance resistors R_MOS is used. These R_MOS are realized as the anti-parallel connection of two minimum-size transistors M_L, operating with V_GS = 0. For AC signals, and for frequencies f >> 1/2πC_iR_MOSi, i = 1…N, resistors R_MOS are shunted by capacitances C_i, which create an analog voltage divider/voltage summing circuit, with the gain coefficients determined solely by the ratio of capacitances [15].

In this work, the multiple-input bulk-driven MOS transistor is implemented using a CMOS structure of the G_m to build a multiple-input voltage-mode analog filter. As a result, the number of used active devices is reduced while offering more filtering responses compared to conventional G_m-based filters.

2. Methods

In this section, the design of the multiple-input G_m and the universal filter based on it will be described.

2.1. The Multiple-Input G_m

The symbol and CMOS structure of the MI-G_m stage are shown in Figure 4a,b, respectively. In an ideal case, the transfer characteristic of the MI-G_m stage of Figure 4a can be expressed by:

$$I_{out}=G_m\left(V_{+1}+V_{+2}-V_{-1}-V_{-2}\right),$$

(1)

where G_m is the transconductance gain, V₊₁ and V₊₂ are signals at the non-inverting inputs, V₋₁, V₋₂ are signals at the inverting inputs, and I_out is the output current.

The particular realization of the MI-G_m stage discussed here was first presented and experimentally verified in [15]. The circuit employs the MI-bulk-driven differential pair M₁, M₂, with the source-degenerative bulk-driven transistors M₁₁, M₁₂, which operate in the triode region and improve the circuit linearity. Note, that V_GS as well as V_BS voltages for M₁₁, M₁₂ and M₁, M₂ are identical for any common-mode input voltage and biasing current. The single-input gate-driven counterpart of the input stage was first proposed in [16], and its weak-inversion version was discussed in [17]. Here, due to the use of bulk-driven transistors, and an additional capacitive voltage divider, both, the input linear range, as well as the input common-mode range are significantly increased, as compared with the conventional gate-driven (GD) version operating in a weak-inversion region. Moreover, the application of MI transistors allows realizing MI-G_ms without multiplying the input differential pair, as in classical solutions, which saves power and simplifies the overall structure of such circuits.

Regarding the rest of the structure, the circuit can be seen as a classical current-mirror OTA, where all current mirrors are realized with the use of self-cascode transistors. This improves their output resistances, and consequently, also the DC voltage gain of the proposed OTA, with negligible limitation of the output voltage swing. Note, that the current gain of all current mirrors in this design was assumed to be equal to unity.

Assuming that a p-MOS transistor is operating in a weak-inversion region, the drain current can be described by the following equation, [18]:

$$I_D=I_T\left(\frac{W}{L}\right)exp\left(\frac{V_{SG}+V_{TH}}{n_p{U}_T}\right)\left[1-exp\left(-\frac{V_{SD}}{U_T}\right)\right]$$

(2)

where I_T is the technology current, W and L are the transistor channel width and length, respectively, n_p is the subthreshold slope factor, U_T is the thermal potential and V_TH is the threshold voltage, which can be linearly approximated as:

$$V_{TH}=V_{TO}-\left(n_p-1\right)V_{BS }$$

(3)

where V_TO is the threshold voltage for V_BS = 0.

Assuming that the circuit is controlled with i-th differential input, with other inputs grounded for AC signals, the low-frequency large-signal transfer characteristic of the G_m can be expressed as:

$$I_{out}=2I_{set}tanh\left({\beta }_i\eta \frac{V_{+i}-V_{-i}}{2n_p{U}_T}-tan{h}^{-1}\left[\frac{1}{4m+1}tanh\left({\beta }_i\eta \frac{V_{V_{+i}-V_{-i}}}{2n_p{U}_T}\right)\right]\right)$$

(4)

where η = (n_p − 1)=g_mb1,2/g_m1,2 at the operating point, m= (W₁₁/L₁₂)⁄(W₁/L₁) is the relative aspect ratio of the two matched transistor pairs M₁₁–M₁₂ and M₁–M_2. β_i is the voltage gain of the input capacitive divider from one input, which neglects the second order effects and for f >> 1/C_iR_MOSi can be approximated as:

$${\beta }_i\cong \frac{C_i}{{\sum }_{i=1}^n{C}_i}$$

(5)

where n is the total number of differential inputs (in the discussed design n = 2).

For optimum linearity, the coefficient m should be equal to 0.5, as for the GD counterpart, of the discussed circuit. This value does not depend on the biasing voltage I_set [17].

As it can be concluded from Equation (4), as compared to its single-input GD counterpart, the linear range of the proposed circuit is extended by a factor of 1⁄β_iη, which for the discussed case (β_i = 0.5, η = 0.34) means that the linear range is extended around 6 times.

The small-signal transconductance of the G_m can be calculated from Equation (4) as:

$$G_m={\beta }_i\eta ·\frac{4m}{4m+1}·\frac{I_{set}}{n_p{U}_T}$$

(6)

thus, the small-signal transconductance is equal to the gate transconductance of the input transistors M₁ and M₂, multiplied by a factor of [4m⁄(4m + 1)] β_iη, which for the proposed design in the optimal case (m = 0.5) is equal to around 1⁄9.

The low-frequency voltage gain of the G_m can be approximated as:

$$A_{VO}\cong G_m[\left(g_{m9}{r}_{dsD9}{r}_{ds9c}\right)||\left(g_{m6}{r}_{ds6}{r}_{ds6c}\right)]$$

(7)

Its value is negatively affected by the low transconductance of the MI-G_m. On the other hand, however, self-cascode connections allow for enlarging the output resistance of the MI-G_m, thus improving its voltage gain and at least partially compensating the losses caused by the input capacitive divider and the small bulk transconductance of MOS transistors.

Assuming that the noise current of an i-th MOS transistor in a weak inversion region can be expressed as:

$$\overline{I_{ni}^2}=2q{I}_{Di}+\frac{1}{f{C}_{OX}}\left(\frac{K{g}_{mi}^2}{W_i{L}_i}\right)$$

(8)

where q is the electron charge, C_OX is the oxide capacitance per unit area and K is the flicker noise constant, the input-referred noise of the MI-G_m, referred to as one of the differential inputs, is given by:

$$\begin{gathered} \overline{v_n^2}=\frac{1}{G_m^2}\left[2\overline{I_{n1,2}^2}{\left(\frac{2G}{g_{m1,2}+2G}\right)}^2+2\overline{I_{n7,8SC}^2}{\left(\frac{g_{m1,2}}{g_{m1,2}+2G}\right)}^2 \\ ++\overline{I_{nG}^2}{\left(2\frac{g_{m1,2}}{g_{m1,2}+2G}\right)}^2+4\overline{I_{n3-6SC}^2}+2\overline{I_{n9,10SC}^2}\right] \end{gathered}$$

(9)

where G = 1⁄(r_ds11||r_ds12) at the operating point.

As it can be concluded from Equation (9), the input-referred noise of the MI-G_m is increased, as compared to its single-input GD counterpart, due to the lower transconductance G_m. However, the input noise is increased in the same proportion as the input linear range, therefore, the dynamic range will not be affected and remains the same in both realizations.

2.2. Universal Filter Design

The voltage-mode analog filter is a commonly used analog signal processing block, that is well-known for a long time. This is due to the versatility of operational amplifiers that are commonly used in the synthesis of analog electronic circuits [19]. Over the last decades, some other active elements such as operational transconductance amplifiers (OTAs), second-generation current conveyors (CCIIs), and current feedback operational amplifiers (CFOAs) have received considerable attention for designing voltage- and current-mode analog filters [20,21,22,23,24,25,26,27,28]. To design voltage-mode filters, multiple-input type filters can reduce the number of active devices compared with single-input type filters, because variant filtering responses can be obtained by appropriately applying the input signal, depending on the conditions of the required filtering responses. To avoid loading effects, the input terminals of the voltage-mode filter must have high impedance. To avoid additional circuits such as inverting amplifiers, the minus-type input signal of voltage-mode filters must be available.

For the purpose of illustration, Figure 5a shows a universal filter design using five standard G_m blocks, and two grounded capacitors and it offers five standard filtering functions [26]. In this work, a multiple-input voltage-mode analog filter using multiple-input transconductors MI-G_m is proposed as shown in Figure 5b. The structure will show that the multiple-input G_m-based filter can reduce the number of used active devices and can offer more filtering responses compared with conventional G_m-based filters. The filter employs three multiple-input G_m stages and two grounded capacitors, which is desirable in integrated solutions. Thanks to the MI-G_m elements that offer noninverting/inverting multiple-input terminals, noninverting/inverting transfer functions of five types of filtering responses, namely, low-pass, high-pass, band-pass, band-stop, and all-pass can be easily obtained. Moreover, the input signals are connected to the high-impedance inputs of MI-G_m, hence the additional buffer circuits to avoid the loading effects are not required. It is worth noting that although both filters in Figure 5a,b offer the five standard filtering functions, the count of active elements is reduced from 5 to 3 thanks to the MI-G_m. This results in power consumption reduction and filter topology simplification, and in offering more transfer functions (including both non-inverting and inverting versions of five standard filtering functions).

Using Equation (1) and nodal analysis, the output voltages of Figure 5b are given by

$$V_{o1}=\frac{\left(s{C}_2{G}_{m1}+G_{m1}{G}_{m2}\right)\left(V_{in1}-V_{in2}\right)+G_{m1}{G}_{m2}\left(V_{in4}-V_{in3}+V_{in5}-V_{in6}\right)}{s^2{C}_1{C}_2+s{C}_1{G}_{m2}+G_{m1}{G}_{m2}}$$

(10)

$$V_{o2}=\frac{G_{m1}{G}_{m2}\left(V_{in1}-V_{in2}\right)+C_1{G}_{m2}\left(V_{in3}-V_{in4}+V_{in6}-V_{in5}\right)}{s^2{C}_1{C}_2+s{C}_1{G}_{m2}+G_{m1}{G}_{m2}}$$

(11)

$$V_{o3}=\frac{G_{m1}{G}_{m2}\left(V_{in1}-V_{in2}\right)+C_1{G}_{m2}\left(V_{in3}-V_{in4}\right)+(s^2{C}_2{C}_2+G_{m1}{G}_{m2})\left(V_{in5}-V_{in6}\right)}{s^2{C}_1{C}_2+s{C}_1{G}_{m2}+G_{m1}{G}_{m2}}$$

(12)

The conditions for obtaining variant filtering responses by the appropriate connection of input signals are shown in

Table 1. Variant filtering functions of the universal filter.

Filtering Function		Input	Output
LP	Non-inverting	$$\begin{gathered} V_{in4} \\ {V}_{in5} \\ {V}_{in1} \\ {V}_{in1} \end{gathered}$$	$$\begin{gathered} V_{o1} \\ {V}_{o1} \\ {V}_{o2} \\ {V}_{o3} \end{gathered}$$
	Inverting	$$\begin{gathered} V_{in3} \\ {V}_{in6} \\ {V}_{in1} \\ {V}_{in2} \end{gathered}$$	$$\begin{gathered} V_{o1} \\ {V}_{o1} \\ {V}_{o2} \\ {V}_{o3} \end{gathered}$$
BP	Non-inverting	$V_{in1}$ and $V_{in6}$ $$\begin{gathered} V_{in3} \\ {V}_{in6} \\ {V}_{in3} \end{gathered}$$	$$\begin{gathered} V_{o1} \\ {V}_{o2} \\ {V}_{o2} \\ {V}_{o3} \end{gathered}$$
	Inverting	$V_{in2}$ and $V_{in5}$ $$\begin{gathered} V_{in4} \\ {V}_{in5} \\ {V}_{in4} \end{gathered}$$	$$\begin{gathered} V_{o1} \\ {V}_{o2} \\ {V}_{o2} \\ {V}_{o3} \end{gathered}$$
HP	Non-inverting	$V_{in5}\mathrm{and}{V}_{in2}$	$V_{o3}$
	Inverting	$V_{in6}\mathrm{and}{V}_{in1}$	$V_{o2}$
BS	Non-inverting	$V_{in5}$	$V_{o3}$
	Inverting	$V_{in6}$	$V_{o3}$
AP	Non-inverting	$V_{in5}\mathrm{and}{V}_{in4}$	$V_{o3}$
	Inverting	$V_{in5}\mathrm{and}{V}_{in3}$	$V_{o3}$

Note: the unused inputs should be grounded.

.

The natural frequency (ω_o) and the quality factor (Q) are given by:

$${\omega }_o=\sqrt{\frac{G_{m1}{G}_{m2}}{C_1{C}_2}}$$

(13)

$$Q=\sqrt{\frac{C_2{G}_{m1}}{C_1{G}_{m2}}}$$

(14)

It is apparent that the parameter ω_o can be controlled electronically by G_m1 = G_m2 while the parameter Q is controllable orthogonally by the ratio of C₂/C₁.

Taking into account the non-idealities of MI-G_m, there are three major non-idealities that should be considered [29]: (i) the frequency-dependent transconductance, (ii) the input parasitic resistances and capacitances, (iii) the output parasitic resistances and capacitances.

Figure 6 shows the non-ideal model with parasitic elements of the MI-G_m, where R₊, R₋, C₊, C₋ are the input parasitic resistances and capacitances, and R_o, C_o is the output parasitic resistance and capacitance, respectively. Considering Figure 5b the parasitic resistances at nodes V_o1 and V_o2 are, respectively, R_o1//R₊₁ and R_o2//R₊₃, thus the value of these parallel resistances is very high and can be neglected. Consider the parasitic capacitances at nodes V_o1 and V_o2, they can be expressed respectively as $C_1^{\prime }=C_1+C_{o1}+C_{+2}$ and $C_2^{\prime }=C_2+C_{o2}+C_{-1}+C_{+3}$.

Considering the non-ideality of transconductance, the output current can be rewritten as

$$I_{out}=G_{mnj}\left(V_{+1}+V_{+2}-V_{-1}-V_{-2}\right),$$

(15)

where G_mnj is the non-ideal transconductance gain of the j-th MI-G_m that is frequency-dependent, and can be approximately given by [29,30]:

$$G_{mnj}\left(s\right)\cong G_{mj}\left(1-T_{j}s\right)$$

(16)

From Figure 5 and Equation (16), denominators of Equations (10)−(12) can be expressed by:

$$\begin{gathered} s^2{C}_1^{\prime }{C}_2^{\prime }\left(1-\frac{C_1{G}_{m2}{T}_2-G_{m1}{G}_{m2}{T}_1{T}_2}{C_1{C}_2}\right)+s{C}_1^{\prime }{G}_{m2}\left(1-\frac{G_{m1}{G}_{m2}{T}_1+G_{m1}{G}_{m2}{T}_2}{C_1^{\prime }{G}_{m2}}\right) \\ +G_{m1}{G}_{m2} \end{gathered}$$

(17)

The non-idealities of the transconductance $G_{mnj}$ can be neglected, if the following condition is satisfied:

$$\frac{C_1^{\prime }{G}_{m2}{T}_2-G_{m1}{G}_{m2}{T}_1{T}_2}{C_1^{\prime }{C}_2^{\prime }}\ll 1$$

(18)

$$\frac{G_{m1}{G}_{m2}{T}_1+G_{m1}{G}_{m2}{T}_2}{C_1^{\prime }{G}_{m2}}\ll 1$$

(19)

In such a case, the parameters ω_o and Q become as follows:

$${\omega }_o=\sqrt{\frac{G_{m1}{G}_{m2}}{C_1^{\prime }{C}_2^{\prime }}}$$

(20)

$$Q=\sqrt{\frac{C_2^{\prime }{G}_{m1}}{C_1^{\prime }{G}_{m2}}}$$

(21)

The parasitic capacitances will decrease the value of ω_o as compared to the ideal case.

3. Results and Discussion

The filter circuit was designed in a Cadence environment using 180 nm TSMC CMOS technology. The voltage supply was 0.5 V, and the power consumption of the filter was 37 nW. The MI-G_m stage first presented in [15] was used. The transistor aspect ratios W/L are presented in

Table 2. Transistor Aspect Ratio of the G_m.

Device Name	W/L (µm⁄µm)
M1, M2, M7–M10, M13	2 × 15/1
M3–M6	2 × 10/1
M3c–M6c	10/1
M7c–M10c, M13c, M11, M12	15/1
ML	5/4

. The input metal-insulator-metal (MIM) capacitor C_i with a capacitance value of 0.5 pF was used. The layout of the MI-G_m is shown in Figure 7, with a silicon area of 116.3 µm × 99.2 µm.

The DC transfer characteristics of the used MI-G_m for I_set = [2, 5, 10, 15, 20, 25] nA are shown in Figure 8. The enhanced linearity in the V_in range of ±500 mV is clearly observable.

For the filter application, the simulated frequency responses of the proposed filter are shown in Figure 9. The values of C₁ = C₂ = 15 pF and the setting current I_set = 5 nA. The simulated cut-off frequency value of 153 Hz is very close to the calculated value of 154.9 Hz. The power consumption of the filter was 37 nW.

Figure 10 shows the tuning capability of the LPF (a), HPF (b), BPF (c), and BSF (d) with C₁ = C₂ = 15 pF. The setting current was I_set = 2 nA, 5 nA, 10nA, and 20 nA and the cut-off frequency values were 62.3 Hz, 153 Hz, 301.9 Hz, and 595.6 Hz, respectively. Results shown in Figure 10 confirm the wide tuning capability of the proposed filter for low-frequency biomedical applications.

The Monte Carlo process and mismatch analysis was performed with 200 runs. Figure 11 shows the simulated results for the LPF and BPF. The low-frequency gain at 1 Hz of the LPF was in the range from −1.39 dB to 0.47 dB, and the gain of the BPF at a frequency of 153 Hz was in the range from −0.438 dB to 0.168 dB.

Figure 12 shows the simulation results of the LPF and BPF with the process, voltage, and temperature variations. The process corners were fast-fast, fast-slow, slow-fast, and slow-slow, the voltage supply corners were in the range of V_DD ± 10%, and the temperature corners were 0 °C and 70 °C.

Figure 13 shows the transient response of the LPF with an applied input signal of 100mV_pp @ 50Hz and its output spectrum. The total harmonic distortion (THD) of 0.33% was achieved, which was kept still below 1% for the input signal of 200 mV_pp @ 50 Hz. The output integrated noise of the LPF was 220 µV_rms which resulted in a 50 dB dynamic range (DR = 20 × log (V_rms-max/V_rms-onoise)) of the filter with 1% THD.

Table 3. Comparison with other filters.

	This Work	[26]	[27]	[28]
Technology (nm)	180	commercial IC	180	180
VDD (V)	0.5	±15	1.2	±0.3
Power consumption (nW)	37	860 × 106	0.96 × 106	5770
DR (dB)	50			53.2
Fter function	22 (VM)	13 (VM)	22(VM)	20 (MM)
Offer inverting and non-inverting of five standard responses	Yes	No	Yes	No
Natural frequency (kHz)	0.153	217	1	5
Number of active and passive element	3-OTA, 2-C	5-OTA, 2-C	4-OTA, 2-C	8-OTA, 2-C
Total harmonic distortion (%)	0.33@100 mVpp	1.93@200 mVpp	1.67@600 mVpp	<2@200 mVpp
$FOM=\frac{P_{diss}}{f_o\times N\times DR}$	2.41 × 10−12	-	78.6	1.26 × 10−12

where $P_{diss}$ is the power dissipation, $f_o$ is the center frequency, $N$ is the order of filter, and $DR$ is the dynamic range.

shows a comparison of the proposed filter with the others [26,27,28]. It is evident that the proposed filter offers the largest amount of filtering functions with a minimum count of active elements, and the lowest voltage supply, and is the only one with nanopower consumption. All these facts confirm the usability of the multiple-input G_m stage in filter applications mainly by means of reducing the count of active blocks and power consumption. The figure of merit (FoM) is also presented, where a lower FoM implies the better performance of the filter.

4. Conclusions

This paper demonstrates the advantages of the MI-G_m in filter application, in terms of topology simplification, increasing filter functions, and minimizing the count of the needed active blocks and their power consumption. Therefore, the developed circuit is a good candidate for extremely low-power low-voltage applications like biosignals processing. The filter application offers the largest amount of filtering functions with a minimum count of active elements. The post-layout simulations prove the presented advantages of MI-G_m.