0.5 V, nW-Range Universal Filter Based on Multiple-Input Transconductor for Biosignals Processing

This paper demonstrates the advantages of the multiple-input transconductor (MI-Gm) in filter application, in terms of topology simplification, increasing filter functions, and minimizing the count of needed active blocks and their consumed power. Further, the filter enjoys high input impedance, uses three MI-Gms and two grounded capacitors, and it offers both inverting and non-inverting versions of low-pass (LPF), high-pass (HPF), band-pass (BPF), band-stop (BS) and all-pass (AP) functions. The filter operates under a supply voltage of 0.5 V and consumes 37 nW, hence it is suitable for extremely low-voltage low-power applications like biosignals processing. The circuit was designed in a Cadence environment using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). The post-layout simulation results, including Monte Carlo and process, voltage, temperature (PVT) corners for the proposed filter correlate well with the theoretical results that confirm attractive features of the developed filter based on MI-Gm.


Introduction
The innovations in circuit design techniques for low-voltage supply and low-power consumption for portable electronics, energy harvesting, biomedical monitoring, and autonomous sensor applications are vital [1][2][3][4]. For biosignal processing electronics, where the bio-signals spectrum lies between sub-hertz up to 10 kHz, the extremely low-voltage supply and low-power consumption of such electronics are rather beneficial since it prolongs the operating lifetime of these applications. Figure 1 shows a conceptual diagram of biosignals processing, where the biosignals with very low amplitude (in the range from µV up to mV) are sensed by actuators/sensors. Then, the sensed signals are amplified by a low-noise amplifier (preamplifier), and the unwanted noise is removed by a suitable analog filter, which is the target of this paper. Next, the digital signal processing includes an analog-to-digital converter (ADC) and a central processing unit (CPU). The resulting data are displayed or wirelessly transmitted.
The operational transconductance amplifier (OTA), also known as the transconductor (G m stage), is a basic block for electronic applications like filters and oscillators [5][6][7][8][9][10]. Unlike the standard and well-known single-input OTA, the multiple-input OTA/transconductor (MI-OTA/MI-G m ) offers increased arithmetic operation at the input that results in a reduced number of active elements, power consumption, and simplification of the filter The operational transconductance amplifier (OTA), also known as the transconductor (Gm stage), is a basic block for electronic applications like filters and oscillators [5][6][7][8][9][10]. Unlike the standard and well-known single-input OTA, the multiple-input OTA/transconductor (MI-OTA/MI-Gm) offers increased arithmetic operation at the input that results in a reduced number of active elements, power consumption, and simplification of the filter topology. It is worth noting that for designers in CMOS, it is a challenge to design a circuit operating with supply voltage VDD around or even below the threshold voltage VTH of the MOS transistor without scarifying the performance of the circuit. The use of multiple-input transconductors to reduce the number of components in the design of OTA-C filters was confirmed in the literature [5,6]. It was shown that the multiple-input OTA can reduce the number of components, silicon area, and power dissipation by approximately factor k, where k is the number of OTA inputs [5]. Multiple-input transconductor can be obtained by the following techniques: 1. using extra differential pairs [5,6], or 2. using a multiple-input floating-gate transistor (MIFG) [7][8][9][10]. While the first technique increases the count of transistors, current branches, and the complexity of the design, the second technique suffers from the high-voltage offset, incapability of processing DC signals, and becomes unsuitable for modern deep-nanoscale CMOS technology with gate leakage [11]. A promising technique that offers multiple-input OTA without the above-mentioned limitations is the multiple-input MOS transistor (MI-MOS), firstly presented and experimentally confirmed in [12][13][14]. The multiple-input MOS transistor is shown in Figure 2. The multiple-input terminals V1, V2, etc. can be obtained from: a. the gate while the bulk is biased by voltage VBB, b. from the bulk while the gate is biased by VBG, c. from the bulkgate (known as dynamic threshold MOS transistor "DTMOS") without biasing or d) from the bulk-gate (known as quasi-floating-gate "QFG") with different biasing voltages VBB and VBG for bulk and gate, respectively [15].  The operational transconductance amplifier (OTA), also known as the transconductor (Gm stage), is a basic block for electronic applications like filters and oscillators [5][6][7][8][9][10]. Unlike the standard and well-known single-input OTA, the multiple-input OTA/transconductor (MI-OTA/MI-Gm) offers increased arithmetic operation at the input that results in a reduced number of active elements, power consumption, and simplification of the filter topology. It is worth noting that for designers in CMOS, it is a challenge to design a circuit operating with supply voltage VDD around or even below the threshold voltage VTH of the MOS transistor without scarifying the performance of the circuit. The use of multiple-input transconductors to reduce the number of components in the design of OTA-C filters was confirmed in the literature [5,6]. It was shown that the multiple-input OTA can reduce the number of components, silicon area, and power dissipation by approximately factor k, where k is the number of OTA inputs [5]. Multiple-input transconductor can be obtained by the following techniques: 1. using extra differential pairs [5,6], or 2. using a multiple-input floating-gate transistor (MIFG) [7][8][9][10]. While the first technique increases the count of transistors, current branches, and the complexity of the design, the second technique suffers from the high-voltage offset, incapability of processing DC signals, and becomes unsuitable for modern deep-nanoscale CMOS technology with gate leakage [11]. A promising technique that offers multiple-input OTA without the above-mentioned limitations is the multiple-input MOS transistor (MI-MOS), firstly presented and experimentally confirmed in [12][13][14]. The multiple-input MOS transistor is shown in Figure 2. The multiple-input terminals V1, V2, etc. can be obtained from: a. the gate while the bulk is biased by voltage VBB, b. from the bulk while the gate is biased by VBG, c. from the bulkgate (known as dynamic threshold MOS transistor "DTMOS") without biasing or d) from the bulk-gate (known as quasi-floating-gate "QFG") with different biasing voltages VBB and VBG for bulk and gate, respectively [15]. The realization of the multiple-input with bulk-driven MOS device is shown in Figure 3. The multiple-input is constructed by a capacitive summing circuit using capacitors Ci (i = 1,…,N) connected to the bulk terminal of a MOS transistor. To provide proper biasing of the bulk terminal for DC operation, the high resistance resistors RMOS is used. These RMOS are realized as the anti-parallel connection of two minimum-size transistors ML, operating with VGS = 0. For AC signals, and for frequencies f >> 1/2πCiRMOSi, i = 1…N, resistors RMOS are shunted by capacitances Ci, which create an analog voltage divider/voltage summing circuit, with the gain coefficients determined solely by the ratio of capacitances [15]. The realization of the multiple-input with bulk-driven MOS device is shown in Figure 3. The multiple-input is constructed by a capacitive summing circuit using capacitors C i (i = 1, . . . ,N) connected to the bulk terminal of a MOS transistor. To provide proper biasing of the bulk terminal for DC operation, the high resistance resistors R MOS is used. These R MOS are realized as the anti-parallel connection of two minimum-size transistors M L , operating with V GS = 0. For AC signals, and for frequencies f >> 1/2πC i R MOSi , i = 1 . . . N, resistors R MOS are shunted by capacitances C i , which create an analog voltage divider/voltage summing circuit, with the gain coefficients determined solely by the ratio of capacitances [15].
In this work, the multiple-input bulk-driven MOS transistor is implemented using a CMOS structure of the G m to build a multiple-input voltage-mode analog filter. As a result, the number of used active devices is reduced while offering more filtering responses compared to conventional G m -based filters.  In this work, the multiple-input bulk-driven MOS transistor is implemented using a CMOS structure of the Gm to build a multiple-input voltage-mode analog filter. As a result, the number of used active devices is reduced while offering more filtering responses compared to conventional Gm-based filters.

Methods
In this section, the design of the multiple-input Gm and the universal filter based on it will be described.

The Multiple-Input Gm
The symbol and CMOS structure of the MI-Gm stage are shown in Figure 4a,b, respectively. In an ideal case, the transfer characteristic of the MI-Gm stage of Figure 4a can be expressed by: where Gm is the transconductance gain, V+1 and V+2 are signals at the non-inverting inputs, V−1, V−2 are signals at the inverting inputs, and Iout is the output current.  The particular realization of the MI-Gm stage discussed here was first presented and experimentally verified in [15]. The circuit employs the MI-bulk-driven differential pair M1, M2, with the source-degenerative bulk-driven transistors M11, M12, which operate in the triode region and improve the circuit linearity. Note, that VGS as well as VBS voltages for M11, M12 and M1, M2 are identical for any common-mode input voltage and biasing current. The single-input gate-driven counterpart of the input stage was first proposed in [16], and its weak-inversion version was discussed in [17]. Here, due to the use of bulkdriven transistors, and an additional capacitive voltage divider, both, the input linear range, as well as the input common-mode range are significantly increased, as compared with the conventional gate-driven (GD) version operating in a weak-inversion region. Moreover, the application of MI transistors allows realizing MI-Gms without multiplying

Methods
In this section, the design of the multiple-input G m and the universal filter based on it will be described.

The Multiple-Input G m
The symbol and CMOS structure of the MI-G m stage are shown in Figure 4a,b, respectively. In an ideal case, the transfer characteristic of the MI-G m stage of Figure 4a can be expressed by: where G m is the transconductance gain, V +1 and V +2 are signals at the non-inverting inputs, V −1 , V −2 are signals at the inverting inputs, and I out is the output current. In this work, the multiple-input bulk-driven MOS transistor is implemented using a CMOS structure of the Gm to build a multiple-input voltage-mode analog filter. As a result, the number of used active devices is reduced while offering more filtering responses compared to conventional Gm-based filters.

Methods
In this section, the design of the multiple-input Gm and the universal filter based on it will be described.

The Multiple-Input Gm
The symbol and CMOS structure of the MI-Gm stage are shown in Figure 4a,b, respectively. In an ideal case, the transfer characteristic of the MI-Gm stage of Figure 4a can be expressed by: where Gm is the transconductance gain, V+1 and V+2 are signals at the non-inverting inputs, V−1, V−2 are signals at the inverting inputs, and Iout is the output current.  The particular realization of the MI-Gm stage discussed here was first presented and experimentally verified in [15]. The circuit employs the MI-bulk-driven differential pair M1, M2, with the source-degenerative bulk-driven transistors M11, M12, which operate in the triode region and improve the circuit linearity. Note, that VGS as well as VBS voltages for M11, M12 and M1, M2 are identical for any common-mode input voltage and biasing current. The single-input gate-driven counterpart of the input stage was first proposed in [16], and its weak-inversion version was discussed in [17]. Here, due to the use of bulkdriven transistors, and an additional capacitive voltage divider, both, the input linear range, as well as the input common-mode range are significantly increased, as compared with the conventional gate-driven (GD) version operating in a weak-inversion region. Moreover, the application of MI transistors allows realizing MI-Gms without multiplying The particular realization of the MI-G m stage discussed here was first presented and experimentally verified in [15]. The circuit employs the MI-bulk-driven differential pair M 1 , M 2 , with the source-degenerative bulk-driven transistors M 11 , M 12 , which operate in the triode region and improve the circuit linearity. Note, that V GS as well as V BS voltages for M 11 , M 12 and M 1 , M 2 are identical for any common-mode input voltage and biasing current. The single-input gate-driven counterpart of the input stage was first proposed in [16], and its weak-inversion version was discussed in [17]. Here, due to the use of bulk-driven transistors, and an additional capacitive voltage divider, both, the input linear range, as well as the input common-mode range are significantly increased, as compared with the conventional gate-driven (GD) version operating in a weak-inversion region. Moreover, the application of MI transistors allows realizing MI-G m s without multiplying the input differential pair, as in classical solutions, which saves power and simplifies the overall structure of such circuits.
Regarding the rest of the structure, the circuit can be seen as a classical current-mirror OTA, where all current mirrors are realized with the use of self-cascode transistors. This improves their output resistances, and consequently, also the DC voltage gain of the proposed OTA, with negligible limitation of the output voltage swing. Note, that the current gain of all current mirrors in this design was assumed to be equal to unity. Assuming that a p-MOS transistor is operating in a weak-inversion region, the drain current can be described by the following equation, [18]: where I T is the technology current, W and L are the transistor channel width and length, respectively, n p is the subthreshold slope factor, U T is the thermal potential and V TH is the threshold voltage, which can be linearly approximated as: where V TO is the threshold voltage for V BS = 0.
Assuming that the circuit is controlled with i-th differential input, with other inputs grounded for AC signals, the low-frequency large-signal transfer characteristic of the G m can be expressed as: where η = (n p − 1)=g mb1,2 /g m1,2 at the operating point, m= (W 11 /L 12 )⁄(W 1 /L 1 ) is the relative aspect ratio of the two matched transistor pairs M 11 -M 12 and M 1 -M 2. β i is the voltage gain of the input capacitive divider from one input, which neglects the second order effects and for f >> 1/C i R MOSi can be approximated as: where n is the total number of differential inputs (in the discussed design n = 2). For optimum linearity, the coefficient m should be equal to 0.5, as for the GD counterpart, of the discussed circuit. This value does not depend on the biasing voltage I set [17].
As it can be concluded from (4), as compared to its single-input GD counterpart, the linear range of the proposed circuit is extended by a factor of 1⁄β i η, which for the discussed case (β i = 0.5, η = 0.34) means that the linear range is extended around 6 times.
The small-signal transconductance of the G m can be calculated from (4) as: thus, the small-signal transconductance is equal to the gate transconductance of the input transistors M 1 and M 2 , multiplied by a factor of [4m⁄(4m + 1)] β i η, which for the proposed design in the optimal case (m = 0.5) is equal to around 1⁄9. The low-frequency voltage gain of the G m can be approximated as: Its value is negatively affected by the low transconductance of the MI-G m . On the other hand, however, self-cascode connections allow for enlarging the output resistance of the MI-G m , thus improving its voltage gain and at least partially compensating the losses caused by the input capacitive divider and the small bulk transconductance of MOS transistors.
Assuming that the noise current of an i-th MOS transistor in a weak inversion region can be expressed as: where q is the electron charge, C OX is the oxide capacitance per unit area and K is the flicker noise constant, the input-referred noise of the MI-G m , referred to as one of the differential inputs, is given by: where G = 1⁄(r ds11 ||r ds12 ) at the operating point.
As it can be concluded from (9), the input-referred noise of the MI-G m is increased, as compared to its single-input GD counterpart, due to the lower transconductance G m . However, the input noise is increased in the same proportion as the input linear range, therefore, the dynamic range will not be affected and remains the same in both realizations.

Universal Filter Design
The voltage-mode analog filter is a commonly used analog signal processing block, that is well-known for a long time. This is due to the versatility of operational amplifiers that are commonly used in the synthesis of analog electronic circuits [19]. Over the last decades, some other active elements such as operational transconductance amplifiers (OTAs), secondgeneration current conveyors (CCIIs), and current feedback operational amplifiers (CFOAs) have received considerable attention for designing voltage-and current-mode analog filters [20][21][22][23][24][25][26][27][28]. To design voltage-mode filters, multiple-input type filters can reduce the number of active devices compared with single-input type filters, because variant filtering responses can be obtained by appropriately applying the input signal, depending on the conditions of the required filtering responses. To avoid loading effects, the input terminals of the voltage-mode filter must have high impedance. To avoid additional circuits such as inverting amplifiers, the minus-type input signal of voltage-mode filters must be available.
For the purpose of illustration, Figure 5a shows a universal filter design using five standard G m blocks, and two grounded capacitors and it offers five standard filtering functions [26]. In this work, a multiple-input voltage-mode analog filter using multiple-input transconductors MI-G m is proposed as shown in Figure 5b. The structure will show that the multiple-input G m -based filter can reduce the number of used active devices and can offer more filtering responses compared with conventional G m -based filters. The filter employs three multiple-input G m stages and two grounded capacitors, which is desirable in integrated solutions. Thanks to the MI-G m elements that offer noninverting/inverting multiple-input terminals, noninverting/inverting transfer functions of five types of filtering responses, namely, low-pass, high-pass, band-pass, band-stop, and all-pass can be easily obtained. Moreover, the input signals are connected to the high-impedance inputs of MI-G m , hence the additional buffer circuits to avoid the loading effects are not required. It is worth noting that although both filters in Figure 5a,b offer the five standard filtering functions, the count of active elements is reduced from 5 to 3 thanks to the MI-G m . This results in power consumption reduction and filter topology simplification, and in offering more transfer functions (including both non-inverting and inverting versions of five standard filtering functions).
Using (1) and nodal analysis, the output voltages of Figure 5b are given by Using (1) and nodal analysis, the output voltages of Figure 5b are given by The conditions for obtaining variant filtering responses by the appropriate connection of input signals are shown in Table 1.
The natural frequency (ωo) and the quality factor (Q) are given by: The conditions for obtaining variant filtering responses by the appropriate connection of input signals are shown in Table 1.

Filtering Function
Input Output Note: the unused inputs should be grounded.
The natural frequency (ω o ) and the quality factor (Q) are given by: It is apparent that the parameter ω o can be controlled electronically by G m1 = G m2 while the parameter Q is controllable orthogonally by the ratio of C 2 /C 1 .
Taking into account the non-idealities of MI-G m , there are three major non-idealities that should be considered [29]: (i) the frequency-dependent transconductance, (ii) the input parasitic resistances and capacitances, (iii) the output parasitic resistances and capacitances. Figure 6 shows the non-ideal model with parasitic elements of the MI-G m , where R + , R − , C + , C − are the input parasitic resistances and capacitances, and R o , C o is the output parasitic resistance and capacitance, respectively. Considering Figure 5b the parasitic resistances at nodes V o1 and V o2 are, respectively, R o1 //R +1 and R o2 //R +3 , thus the value of these parallel resistances is very high and can be neglected. Consider the parasitic capacitances at nodes V o1 and V o2 , they can be expressed respectively as Taking into account the non-idealities of MI-Gm, there are three major non-idealities that should be considered [29]: (i) the frequency-dependent transconductance, (ii) the input parasitic resistances and capacitances, (iii) the output parasitic resistances and capacitances. Figure 6 shows the non-ideal model with parasitic elements of the MI-Gm, where R+, R−, C+, C− are the input parasitic resistances and capacitances, and Ro, Co is the output parasitic resistance and capacitance, respectively. Considering Figure 5b the parasitic resistances at nodes Vo1 and Vo2 are, respectively, Ro1//R+1 and Ro2//R+3, thus the value of these parallel resistances is very high and can be neglected. Consider the parasitic capacitances at nodes Vo1 and Vo2, they can be expressed respectively as = + + and = + + + . Figure 6. Non-ideal MI-Gm model with parasitic elements. Figure 6. Non-ideal MI-G m model with parasitic elements.
Considering the non-ideality of transconductance, the output current can be rewritten as where G mnj is the non-ideal transconductance gain of the j-th MI-G m that is frequencydependent, and can be approximately given by [29,30]: From Figure 5 and (16), denominators of (10)−(12) can be expressed by: The non-idealities of the transconductance G mnj can be neglected, if the following condition is satisfied: In such a case, the parameters ω o and Q become as follows: The parasitic capacitances will decrease the value of ω o as compared to the ideal case.

Results and Discussion
The filter circuit was designed in a Cadence environment using 180 nm TSMC CMOS technology. The voltage supply was 0.5 V, and the power consumption of the filter was 37 nW. The MI-G m stage first presented in [15] was used. The transistor aspect ratios W/L are presented in Table 2. The input metal-insulator-metal (MIM) capacitor C i with a capacitance value of 0.5 pF was used. The layout of the MI-G m is shown in Figure 7, with a silicon area of 116.3 µm × 99.2 µm.  The DC transfer characteristics of the used MI-Gm for Iset = [2,5,10,15,20,25] nA are shown in Figure 8. The enhanced linearity in the Vin range of ±500 mV is clearly observable. For the filter application, the simulated frequency responses of the proposed filter are shown in Figure 9. The values of C1 = C2 = 15 pF and the setting current Iset = 5 nA. The simulated cut-off frequency value of 153 Hz is very close to the calculated value of 154.9 Hz. The power consumption of the filter was 37 nW.  The DC transfer characteristics of the used MI-G m for I set = [2,5,10,15,20,25] nA are shown in Figure 8. The enhanced linearity in the V in range of ±500 mV is clearly observable. The DC transfer characteristics of the used MI-Gm for Iset = [2,5,10,15,20,25] nA are shown in Figure 8. The enhanced linearity in the Vin range of ±500 mV is clearly observable. For the filter application, the simulated frequency responses of the proposed filter are shown in Figure 9. The values of C1 = C2 = 15 pF and the setting current Iset = 5 nA. The simulated cut-off frequency value of 153 Hz is very close to the calculated value of 154.9 Hz. The power consumption of the filter was 37 nW. For the filter application, the simulated frequency responses of the proposed filter are shown in Figure 9. The values of C 1 = C 2 = 15 pF and the setting current I set = 5 nA. The simulated cut-off frequency value of 153 Hz is very close to the calculated value of 154.9 Hz. The power consumption of the filter was 37 nW.  For the filter application, the simulated frequency responses of the proposed filter are shown in Figure 9. The values of C1 = C2 = 15 pF and the setting current Iset = 5 nA. The simulated cut-off frequency value of 153 Hz is very close to the calculated value of 154.9 Hz. The power consumption of the filter was 37 nW.   The Monte Carlo process and mismatch analysis was performed with 200 runs. Figure 11 shows the simulated results for the LPF and BPF. The low-frequency gain at 1 Hz of the LPF was in the range from −1.39 dB to 0.47 dB, and the gain of the BPF at a frequency of 153 Hz was in the range from −0.438 dB to 0.168 dB.
The Monte Carlo process and mismatch analysis was performed with 200 runs. Figure 11 shows the simulated results for the LPF and BPF. The low-frequency gain at 1 Hz of the LPF was in the range from −1.39 dB to 0.47 dB, and the gain of the BPF at a frequency of 153 Hz was in the range from −0.438 dB to 0.168 dB.
(a) (b) Figure 11. The Monte Carlo simulation of the LPF (a) and BPF (b). Figure 12 shows the simulation results of the LPF and BPF with the process, voltage, and temperature variations. The process corners were fast-fast, fast-slow, slow-fast, and slow-slow, the voltage supply corners were in the range of VDD ± 10%, and the temperature corners were 0 °C and 70 °C.  Figure 12 shows the simulation results of the LPF and BPF with the process, voltage, and temperature variations. The process corners were fast-fast, fast-slow, slow-fast, and slow-slow, the voltage supply corners were in the range of V DD ± 10%, and the temperature corners were 0 • C and 70 • C.  Figure 13 shows the transient response of the LPF with an applied input signal of 100mVpp @ 50Hz and its output spectrum. The total harmonic distortion (THD) of 0.33% was achieved, which was kept still below 1% for the input signal of 200 mVpp @ 50 Hz. The output integrated noise of the LPF was 220 µVrms which resulted in a 50 dB dynamic range (DR = 20 × log (Vrms-max/Vrms-onoise)) of the filter with 1% THD.  Table 3 shows a comparison of the proposed filter with the others [26][27][28]. It is evident that the proposed filter offers the largest amount of filtering functions with a minimum count of active elements, and the lowest voltage supply, and is the only one with nanopower consumption. All these facts confirm the usability of the multiple-input Gm stage in filter applications mainly by means of reducing the count of active blocks and power consumption. The figure of merit (FoM) is also presented, where a lower FoM im-  Figure 13 shows the transient response of the LPF with an applied input signal of 100mV pp @ 50Hz and its output spectrum. The total harmonic distortion (THD) of 0.33% was achieved, which was kept still below 1% for the input signal of 200 mV pp @ 50 Hz. The output integrated noise of the LPF was 220 µV rms which resulted in a 50 dB dynamic range (DR = 20 × log (V rms-max /V rms-onoise )) of the filter with 1% THD.  Figure 13 shows the transient response of the LPF with an applied input signal of 100mVpp @ 50Hz and its output spectrum. The total harmonic distortion (THD) of 0.33% was achieved, which was kept still below 1% for the input signal of 200 mVpp @ 50 Hz. The output integrated noise of the LPF was 220 µVrms which resulted in a 50 dB dynamic range (DR = 20 × log (Vrms-max/Vrms-onoise)) of the filter with 1% THD.  Table 3 shows a comparison of the proposed filter with the others [26][27][28]. It is evident that the proposed filter offers the largest amount of filtering functions with a minimum count of active elements, and the lowest voltage supply, and is the only one with nanopower consumption. All these facts confirm the usability of the multiple-input Gm stage in filter applications mainly by means of reducing the count of active blocks and  Table 3 shows a comparison of the proposed filter with the others [26][27][28]. It is evident that the proposed filter offers the largest amount of filtering functions with a minimum count of active elements, and the lowest voltage supply, and is the only one with nanopower consumption. All these facts confirm the usability of the multiple-input G m stage in filter applications mainly by means of reducing the count of active blocks and power consumption. The figure of merit (FoM) is also presented, where a lower FoM implies the better performance of the filter. where P diss is the power dissipation, f o is the center frequency, N is the order of filter, and DR is the dynamic range.

Conclusions
This paper demonstrates the advantages of the MI-G m in filter application, in terms of topology simplification, increasing filter functions, and minimizing the count of the needed active blocks and their power consumption. Therefore, the developed circuit is a good candidate for extremely low-power low-voltage applications like biosignals processing. The filter application offers the largest amount of filtering functions with a minimum count of active elements. The post-layout simulations prove the presented advantages of MI-G m .