# FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation

^{1}

^{2}

^{*}

## Abstract

**:**

_{x}is capacitively coupled with the measurement electrodes with time-varying unknown capacitance C

_{x}, CIS can be measured. As a proof of concept, this study aimed to develop a prototype that implemented the novel algorithm of CIS and circuit parameter estimation to verify whether the frequency spectra and circuit parameters could be obtained in milliseconds and whether time-varying impedance could be measured. This study proposes a dedicated processor that was implemented as field-programmable gate arrays to perform CIS, estimate R

_{x}and C

_{x}, and their digital-to-analog conversions at a certain time, and to repeat them continually. The proposed processor executed the entire sequence in the order of milliseconds. Combined with a front-end nonsinusoidal oscillator and interfacing circuits, the processor estimated the fixed R

_{x}and fixed C

_{x}with reasonable accuracy. Additionally, the combined system with the processor succeeded in detecting a quick optical response in the resistance of the cadmium sulfide (CdS) photocell connected in series with a capacitor, and in reading out their resistance and capacitance independently as voltages in real-time.

## 1. Introduction

_{x}(t) is capacitively coupled with the measuring electrodes with time-varying unknown capacitance C

_{x}(t). In this method, the measurement object and the capacitive coupling are embedded in the nonsinusoidal oscillation circuit. The frequency spectra of the complex electrical impedance of the measurement object are obtained rapidly using discrete Fourier transform (DFT) to analyze the obtained oscillation waveform. Therefore, the resistance and capacitance of the measurement object can be estimated from the obtained impedance spectra, and changing the frequency of the excitation voltage is not required. Moreover, because the analysis is used in only a single-cycle waveform, EIS can quickly measure the measurement object, indicating that the time-varying unknown impedance is obtained with real-time processing. In [33], we reported good, estimated results using an equivalent circuit model comprising resistance and capacitance that could be applied in living tissue impedance measurement. We also reported the possibility of detecting rapid optical response in the resistance of cadmium sulfide (CdS) photocells.

- The architecture of the proposed FPGA-based processor based on CIS and parameter estimation in the CR circuit model that can be measured in real-time were shown;
- The measurement accuracy of the proposed FPGA-based processor was confirmed;
- We show that continual impedance estimation in real-time is possible using the proposed FPGA-based processor.

## 2. Materials and Systems

#### 2.1. Overview of the Proposed FPGA-Based Processor and CIS Method

_{x}in series with an unknown capacitance C

_{x}, a FPGA-based processor for CIS, and the parameter estimation on the CR circuit model. Table 1 shows the list of notations in this paper.

_{x}

_{1}and C

_{x}

_{2}, where C

_{x}= C

_{x}

_{1}C

_{x}

_{2}/(C

_{x}

_{1}+ C

_{x}

_{2}) denotes the combined capacitance of C

_{x}

_{1}and C

_{x}

_{2}. The measurement object had a series circuit model of an unknown resistance R

_{x}and capacitance C

_{x}(CR circuit model). They were built in as part of the nonsinusoidal oscillator. The proposed FPGA-based processor comprised an input interfacing part, DFT, a spectrum calculation based on CIS, the parameter estimation on the CR circuit model, and a DAC. First, the oscillation waveform for a single cycle was digitalized and stored using the input interfacing part. Second, the impedance spectra were calculated using CIS calculations based on DFT. Third, the parameter estimation to fit the CR circuit model was obtained from multiple impedance spectra. Finally, the estimated results were converted to an analog voltage at a certain time, and the processor repeated these processes continually.

_{x}

_{2}and to R

_{A}via C

_{x}

_{1}. R

_{A}existed for the current–voltage conversion. The unknown impedance ${\dot{Z}}_{x}$ could be calculated using Equation (1), and it could be estimated using the following process from [32,33]:

_{A}and stray capacitance C

_{A}. ${\dot{Z}}_{x}$ at each frequency f can be obtained as follows:

_{0}and its integral multiple nf

_{0}as follows:

_{0}of ${v}_{1}\left(t\right)$ and ${v}_{12}\left(t\right)$ can be calculated as follows:

_{0}. If ${v}_{1}\left(t+{T}_{0}\right)=-{v}_{1}\left(t\right)$, ${v}_{12}\left(t\right)$ and ${v}_{1}\left(t\right)$ consist only of odd-order frequency components.

_{0}. The real and imaginary parts of ${\dot{V}}_{12}\left(n{f}_{0}\right)$ and ${\dot{V}}_{1}\left(n{f}_{0}\right)$ were calculated as follows:

_{x}and C

_{x}were estimated by fitting an appropriate function to the real and imaginary parts of spectrum ${\dot{Z}}_{x}$ at the frequency nf

_{0}(n = 1, 3, 5, …). The appropriate function for the real part was a constant (Equation (22)), and the function for the imaginary part was rational (Equation (23)).

#### 2.2. Architecture of the Proposed FPGA-Based Processor for CIS and the Parameter Estimation on the CR Circuit Model

- (a)
- Input interfacing part;
- (b)
- CIS calculation;
- (c)
- Parameter estimation on the CR circuit model;
- (d)
- Digital-to-analog (DA) conversion.

_{0}and odd order up to M based on DFT. M is a parameter that can be set from the external of the processor. In the (c) parameter estimation on the CR circuit model, the R

_{x}and C

_{x}of the measured object were estimated using the obtained impedance spectrum at each frequency based on the least-squares method. The estimations were performed from the obtained impedance spectrum data in four-cycle waveforms. In the (d) DA conversion block, the estimated R

_{x}and C

_{x}(R

_{x_est}and C

_{x_est}, respectively) were quantized and converted to pulse density modulation (PDM) signals based on 1-bit ΔΣDAC. Then, the CR low-pass filter (LPF) outputted the PDM signals of R

_{x_est}and C

_{x_est}as an analog voltage.

#### 2.2.1. Input Interfacing Part

_{1}removed the DC component. Then, these voltages were level-converted to approximately 1/2 using the inverted amplifier in the input voltage range of the ADC. The attenuation rate 1/2 of the inverted amplifier was experimentally set to fit within the input voltage range. C

_{1}was 10 μF, R

_{1}was 10 kΩ, and R

_{2}was 5.1 kΩ. The op-amps were AD822 (Analog Devices Inc.). The power supplies of the circuit were 5 V from the mobile battery (CHE-061-IOT, TRA Co., Ltd., Osaka, Japan) and −5 V from the voltage converter IC (LTC1144, Analog Devices Inc.).${V}_{\mathrm{ref}}$ was supplied at 0.5 V, half of the input voltage range of the ADC. Furthermore, the ${v}_{1}\left(t\right)$ and ${v}_{2}\left(t\right)$ circuits had the same configuration.

_{s}= 1 MHz), input voltage range of 0–1 V, and differential input, and AD conversion is possible for two channels simultaneously. ${v}_{1}\left(t\right)$ and ${v}_{2}\left(t\right)$ after AD conversion were expressed as ${v}_{1}\left(i\right)$ and ${v}_{2}\left(i\right)$. The rising edge of the waveform from negative to positive was detected by monitoring ${v}_{1}\left(i\right)$. Moreover, this block had a frequency counter at the detected rising edge. Thus, the fundamental frequency f

_{0}of oscillation waveform for a single cycle were calculated using the number of samples N during the rising edge and sampling frequency f

_{s}of the ADC (f

_{0}= f

_{s}/N).

#### 2.2.2. CIS Calculation

_{A}and C

_{A}were measured in advance and set external to the processor as constants in the FPGA. ${\dot{Z}}_{x}$ was calculated based on Equations (20) and (21) using the results of the DFT and ${\dot{Z}}_{\mathrm{A}}$, and the real part of ${\dot{Z}}_{x}$ ($\mathrm{Re}({\dot{Z}}_{x})$) and the imaginary part of ${\dot{Z}}_{x}$ ($\mathrm{Im}({\dot{Z}}_{x})$) at each frequency are output.

#### 2.2.3. Parameter Estimation on CR Circuit Model Based on the Least-Squares Method

_{x}and C

_{x}were estimated by model fitting based on the least-squares method to the real and imaginary parts of the impedance spectra. To avoid the effect of noise, the model fitting used up to the Mth harmonic component. The R

_{x_est}that minimized J

_{Rx}in Equation (24) was the estimated value of the R

_{x}, and the C

_{x_est}that minimized J

_{Cx}in Equation (25) was the estimated value of the C

_{x}.

_{Rx}becomes the minimum when the derivative of R

_{x_est}becomes 0. In Equation (25), J

_{Cx}becomes the minimum when the derivative of u = 1/C

_{x_est}becomes 0.

_{0}(n = 1, 3, 5, …, M). Let ${\mathit{B}}_{Re}$ and ${\mathit{B}}_{Im}$ be the real and imaginary parts of the basis vector at nf

_{0}. These are defined as follows:

**,**and ${\mathit{B}}_{Im}$.

_{x_est}and C

_{x_est}were calculated using the following equations,

_{x_est}and C

_{x_est}each time the block obtains a spectral value for each frequency nf

_{0}(n = 1, 3, 5, …, M).

#### 2.2.4. DA Conversion

_{x_est}and C

_{x_est}into analog voltages and outputted them. First, the quantization module quantized the estimated results based on Equations (40) and (41). The quantization bits $Q$ were 24 bits.

_{max}is the maximum value of measurable resistance and C

_{max}is the maximum value of measurable capacitance. The output voltage was maximum when the estimated values were R

_{max}and C

_{max}. Moreover, the measurement range could be changed by changing the R

_{max}and C

_{max}values.

_{LPF}and C

_{LPF}were 10 kΩ and 3.3 nF, respectively. These values were adjusted so that half of the maximum output voltage of the FPGA board V

_{max}was outputted when ${2}^{Q-1}$, half of the maximum quantization value, was inputted. The conversion from the output voltage to the estimated values of R

_{x}and C

_{x}could be conducted using Equations (42) and (43):

#### 2.3. Execution Time of the Proposed FPGA-Based Processor

_{x}and C

_{x}for one frequency spectrum was 449 + N cycles. In total, 449 + N cycles were the pipeline processing, and 449 cycles were pipeline stalls caused by waiting for the calculation result in the previous stage (data hazard). At the start of the DFT calculation, stalls occurred in 255 cycles, 119 cycles for ${\dot{Z}}_{x}$ sine and cosine calculation, and 75 cycles for parameter estimation part C

_{x_est}calculation. The total number of stalls was 449 (= 255 + 119 + 75) cycles. N was the number of samples of single-cycle waveforms. The execution time T

_{exe}of estimating R

_{x}and C

_{x}by odd order up to order M could be calculated using

_{FPGA}is the reciprocal of the operating frequency of FPGA.

## 3. System Evaluation Method

_{x}and fixed C

_{x}, and detecting the rapid optical response in resistance of a CdS photocell as time-varying impedance. In the following evaluation, we used the Z-7020 (xc7z020clg400-1, Xilinx Inc.) of the Zynq-7000 series as the target FPGA, and the FPGA board used Zybo Z7 (Digilent Inc.).

#### 3.1. Calculation Method of the Execution Times and Other Environments for Comparison

_{x}= 1.0 kΩ and polypropylene film capacitor C

_{x}= 10 nF using an oscilloscope (TBS2104B, Tektronix Inc., Beaverton, OR, USA). The C program was estimated from the IS data to the 19th order (e.g., the CIS calculation was repeated 10 times) using these waveform data. The execution time of the proposed FPGA-based processor was calculated using the required cycles from Equation (44). Generally, the execution time of FPGA can be measured. However, because the execution time of the proposed processor varied with the number of samples of the input-single cycle oscillation waveforms depending on the resistance of the measured object, it was difficult to perform a precise comparison for this system. Thus, to match the conditions with the comparison environments, the FPGA execution time was calculated from waveform data with the same amount of data. The execution time of the proposed FPGA-based processor was compared with the averaged values of running the C program 10 times on the PC and Raspberry Pi. Because the C program ran on the operating system, the execution time varied depending on the program running in the background. Thus, we employed the mean value repeated 10 times as the execution time.

#### 3.2. Measuring Methods of Fixed Resistors and Capacitors

_{x}had metal film resistors of 0.2 k–10 kΩ, and C

_{x}had polypropylene film capacitors of 1, 5, and 10 nF. Furthermore, the orders were set to 31st order for C

_{x}= 10 nF and 19th order for C

_{x}= 5 nF. In the C

_{x}= 1 nF, the order did not exceed 100 kHz and was adjusted. The C

_{A}was 10 pF. Furthermore, R

_{max}, which determined the measurement range, was set to 1.0 kΩ when R

_{x}was 0.2 k–0.91 kΩ, R

_{max}was set to 10 kΩ when R

_{x}was 2.0 k–9.1 kΩ, and R

_{max}was set to 100 kΩ when R

_{x}was 10 kΩ. Similarly, C

_{max}was 10 nF when C

_{x}was 1 and 5 nF, and C

_{max}was set to 100 nF when C

_{x}was 10 nF.

#### 3.3. Measuring Method of CdS Photocell for Time-Varying Impedance Measurement

_{x}to the nonsinusoidal oscillator shown in Figure 1. An NJU7032D (Nissinbo Micro Devices Inc., Tokyo, Japan) was used as the operational amplifier. A 2N7000 (ON Semiconductor Co., Phoenix, AZ, USA) was used as a field-effect transistor. The combined capacitance C

_{x}= C

_{x}

_{1}C

_{x}

_{2}/(C

_{x}

_{1}+ C

_{x}

_{2}) was used as the alternative capacitance of C

_{x}

_{1}and C

_{x}

_{2}. C

_{x}was provided by a polypropylene film capacitor of 10 nF. We measured R

_{x}and C

_{x}when R

_{max}was set at 2 kΩ, C

_{max}was set at 100 nF, and I

_{Ph}= 0.4–10 mA by changing the V

_{C}= 0.08 to 2.0 V. Because the oscillation frequency changed near 20 kHz, the order was set to the 5th order because the frequency would be approximately 100 kHz. The R

_{F}, R

_{A}, and C

_{A}were 8.2 kΩ, 0.2 kΩ, and 0 pF, respectively. The proposed FPGA-based processor was estimated using four-cycle waveforms (one segment). The analog voltages of the estimated values were measured using the same measuring instrument described in Section 3.2. The measured voltages were converted to resistance and capacitance values.

## 4. Results

#### 4.1. Result of the Comparison of Execution Times

_{FPGA}= 6.67 ns). In the used waveform data for comparison obtained by the oscilloscope, the fundamental frequency f

_{0}was 675 Hz (T

_{0}= 1.48 ms), and the number of waveform samples N was 1852 at 1.25 MHz sample per second. The order M was 19th order. Therefore, the proposed FPGA-based processor could be calculated at 0.153 ms after saving the waveform for a single cycle using these results. On the other hand, the PC consumed 0.263 ± 0.029 ms (Min.–Max.: 0.217–0.310 ms) and took 1.71 ± 0.19 times (Min.–Max.: 1.41–2.02 times) longer than the proposed FPGA-based processor. From the time-saving value of 0.11 ms, which is the result in Table 4, it became obvious that the proposed FPGA-based processor could perform 0.11 ms faster on average than the recent CPU with a clock frequency difference of ≥10 times. Moreover, the Raspberry Pi consumed 2.551 ± 0.622 ms (Min.–Max.: 1.047–3.193 ms) and took 16.6 ± 4.06 times (Min.–Max.: 6.8–20.8 times) longer than the processor.

#### 4.2. Measurement Results of Fixed Resistors and Capacitors

_{Rx}and V

_{Cx}from the proposed FPGA-based processor when R

_{x}= 1.0 kΩ and C

_{x}= 10 nF. The circuit parameters of R

_{x}and C

_{x}were estimated and converted to the voltages for each segment (four cycles). Because the proposed FPGA-based processor was estimated using four-cycle oscillation waveforms, the voltage waveform V

_{Rx}was changed in each segment. V

_{Rx}and V

_{Cx}were the output voltage under the measurable maximum value of R

_{max}and C

_{max}, which were set at 10 kΩ and 100 nF, respectively. V

_{Rx}and V

_{Cx}were about 330 mV. By converting from Equations (42) and (43), the estimated R

_{x}and C

_{x}were 1.0 kΩ and 10 nF, respectively. From these results, it was confirmed that the proposed FPGA-based processor could estimate R

_{x}and C

_{x}values close to the true value, and output them.

_{x}(0.2–10 kΩ) and polypropylene film capacitors C

_{x}(1–10 nF) using the proposed FPGA-based processor. The plots and error bars in Figure 8 are the mean values and standard deviations within 100 ms obtained using the oscilloscope (12.5 k samples per second). Each figure in Figure 8 is the (a) mean estimated R

_{x}value, (b) mean absolute error of the estimated R

_{x}value, (c) mean estimated C

_{x}value, or (d) relative error of the estimated C

_{x}value, respectively. From Figure 8b, the mean absolute errors of the estimated R

_{x}values were −150 Ω to 300 Ω. When R

_{x}was less than 9.1 kΩ, the errors were within ±150 Ω, and when C

_{x}was 5 and 10 nF, the errors were within ±100 Ω. When R

_{x}was 2.0 k to 9.1 kΩ, the errors were within 5%, and when C

_{x}was 1 nF, the errors increased to negative dozens of ohms. Furthermore, the standard deviations increased. However, the error was within ±150 Ω. When R

_{x}was 10 kΩ, the errors increased. Because the measurement range was set at a maximum of 100 kΩ, it was considered that the tendency was different from that of other R

_{x}values.

_{x}values were −6% to +1%, and when C

_{x}was 5 and 10 nF, the relative errors were ±1.5%. When C

_{x}was 1 nF, the relative errors increased to −3% or above; however, the maximum range was −6% or less. Moreover, for all C

_{x}values, the relative errors of C

_{x}increased as R

_{x}increased.

#### 4.3. Measurement Results of CdS Photocell

_{Ph}= 0.4 mA (Low) and I

_{Ph}= 10 mA (High). Figure 9a shows the input oscillation waveform of ${v}_{1}\left(t\right)$ and ${v}_{2}\left(t\right)$, resulting in output voltages of V

_{Rx}and V

_{Cx}from the proposed FPGA-based processor. Circuit parameters of R

_{x}and C

_{x}were estimated and converted to the voltages for each segment (four cycles). Figure 9b shows the enlarged view near 0 μs (−1000 μs to 1000 μs) in Figure 9a. In Figure 9a, the output voltage V

_{Rx}changed according to the optical response in the resistance of the CdS photocell. Furthermore, in Figure 9b, the proposed FPGA-based processor outputted the estimated values at 200–300 μs. From these results, the processor could read out the time-varying resistance R

_{x}and the capacitance C

_{x}independently in real-time.

_{x}of each I

_{Ph}value for a CdS photocell during the high period using the proposed FPGA-based processor. Figure 10a shows the time–resistance curves of R

_{x}at each I

_{Ph}value, and Figure 10b shows the saturation value at each I

_{Ph}value. The circuit parameters of R

_{x}were estimated and converted to the voltages for each segment (four cycles). The estimated R

_{x}values according to the changed I

_{Ph}values were observed.

## 5. Discussion

_{Rx}and V

_{Cx}oscillated ±5 mV, considered to be due to ΔΣDAC. By converting the oscillation of ±5 mV to resistance and capacitance, the resistance was ±1.52 Ω when R

_{max}was set at 1.0 kΩ, and the capacitance was ±0.0152 nF when C

_{max}was set at 10 nF. Therefore, these were errors of ±0.15%.

_{x}was 5 and 10 nF, the mean absolute errors of the estimated R

_{x}value were ±5%, and the mean relative errors of the estimated C

_{x}value were ±1.5%. However, when C

_{x}was 1 nF, these errors increased due to the increasing oscillation frequency. The oscillation frequency f

_{0}will be high with decreasing C

_{x}. When C

_{x}was 1 nF, f

_{0}was in the order of several kHz. Above the 10th order, the oscillation frequency exceeded 100 kHz, and the relative errors increased. Therefore, the order was adjusted so that the oscillation frequency was less than 100 kHz. The sampling frequency of the ADC caused the error because of the change in errors related to the oscillation frequency. The sampling frequency of the ADC in the current processor was approximately 1 MHz. The harmonic components analyzed using DFT were approximately 500 kHz according to the sampling theorem. However, the upper-limit frequency required to ensure CIS calculation accuracy will reduce. Therefore, improvement can be expected when using a dedicated ADC IC with a high sampling frequency and high resolution, instead of a FPGA internal ADC. Furthermore, the oscillation frequency can be decreased by increasing the ${R}_{F}$. However, the current flowing through the measurement object would decrease with increasing resistance R

_{F}of a Schmitt trigger inverter. Therefore, the error should increase in the voltage waveform occurring in R

_{A}. The analog input circuit, sampling frequency, and ADC and DAC resolution affected the measurement accuracy of the proposed FPGA-based processor. In the DAC, improvement could be expected using a dedicated DAC IC or multibit ΔΣDAC instead of a simple 1-bit ΔΣDAC. These are future studies.

_{Ph}were also measured. The estimation results were output from 200 to 300 μs. Therefore, there were 3000–5000 estimations per second. The results indicated that simultaneous measurements in real-time depended on the time-varying impedance changing with the analog voltage. Figure 9b shows that the output voltage was blunted at the transition of the estimated value because of the LPF effect of CR in the ΔΣDAC. In the future, if the oscillation frequency becomes high, the circuit constants of the resistors and capacitances that make up the LPF must be reviewed.

## 6. Conclusions

_{x}and C

_{x}, and their digital-to-analog conversions at a certain time and to repeat them continually. Even if there is a change in the circuit model to be estimated in the future, it is possible to respond flexibly by reconfiguring the FPGA-based processor. By performing circuit parameter estimation based on IS, more detailed impedance changes for the measurement object can be monitored in real-time. Furthermore, the proposed FPGA-based processor was evaluated through three examinations. The proposed processor could execute 19th-order CIS in 0.153 ms and a whole sequence in the order of milliseconds. The execution time comparison with other environments showed that the execution time of the proposed FPGA-based processor was shorter than that of a PC and a microprocessor. Furthermore, the measurement results from metal film resistors and polypropylene film capacitors suggested that estimating the resistance R

_{x}and capacitance C

_{x}with reasonable accuracy is possible. The processor estimated fixed R

_{x}within a relative error of ±5% for the metal film resistor (2.0–9.1 kΩ) and fixed C

_{x}, and within ±6% for the polypropylene film capacitor (1–10 nF). Moreover, in the measurement of a CdS photocell, the proposed processor was detected to have a rapid optical response to the resistance of the CdS photocell. The results indicated that simultaneous measurements in real time depend on the time-varying impedance changing with the analog voltage. It is considered that the purpose of demonstrating the real-time measurability based on the novel algorithm CIS method has been almost achieved by using the prototype shown in this paper. As our prototype is a simple configuration, there is room for improvement in practicality and size.

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

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**Figure 1.**Block diagram of the constructed system composed of a nonsinusoidal oscillator involving the measured object R

_{x}in series with unknown capacitance C

_{x}

_{,}a FPGA-based processor for CIS, and the parameter estimation on the CR circuit model.

**Figure 2.**Detailed illustration of the input interfacing part written in Figure 1.

**Figure 3.**Detailed illustration of the CIS calculation module written in Figure 1.

**Figure 4.**Detailed illustration of the parameter estimation on the CR circuit model written in Figure 1.

**Figure 5.**Detailed illustration of the DA conversion written in Figure 1.

**Figure 6.**Constant current circuit for the LED current control of the photocoupler. The CdS photocell was used as a photosensitive resistor, which was connected in series with unknown capacitance C

_{x}to the nonsinusoidal oscillator shown in Figure 1.

**Figure 7.**An example of oscillatory voltage ${v}_{1}\left(t\right)$ and ${v}_{2}\left(t\right)$ being inputted into the processor, resulting in output voltages of V

_{Rx}and V

_{Cx}from the proposed FPGA-based processor when R

_{x}= 1.0 kΩ, C

_{x}= 10 nF, M was set as 19th order, R

_{max}was set at 10 kΩ, and C

_{max}was set at 100 nF. The top plot is the output of the nonsinusoidal oscillator circuit when connected to the measurement object through capacitive coupling and the input waveform of the proposed processor. ${v}_{1}\left(t\right)$ and ${v}_{2}\left(t\right)$ have nothing else to convert. The bottom two plots show the results of the R

_{x}and C

_{x}circuit parameters estimated and converted into voltages for each segment (four cycles). These voltages were converted back into estimated values R

_{x}and C

_{x}, and are shown on the right side of the y-axis as the estimated values corresponding to the voltage.

**Figure 8.**Estimated results of the metal film resistors R

_{x}(0.2–10 kΩ) and polypropylene film capacitors C

_{x}(1–10 nF) using the proposed FPGA-based processor: (

**a**) mean estimated R

_{x}value; (

**b**) mean absolute error of the estimated R

_{x}value; (

**c**) mean estimated C

_{x}value; (

**d**) relative error of the estimated C

_{x}value. Plots and error bars are the mean values and standard deviations within 100 ms obtained using the oscilloscope (12.5 k samples per second).

**Figure 9.**An example of the measurement result for a CdS photocell using the proposed FPGA-based processor when I

_{Ph}= 0.4 mA (Low), I

_{Ph}= 10 mA (High), M was set as 5th order, R

_{max}was set at 2.0 kΩ, and C

_{max}was set at 100 nF: (

**a**) oscillatory voltage ${v}_{1}\left(t\right)$ and ${v}_{2}\left(t\right)$ input to the processor and resulting output voltages of V

_{Rx}and V

_{Cx}from the proposed FPGA-based processor. The top plot is the output of the nonsinusoidal oscillator circuit when connected to the measurement object through capacitive coupling and the input waveform of the proposed processor. ${v}_{1}\left(t\right)$ and ${v}_{2}\left(t\right)$ have nothing else to convert. The bottom two plots show the results of R

_{x}and C

_{x}circuit parameters estimated and converted to voltages for each segment (four cycles). These voltages were converted back into estimated values R

_{x}and C

_{x}, and are shown on the right side of the y-axis as the estimated values corresponding to the voltage; (

**b**) enlarged view near 0 μs (−1000 μs to 1000 μs) in Figure 9a.

**Figure 10.**Resistance R

_{x}of each I

_{Ph}value for a CdS photocell during the high period using the proposed FPGA-based processor: (

**a**) time–resistance curves of R

_{x}at each I

_{Ph}value; (

**b**) saturation value at each I

_{Ph}value. Circuit parameters of R

_{x}were estimated and converted to the voltages for each segment (four cycles).

Symbol | Meaning |
---|---|

R_{x} | Unknown resistance of the measurement object. |

C_{x}_{1} | Unknown capacitance 1 of capacitive coupling to the measurement object. |

C_{x}_{2} | Unknown capacitance 2 of capacitive coupling to the measurement object. |

C_{x} | Unknown capacitance caused by capacitive coupling. Combined capacitance of C_{x}_{1} and C_{x}_{2}. C_{x} = C_{x}_{1} C_{x}_{2}/(C_{x}_{1} + C_{x}_{2}). |

${\dot{Z}}_{x}$ | Unknown impedance of measurement object and capacitance caused by capacitive coupling. Combined impedance of R_{x} and C_{x}. |

R_{A} | Known resistance for I/V conversion. A resistance for calibration and converting the current flowing ${\dot{I}}_{12}$ through the measurement object into a voltage ${\dot{V}}_{1}$. |

C_{A} | Stray capacitance generated in parallel with R_{A}. |

${\dot{Z}}_{A}$ | Known impedance. Combined impedance of R_{A} and C_{A}. |

${v}_{1}\left(t\right)$ | Nonsinusoidal oscillation waveform generated by capacitive coupling to the measurement object. Voltage applied to ${\dot{Z}}_{A}$. |

${v}_{2}\left(t\right)$ | Nonsinusoidal oscillation waveform generated by capacitive coupling to the measurement object. |

${v}_{12}\left(t\right)$ | Excited voltage to the measurement object. ${v}_{12}\left(t\right)={v}_{2}\left(t\right)-{v}_{1}\left(t\right)$. |

${i}_{12}\left(t\right)$ | Current flowing through the measurement object. |

${\dot{V}}_{1}$ | Complex voltage of ${\dot{Z}}_{A}$ Complex number indication of ${v}_{1}\left(t\right)$. |

${\dot{V}}_{12}$ | Complex voltage of ${\dot{Z}}_{x}$ Complex number indication of ${v}_{12}\left(t\right)$. |

${\dot{I}}_{12}$ | Complex current of ${\dot{Z}}_{x}$ Complex number indication of ${i}_{12}\left(t\right)$. |

f | Frequency. |

f_{0} | Fundamental frequency of nonsinusoidal oscillation waveform. |

T_{0} | Period of fundamental frequency f_{0}. T_{0} = 1/f_{0}. |

n | Integer number. |

${\dot{V}}_{1}\left(n{f}_{0}\right)$ | Complex voltages ${\dot{V}}_{1}$ at frequency nf_{0}. |

${\dot{V}}_{12}\left(n{f}_{0}\right)$ | Complex voltages ${\dot{V}}_{12}$ at frequency nf_{0}. |

$\mathrm{Re}\{{\dot{V}}_{1}\left(n{f}_{0}\right)\}$ | Real part of ${\dot{V}}_{1}\left(n{f}_{0}\right)$. |

$\mathrm{Im}\{{\dot{V}}_{1}\left(n{f}_{0}\right)\}$ | Imaginary part of ${\dot{V}}_{1}\left(n{f}_{0}\right)$. |

$\mathrm{Re}\{{\dot{V}}_{12}\left(n{f}_{0}\right)\}$ | Real part of ${\dot{V}}_{12}\left(n{f}_{0}\right)$. |

$\mathrm{Im}\{{\dot{V}}_{12}\left(n{f}_{0}\right)\}$ | Imaginary part of ${\dot{V}}_{12}\left(n{f}_{0}\right)$. |

$|{\dot{V}}_{1}\left(n{f}_{0}\right)|$ | Amplitude spectrum of ${\dot{V}}_{1}\left(n{f}_{0}\right)$. |

${\theta}_{V1}\left(n{f}_{0}\right)$ | Phase spectrum of ${\dot{V}}_{1}\left(n{f}_{0}\right)$. |

$|{\dot{V}}_{12}\left(n{f}_{0}\right)|$ | Amplitude spectrum of ${\dot{V}}_{12}\left(n{f}_{0}\right)$. |

${\theta}_{V12}\left(n{f}_{0}\right)$ | Phase spectrum of ${\dot{V}}_{12}\left(n{f}_{0}\right)$. |

$|{\dot{Z}}_{A}\left(n{f}_{0}\right)|$ | Amplitude spectrum of ${\dot{Z}}_{A}\left(n{f}_{0}\right)$. |

${\theta}_{ZA}\left(n{f}_{0}\right)$ | Phase spectrum of ${\dot{Z}}_{A}\left(n{f}_{0}\right)$. |

$\mathrm{Re}({\dot{Z}}_{x})$ | Real part of ${\dot{Z}}_{x}$. Real part of the impedance of the measurement object. |

$\mathrm{Im}({\dot{Z}}_{x})$ | Imaginary part of ${\dot{Z}}_{x}$. Imaginary part of the impedance of the measurement object. |

f_{s} | Sampling frequency of ADC. |

N | Number of oscillation waveform samples at f_{0}. |

M | Upper limit order of fundamental frequency harmonics. |

R_{x_est} | Estimated R_{x} by least-squares method. |

C_{x_est} | Estimated C_{x} by least-squares method. |

J_{Rx} | Constant minimized by the least-squares method for R_{x}. |

J_{Cx} | Constant minimized by the least-squares method for C_{x}. |

u | Constant with 1/C_{x} replaced. |

m | Number of vector elements. m = (M + 1)/2. |

${\mathit{Z}}_{xRe}$ | Real part vectors of IS at nf_{0} (n = 1, 3, 5, …, M). One row m column vector. |

${\mathit{Z}}_{xIm}$ | Imaginary part vectors of IS at nf_{0} (n = 1, 3, 5, …, M). One row m column vector. |

${\mathit{B}}_{Re}$ | Real parts of the basis vector at nf_{0} (n = 1, 3, 5, …, M). M row one column vector. |

${\mathit{B}}_{Im}$ | Imaginary parts of the basis vector at nf_{0} (n = 1, 3, 5, …, M). m row one column vector. |

V_{Rx} | Processor output voltage of R_{x}. Estimated R_{x} (R_{x_est}) converted to voltage. |

V_{Cx} | Processor output voltage of C_{x}. Estimated C_{x} (C_{x_est}) converted to voltage. |

Q | Quantization bits of R_{x_est} and C_{x_est}. |

V_{max} | Maximum output voltage of the FPGA board. |

R_{max} | Maximum value of measurable resistance. |

C_{max} | Maximum value of measurable capacitance. |

R_{LPF} | Resistance of LPF used in the DA converter. |

C_{LPF} | Capacitance of LPF used in the DA converter. |

${T}_{exe}$ | Execution time of the proposed FPGA-based processor. |

${T}_{FPGA}$ | Reciprocal of operating frequency of FPGA. |

**Table 2.**Specifications of the PC and microprocessor used for comparison of the execution time of CIS.

Item | PC | Raspberry Pi 4 Model B |
---|---|---|

CPU | Intel Core [email protected] GHz, 1.69 GHz | Broadcom 2711 4-core ARM [email protected] GHz |

RAM | 16 GB | 8 GB |

SSD | 512 GB | – |

OS | Windows 10 Home | Raspbian OS |

C compiler | Visual Studio 2019 | GCC |

FPGA Resources | Available (Z-7020, xc7z020clg400-1) | Utilization |
---|---|---|

Look up table (LUT) | 53,200 | 38,896 (73.1%) |

LUT RAM | 17,400 | 939 (5.4%) |

Flip flop | 106,400 | 56,011 (52.6%) |

Block RAM | 140 | 16.5 (11.8%) |

DSP | 220 | 72 (32.7%) |

**Table 4.**Comparison of execution time for a single CIS when R

_{x}= 1.0 kΩ, C

_{x}= 10 nF, and M was set as 19th order *.

Environments | Execution Time (ms) | Ratio | |
---|---|---|---|

FPGA-based proposed processor @150 MHz | 0.153 | 1 | |

PC (C, Single thread) @2.8 GHz, 1.69 GHz | Minimum | 0.217 | 1.41 |

Mean ± S.D. | 0.263 ± 0.029 | 1.71 | |

Maximum | 0.310 | 2.02 | |

Raspberry Pi 4 (C, Single thread) @1.5 GHz | Minimum | 1.047 | 6.8 |

Mean ± S.D. | 2.551 ± 0.622 | 16.6 | |

Maximum | 3.193 | 20.8 |

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## Share and Cite

**MDPI and ACS Style**

Tsukahara, A.; Yamaguchi, T.; Tanaka, Y.; Ueno, A. FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation. *Sensors* **2022**, *22*, 4406.
https://doi.org/10.3390/s22124406

**AMA Style**

Tsukahara A, Yamaguchi T, Tanaka Y, Ueno A. FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation. *Sensors*. 2022; 22(12):4406.
https://doi.org/10.3390/s22124406

**Chicago/Turabian Style**

Tsukahara, Akihiko, Tomiharu Yamaguchi, Yuho Tanaka, and Akinori Ueno. 2022. "FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation" *Sensors* 22, no. 12: 4406.
https://doi.org/10.3390/s22124406