FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation

In principle, the recently proposed capacitive-coupling impedance spectroscopy (CIS) has the capability to acquire frequency spectra of complex electrical impedance sequentially on a millisecond timescale. Even when the measured object with time-varying unknown resistance Rx is capacitively coupled with the measurement electrodes with time-varying unknown capacitance Cx, CIS can be measured. As a proof of concept, this study aimed to develop a prototype that implemented the novel algorithm of CIS and circuit parameter estimation to verify whether the frequency spectra and circuit parameters could be obtained in milliseconds and whether time-varying impedance could be measured. This study proposes a dedicated processor that was implemented as field-programmable gate arrays to perform CIS, estimate Rx and Cx, and their digital-to-analog conversions at a certain time, and to repeat them continually. The proposed processor executed the entire sequence in the order of milliseconds. Combined with a front-end nonsinusoidal oscillator and interfacing circuits, the processor estimated the fixed Rx and fixed Cx with reasonable accuracy. Additionally, the combined system with the processor succeeded in detecting a quick optical response in the resistance of the cadmium sulfide (CdS) photocell connected in series with a capacitor, and in reading out their resistance and capacitance independently as voltages in real-time.


Introduction
Electrical impedance measurement has attracted much attention in various fields. Electrical impedance spectroscopy (EIS) is a method of examining the amplitude (Ω) and phase (rad) of impedance (Ω) at each frequency (Hz). EIS can be applied to the medical and healthcare fields [1]. Furthermore, applications for monitoring substance properties include lithium-ion battery characteristic monitoring [2], aluminum alloy 7075 corrosion [3], and the dehydration of plants [4]. Particularly in the medical field, electrical impedance is applied in body tissue analysis as bioelectrical impedance analysis [5], disease diagnosis as bioelectrical impedance vector analysis [6], monitoring the contact status of local impedance in catheter ablation for treating arrhythmia [7], pathogen detection of COVID-19 [8], rapid screening for influenza virus [9], DNA analysis [10,11], continuous monitoring of bioimpedance [12], blood pressure monitoring [13,14], and more. Furthermore, electrical impedance tomography (EIT) [15] has been applied in monitoring lungs, brain activity, cancer diagnosis, and merging biomedical applications [16]. In the medical field, impedance measurement requires impedances to be obtained at multiple frequencies. Therefore, if impedance spectroscopy (IS) in a wide frequency band and in real-time is obtained, detailed information about living tissue can be obtained, indicating higher accuracy and faster illness diagnosis and treatment.
In conventional impedance measurement, the measurement object is connected to the measurement system via electrodes as resistant coupling, and the measurement frequency measure the measurement object, indicating that the time-varying unknown impedance is obtained with real-time processing. In [33], we reported good, estimated results using an equivalent circuit model comprising resistance and capacitance that could be applied in living tissue impedance measurement. We also reported the possibility of detecting rapid optical response in the resistance of cadmium sulfide (CdS) photocells.
In the conventional EIS method, it is often the case that sine waves with different frequencies are applied to the measurement object as excitation voltages, the currents flowing through the measurement object are measured, and the impedances for each frequency are obtained [1,3,4,11]. In this method, the excitation voltage needs to be switched multiple times and the measurement time increases in proportion to the number of excitation voltages. Since the excitation voltage needs to be applied for a single cycle or more, a certain measurement time is required as the frequency becomes lower. Furthermore, a method of synthesizing dozens of sine waves with different frequencies and applying a single excitation voltage has been proposed [2]. In this method, the frequency needs to be changed according to the measurement object. On the other hand, the CIS approach does not require the application of multiple waveforms with different frequencies, and EIS can be obtained by analyzing a nonsinusoidal oscillation waveform with a single cycle. There is no need to change the frequency according to the measurement object. Additionally, since the CIS approach is capacitive coupling, EIS can be measured in a non-contact manner through an insulator. An EIS method has been not reported that is based on capacitive coupling and does not require a frequency change of the excitation voltage.
In our previous studies [32,33], it was confirmed offline in [32,33] that the time-varying impedance can be obtained in milliseconds using the novel algorithm of the CIS approach. From this result, it was clarified that the CIS approach can obtain EIS on the order of milliseconds in principle. Therefore, the CIS method can be expected to be used for an electronic sensor that repeatedly measures an impedance spectrum via capacitive coupling in a short time. To embody the sensor, it is necessary to implement the CIS algorithm involving DFT in a digital processor and to determine circuit parameters, such as resistance and capacitance, from each impedance spectrum. Moreover, if these circuit parameters are output as an analog voltage, they can be handled simply. Thus, in this study, we aimed to develop a proof-of-concept prototype that obtains EIS based on the CIS approach, estimates circuit parameters, converts them to an analog voltage, and outputs them. In view of speeding up the above-mentioned processing, lowering the initial cost for modularization, and enhancing the function of circuit parameter estimation in the future, we adopted a FPGA-based processor for implementation. Furthermore, from the experiments reported in the previous paper [33], it was confirmed that the optical response of the CdS photocell occurs in a short time of about 2.5 ms. The frequency of the voltage excited by the CdS photocell was around 20 kHz. Thus, in our prototype, we aimed to support the frequency of 20 kHz or higher, and to obtain the result in 1 ms or less, including the CIS calculation, circuit parameter estimation, and analog voltage output as the execution time.
In this study, the target circuit model of the measurement object was a series circuit of capacitance and resistance (CR circuit model). The contributions of this study are as follows: • The architecture of the proposed FPGA-based processor based on CIS and parameter estimation in the CR circuit model that can be measured in real-time were shown; • The measurement accuracy of the proposed FPGA-based processor was confirmed; • We show that continual impedance estimation in real-time is possible using the proposed FPGA-based processor.
Section 2 describes an overview of the proposed FPGA-based processor, the implemented CIS principle, the detailed configuration of the proposed processor, and the estimation of the processor execution time. Section 3 describes three experimental approaches conducted to evaluate the proposed processor, a comparison of the execution time with other environments, verification of the measurement accuracy using known fixed resistors and capacitors, and responsiveness verification to time-varying impedance by measuring a CdS photocell as an example. Section 4 presents the results of the three experiments, and Section 5 offers a discussion.

Materials and Systems
2.1. Overview of the Proposed FPGA-Based Processor and CIS Method Figure 1 shows a block diagram of the constructed system composed of a nonsinusoidal oscillator involving a measured object R x in series with an unknown capacitance C x , a FPGA-based processor for CIS, and the parameter estimation on the CR circuit model. Table 1 shows the list of notations in this paper. Section 2 describes an overview of the proposed FPGA-based processor, the implemented CIS principle, the detailed configuration of the proposed processor, and the estimation of the processor execution time. Section 3 describes three experimental approaches conducted to evaluate the proposed processor, a comparison of the execution time with other environments, verification of the measurement accuracy using known fixed resistors and capacitors, and responsiveness verification to time-varying impedance by measuring a CdS photocell as an example. Section 4 presents the results of the three experiments, and Section 5 offers a discussion. Figure 1 shows a block diagram of the constructed system composed of a nonsinusoidal oscillator involving a measured object Rx in series with an unknown capacitance Cx, a FPGA-based processor for CIS, and the parameter estimation on the CR circuit model. Table 1 shows the list of notations in this paper.   Block diagram of the constructed system composed of a nonsinusoidal oscillator involving the measured object R x in series with unknown capacitance C x, a FPGA-based processor for CIS, and the parameter estimation on the CR circuit model.

Overview of the Proposed FPGA-Based Processor and CIS Method
Current flowing through the measurement object. .

B Re
Real parts of the basis vector at nf 0 (n = 1, 3, 5, . . . , M). M row one column vector. The non-sinusoidal oscillator circuit is based on a Schmitt trigger inverter (74HC14AP; Toshiba, Japan). The measurement object was targeted for resistance, and it was a model capacitively coupled with C x1 and C x2 , where C x = C x1 C x2 /(C x1 + C x2 ) denotes the combined capacitance of C x1 and C x2 . The measurement object had a series circuit model of an unknown resistance R x and capacitance C x (CR circuit model). They were built in as part of the nonsinusoidal oscillator. The proposed FPGA-based processor comprised an input interfacing part, DFT, a spectrum calculation based on CIS, the parameter estimation on the CR circuit model, and a DAC. First, the oscillation waveform for a single cycle was digitalized and stored using the input interfacing part. Second, the impedance spectra were calculated using CIS calculations based on DFT. Third, the parameter estimation to fit the CR circuit model was obtained from multiple impedance spectra. Finally, the estimated results were converted to an analog voltage at a certain time, and the processor repeated these processes continually.
The measurement object was connected to a Schmitt trigger inverter oscillator via C x2 and to R A via C x1 . R A existed for the current-voltage conversion. The unknown impedance . Z x could be calculated using Equation (1), and it could be estimated using the following process from [32,33]: Z A is the combined impedance of the known resistance R A and stray capacitance C A .
. Z x at each frequency f can be obtained as follows: .
In Figure 1, voltages v 1 (t) and v 12 (t) are nonsinusoidal oscillation waveforms. The Fourier series expansion of waveform for a single cycle (T 0 = 1/ f 0 ) can be regarded as the sine wave of the fundamental frequency f 0 and its integral multiple nf 0 as follows: Therefore, the Fourier coefficient of each frequency component can be obtained as the amplitude and phase spectra by the Fourier transformation of the section. Fourier transformations at continuous time t and frequency nf 0 of v 1 (t) and v 12 (t) can be calculated as follows: .
V 12 (n f 0 ) and , v 12 (t) and v 1 (t) consist only of odd-order frequency components.
Because the proposed FPGA-based processor is a digital circuit, it was obtained using the DFT. The DFTs of . V 1 (n f 0 ) and . V 12 (n f 0 ) were calculated as follows: .
where v 1 (i) and v 12 (i) are the analog-to-digital (AD) converted values of v 1 (t) and v 12 (t), respectively, and N is the number of oscillation waveform samples at f 0 . The real and imaginary parts of .
V 1 (n f 0 ) were calculated as follows: respectively. Furthermore, the amplitude spectra (| . V 12 (n f 0 )| and | . V 1 (n f 0 )|) and phase spectra (θ V12 (n f 0 ) and θ V1 (n f 0 )) of . V 12 (n f 0 ) and . V 1 (n f 0 ) were respectively calculated as follows: Moreover, the amplitude spectra | . Z A (n f 0 )| and phase spectra θ ZA (n f 0 ) of . Z A (n f 0 ) were calculated as follows: Therefore, unknown impedance . Z x was calculated using Equation (19) from the obtained amplitude and phase spectra: Then, the real and imaginary parts of . Z x (n f 0 ) were calculated as follows: Im( When the measurement object was the CR circuit model, R x and C x were estimated by fitting an appropriate function to the real and imaginary parts of spectrum . Z x at the frequency nf 0 (n = 1, 3, 5, . . . ). The appropriate function for the real part was a constant (Equation (22)), and the function for the imaginary part was rational (Equation (23)). Im( Furthermore, the CIS method could be applied to bioimpedance by changing the circuit model of . Z x [33]. All blocks were designed as digital circuits based on FPGA. However, part of blocks (a) and (d) comprised an external analog circuit. The processor operated as follows. In the (a) input interfacing part, the oscillation waveform was converted to input the voltage range of the ADC from the external analog circuit, and the analog voltage was converted by the ADC built into the FPGA. Then, the oscillation waveform for a single cycle was detected and stored in random-access memory (RAM). In the (b) CIS calculation block, the impedance spectrum was at the fundamental frequency f 0 and odd order up to M based on DFT. M is a parameter that can be set from the external of the processor. In the (c) parameter estimation on the CR circuit model, the R x and C x of the measured object were estimated using the obtained impedance spectrum at each frequency based on the least-squares method. The estimations were performed from the obtained impedance spectrum data in four-cycle waveforms. In the (d) DA conversion block, the estimated R x and C x (R x_est and C x_est , respectively) were quantized and converted to pulse density modulation (PDM) signals based on 1-bit ∆ΣDAC. Then, the CR low-pass filter (LPF) outputted the PDM signals of R x_est and C x_est as an analog voltage.
The digital circuits on FPGA were used as very-high-speed integrated circuits hardware description language (VHDL). The circuit design and simulation tool used was Vivado 2020.2 (Xilinx Inc., San Jose, CA, USA). The target FPGA was the Z-7020 (xc7z020clg400-1, Xilinx Inc.) of the Zynq-7000 series, and the FPGA board was Zybo Z7 (Digilent Inc., Pullman, WA, USA). The calculation module in the FPGA used single-precision floating-point arithmetic units for the four arithmetic operations. Furthermore, the trigonometric functions, angle adjustment parts, and polar transformations used to convert the amplitude and phase were CORDIC IP core (Xilinx Inc.). These were converted to a fixed-point format and calculated. The details of each block are described below. Figure 2 shows a detailed illustration of the input interfacing part. In the level converter block, voltage followers were connected to points v 1 (t) and v 2 (t) in the oscillator, and C 1 removed the DC component. Then, these voltages were level-converted to approximately 1/2 using the inverted amplifier in the input voltage range of the ADC. The attenuation rate 1/2 of the inverted amplifier was experimentally set to fit within the input voltage range. C 1 was 10 µF, R 1 was 10 kΩ, and R 2 was 5.1 kΩ. The op-amps were AD822 (Analog Devices Inc.). The power supplies of the circuit were 5 V from the mobile battery (CHE-061-IOT, TRA Co., Ltd., Osaka, Japan) and −5 V from the voltage converter IC (LTC1144, Analog Devices Inc.). V ref was supplied at 0.5 V, half of the input voltage range of the ADC. Furthermore, the v 1 (t) and v 2 (t) circuits had the same configuration.

Input Interfacing Part
voltage range. C1 was 10 μF, R1 was 10 kΩ, and R2 was 5.1 kΩ. The op-amps were AD822 (Analog Devices Inc.). The power supplies of the circuit were 5 V from the mobile battery (CHE-061-IOT, TRA Co., Ltd., Osaka, Japan) and −5 V from the voltage converter IC (LTC1144, Analog Devices Inc.). ref was supplied at 0.5 V, half of the input voltage range of the ADC. Furthermore, the 1 ( ) and 2 ( ) circuits had the same configuration.
In the ADC and single-cycle waveform module detection, the ADC used the Xilinx ADC (XADC) built into the FPGA. The XADC is a successive approximation register type with a 12-bit resolution, 1 mega sample per second (sampling frequency fs = 1 MHz), input voltage range of 0-1 V, and differential input, and AD conversion is possible for two channels simultaneously. 1 ( ) and 2 ( ) after AD conversion were expressed as 1 ( ) and 2 ( ). The rising edge of the waveform from negative to positive was detected by monitoring 1 ( ). Moreover, this block had a frequency counter at the detected rising edge. Thus, the fundamental frequency f0 of oscillation waveform for a single cycle were calculated using the number of samples N during the rising edge and sampling frequency fs of the ADC (f0 = fs/N).
Simultaneously, when a rising edge was detected, the results of ADC were stored in the RAM until the next rising edge was detected. Furthermore, 12 ( ) was calculated by subtracting 2 ( ) from 1 ( ), and it was stored in RAM at the same time as 1 ( ). Moreover, two RAMs were prepared and processed as double buffering. When the first RAM completed storing waveforms for a single cycle, the CIS calculation block read the waveform data from the first RAM and started calculation. The next-cycle waveform was stored in the second RAM in parallel. Therefore, the storing of the waveform and the CIS calculations were performed in parallel. In the ADC and single-cycle waveform module detection, the ADC used the Xilinx ADC (XADC) built into the FPGA. The XADC is a successive approximation register type with a 12-bit resolution, 1 mega sample per second (sampling frequency f s = 1 MHz), input voltage range of 0-1 V, and differential input, and AD conversion is possible for two channels simultaneously. v 1 (t) and v 2 (t) after AD conversion were expressed as v 1 (i) and v 2 (i). The rising edge of the waveform from negative to positive was detected by monitoring v 1 (i). Moreover, this block had a frequency counter at the detected rising edge. Thus, the fundamental frequency f 0 of oscillation waveform for a single cycle were calculated using the number of samples N during the rising edge and sampling frequency f s of the ADC (f 0 = f s /N).
Simultaneously, when a rising edge was detected, the results of ADC were stored in the RAM until the next rising edge was detected. Furthermore, v 12 (i) was calculated by subtracting v 2 (i) from v 1 (i), and it was stored in RAM at the same time as v 1 (i). Moreover, two RAMs were prepared and processed as double buffering. When the first RAM completed storing waveforms for a single cycle, the CIS calculation block read the waveform data from the first RAM and started calculation. The next-cycle waveform was stored in the second RAM in parallel. Therefore, the storing of the waveform and the CIS calculations were performed in parallel. Figure 3 shows a detailed illustration of the CIS calculation module. The CIS calculation block comprised the DFT module for v 12 (i) and v 1 (i) and the calculated . Z A and . Z x modules. In these modules, the CORDIC IP core (Xilinx Inc.) was used for the trigonometric functions (sine and cosine) and the polar coordinate transformation (Equations (13)-(18)) to calculate the amplitude and phase spectra from the DFT results.

CIS Calculation
nents required for estimation in the CIS calculation, calculating all frequency spectra is unnecessary. Thus, in the DFT definition (Equations (7) and (8)), this module calculated the real and imaginary parts (Equations (9)-(12)) in parallel by the required set Mth-order. Furthermore, the trigonometric function results were shared because they could be commonly used in calculating ( ) and 1 ( ). In the DFT calculation module, waveform data for a single cycle were read from the RAM and odd-order impedance spectra were calculated repeatedly.
was calculated based on Equations (17) and (18). These calculations were polar transformations when the real part was 1/ and the imaginary part was 2 0 . Therefore, the module was configured to perform polar transformation using the CORDIC IP core. The RA and CA were measured in advance and set external to the processor as constants in the FPGA.
was calculated based on Equations (20) and (21) using the results of the DFT and A , and the real part of (Re( )) and the imaginary part of (Im( )) at each frequency are output.

Parameter Estimation on CR Circuit Model Based on the Least-Squares Method
In the proposed method, Rx and Cx were estimated by model fitting based on the least-squares method to the real and imaginary parts of the impedance spectra. To avoid the effect of noise, the model fitting used up to the Mth harmonic component. The Rx_est that minimized JRx in Equation (24) was the estimated value of the Rx, and the Cx_est that minimized JCx in Equation (25) was the estimated value of the Cx.  Because it is sufficient to focus on the odd-order spectrum and calculate the components required for estimation in the CIS calculation, calculating all frequency spectra is unnecessary. Thus, in the DFT definition (Equations (7) and (8)), this module calculated the real and imaginary parts (Equations (9)-(12)) in parallel by the required set Mth-order. Furthermore, the trigonometric function results were shared because they could be commonly used in calculating v 12 (i) and v 1 (i). In the DFT calculation module, waveform data for a single cycle were read from the RAM and odd-order impedance spectra were calculated repeatedly.
. Z A was calculated based on Equations (17) and (18). These calculations were polar transformations when the real part was 1/R A and the imaginary part was 2πn f 0 C A . Therefore, the module was configured to perform polar transformation using the CORDIC IP core. The R A and C A were measured in advance and set external to the processor as constants in the FPGA.
. Z x was calculated based on Equations (20) and (21)

Parameter Estimation on CR Circuit Model Based on the Least-Squares Method
In the proposed method, R x and C x were estimated by model fitting based on the least-squares method to the real and imaginary parts of the impedance spectra. To avoid the effect of noise, the model fitting used up to the Mth harmonic component. The R x_est that minimized J Rx in Equation (24) was the estimated value of the R x , and the C x_est that minimized J Cx in Equation (25) was the estimated value of the C x .
In Equation (24), J Rx becomes the minimum when the derivative of R x_est becomes 0. In Equation (25), J Cx becomes the minimum when the derivative of u = 1/C x_est becomes 0.
Therefore, estimated values can be obtained by solving Equations (28) and (29): Let Z xRe and Z xIm be the real and imaginary part vectors of IS at nf 0 (n = 1, 3, 5, . . . , M). Let B Re and B Im be the real and imaginary parts of the basis vector at nf 0 . These are defined as follows: respectively. Because the model fitting was performed to odd harmonic components, B Re , B Im , Z xRe , and Z xIm were column vectors comprising m elements (m = (M + 1)/2). Equations (34) and (35) are shown below in a matrix form using Z xRe , Z xIm , B Re , and B Im .
From this matrix-form representation, the estimation values of R x_est and C x_est were calculated using the following equations, The implementation of FPGA was simplified by substituting the values of the basis matrix into Equations (36) and (37), and they could be rewritten as follows: respectively, where Z xRe i is the ith element of the vector Z xRe . The same is true for Z xIm i and B Im i . Figure 4 shows a detailed illustration of the parameter estimation on the CR circuit model. This block calculates and updates R x_est and C x_est each time the block obtains a spectral value for each frequency nf 0 (n = 1, 3, 5, . . . , M).
respectively, where is the ith element of the vector . The same is true for and . Figure 4 shows a detailed illustration of the parameter estimation on the CR circuit model. This block calculates and updates Rx_est and Cx_est each time the block obtains a spectral value for each frequency nf0 (n = 1, 3, 5, …, M).
where Rmax is the maximum value of measurable resistance and Cmax is the maximum value of measurable capacitance. The output voltage was maximum when the estimated values were Rmax and Cmax. Moreover, the measurement range could be changed by changing the Rmax and Cmax values. Second, the PDM signal converted the quantized values based on 1-bit ΔΣ modulation and outputted them to the external of the FPGA. This module primarily comprised a Q + 1 bit counter and register. The module added a quantized value and inverted MSB of the register, and MSB was outputted as the PDM signal. This module was operated at 10 MHz on the target FPGA board, where the ringing (unwanted voltage vibration) of the output waveform was slight.
Finally, the converted PDM signal was converted to an analog voltage using external CR LPF. The RLPF and CLPF were 10 kΩ and 3.3 nF, respectively. These values were adjusted so that half of the maximum output voltage of the FPGA board Vmax was outputted when 2 , half of the maximum quantization value, was inputted. The conversion from the output voltage to the estimated values of Rx and Cx could be conducted using Equations (42) and (43): where R max is the maximum value of measurable resistance and C max is the maximum value of measurable capacitance. The output voltage was maximum when the estimated values were R max and C max . Moreover, the measurement range could be changed by changing the R max and C max values.

Execution Time of the Proposed FPGA-Based Processor
The proposed FPGA-based processor conducted calculated after acquiring the oscillation waveform for a single cycle. The number of clock cycles required to obtain Rx and Cx for one frequency spectrum was 449 + N cycles. In total, 449 + N cycles were the pipeline processing, and 449 cycles were pipeline stalls caused by waiting for the calculation result in the previous stage (data hazard). At the start of the DFT calculation, stalls occurred in 255 cycles, 119 cycles for sine and cosine calculation, and 75 cycles for parameter estimation part Cx_est calculation. The total number of stalls was 449 (= 255 + 119 + 75) cycles. N was the number of samples of single-cycle waveforms. The execution time Texe of estimating Rx and Cx by odd order up to order M could be calculated using where N is the number of waveform samples and TFPGA is the reciprocal of the operating frequency of FPGA.

System Evaluation Method
The proposed FPGA-based processor was evaluated by comparing the execution time of the software program on a PC and a microprocessor. Accuracy verification was conducted by measuring metal film resistors and polypropylene film capacitors as fixed Rx and fixed Cx, and detecting the rapid optical response in resistance of a CdS photocell as time-varying impedance. In the following evaluation, we used the Z-7020 (xc7z020clg400-1, Xilinx Inc.) of the Zynq-7000 series as the target FPGA, and the FPGA board used Zybo Z7 (Digilent Inc.).

Calculation Method of the Execution Times and Other Environments for Comparison
First, the execution time of the proposed FPGA-based processor was compared with the execution time of a C program on a PC and a microprocessor. A laptop PC (32 × 22 × 2 cm) and the Raspberry Pi 4 Model B (Raspberry Pi foundation) microprocessor were used. Table 2 shows the specifications of the PC and Raspberry Pi. The C program was  Finally, the converted PDM signal was converted to an analog voltage using external CR LPF. The R LPF and C LPF were 10 kΩ and 3.3 nF, respectively. These values were adjusted so that half of the maximum output voltage of the FPGA board V max was outputted when 2 Q−1 , half of the maximum quantization value, was inputted. The conversion from the output voltage to the estimated values of R x and C x could be conducted using Equations (42) and (43):

Execution Time of the Proposed FPGA-Based Processor
The proposed FPGA-based processor conducted calculated after acquiring the oscillation waveform for a single cycle. The number of clock cycles required to obtain R x and C x for one frequency spectrum was 449 + N cycles. In total, 449 + N cycles were the pipeline processing, and 449 cycles were pipeline stalls caused by waiting for the calculation result in the previous stage (data hazard). At the start of the DFT calculation, stalls occurred in 255 cycles, 119 cycles for . Z x sine and cosine calculation, and 75 cycles for parameter estimation part C x_est calculation. The total number of stalls was 449 (= 255 + 119 + 75) cycles. N was the number of samples of single-cycle waveforms. The execution time T exe of estimating R x and C x by odd order up to order M could be calculated using where N is the number of waveform samples and T FPGA is the reciprocal of the operating frequency of FPGA.

System Evaluation Method
The proposed FPGA-based processor was evaluated by comparing the execution time of the software program on a PC and a microprocessor. Accuracy verification was conducted by measuring metal film resistors and polypropylene film capacitors as fixed R x and fixed C x , and detecting the rapid optical response in resistance of a CdS photocell as time-varying impedance. In the following evaluation, we used the Z-7020 (xc7z020clg400-1, Xilinx Inc.) of the Zynq-7000 series as the target FPGA, and the FPGA board used Zybo Z7 (Digilent Inc.).

Calculation Method of the Execution Times and Other Environments for Comparison
First, the execution time of the proposed FPGA-based processor was compared with the execution time of a C program on a PC and a microprocessor. A laptop PC (32 × 22 × 2 cm) and the Raspberry Pi 4 Model B (Raspberry Pi foundation) microprocessor were used. Table 2 shows the specifications of the PC and Raspberry Pi. The C program was created as a single-thread program operating in the same processing as the proposed FPGA-based processor. The trigonometric functions and polar transformations in the C program were cosf, sinf, sqrtf, and atan2f as single-precision floating-point format functions. The C compilers were Visual Studio Professional 2019 (Microsoft Co., Washington, DC, USA) on the PC and GCC on the Raspberry Pi. The data were obtained by saving the oscillation waveform when the measurement targets were a metal film resistor R x = 1.0 kΩ and polypropylene film capacitor C x = 10 nF using an oscilloscope (TBS2104B, Tektronix Inc., Beaverton, OR, USA). The C program was estimated from the IS data to the 19th order (e.g., the CIS calculation was repeated 10 times) using these waveform data. The execution time of the proposed FPGA-based processor was calculated using the required cycles from Equation (44). Generally, the execution time of FPGA can be measured. However, because the execution time of the proposed processor varied with the number of samples of the input-single cycle oscillation waveforms depending on the resistance of the measured object, it was difficult to perform a precise comparison for this system. Thus, to match the conditions with the comparison environments, the FPGA execution time was calculated from waveform data with the same amount of data. The execution time of the proposed FPGA-based processor was compared with the averaged values of running the C program 10 times on the PC and Raspberry Pi. Because the C program ran on the operating system, the execution time varied depending on the program running in the background. Thus, we employed the mean value repeated 10 times as the execution time.

Measuring Methods of Fixed Resistors and Capacitors
Second, the CR circuit model as a measurement object was measured using the proposed FPGA-based processor. R x had metal film resistors of 0.2 k-10 kΩ, and C x had polypropylene film capacitors of 1, 5, and 10 nF. Furthermore, the orders were set to 31st order for C x = 10 nF and 19th order for C x = 5 nF. In the C x = 1 nF, the order did not exceed 100 kHz and was adjusted. The C A was 10 pF. Furthermore, R max , which determined the measurement range, was set to 1.0 kΩ when R x was 0.2 k-0.91 kΩ, R max was set to 10 kΩ when R x was 2.0 k-9.1 kΩ, and R max was set to 100 kΩ when R x was 10 kΩ. Similarly, C max was 10 nF when C x was 1 and 5 nF, and C max was set to 100 nF when C x was 10 nF.
The analog voltages of the estimated values were measured using an oscilloscope. The proposed FPGA-based processor was estimated using four-cycle waveforms (one segment).
The measured voltages were converted to the resistance and capacitance values. These estimated values were compared with the values measured using a digital multimeter (GDM-8341, Good Will Instrument Co., Ltd., New Taipei, Taiwan).

Measuring Method of CdS Photocell for Time-Varying Impedance Measurement
Finally, an experiment similar to the impedance measurement experiment that changed with time shown in [33] was performed. The experiment involved detecting a rapid optical response in the resistance of a CdS photocell (Photocoupler LCR0203, Nantang Senba Optical and Electonic, Shenzhen, China) connected in series to a capacitor. Figure 6 shows the constant current circuit for the LED current control of the photocoupler. The CdS photocell was used as a photosensitive resistor, which was connected in series with unknown capacitance C x to the nonsinusoidal oscillator shown in Figure 1. An NJU7032D (Nissinbo Micro Devices Inc., Tokyo, Japan) was used as the operational amplifier. A 2N7000 (ON Semiconductor Co., Phoenix, AZ, USA) was used as a field-effect transistor. The combined capacitance C x = C x1 C x2 /(C x1 + C x2 ) was used as the alternative capacitance of C x1 and C x2 . C x was provided by a polypropylene film capacitor of 10 nF. We measured R x and C x when R max was set at 2 kΩ, C max was set at 100 nF, and I Ph = 0.4-10 mA by changing the V C = 0.08 to 2.0 V. Because the oscillation frequency changed near 20 kHz, the order was set to the 5th order because the frequency would be approximately 100 kHz. The R F , R A , and C A were 8.2 kΩ, 0.2 kΩ, and 0 pF, respectively. The proposed FPGA-based processor was estimated using four-cycle waveforms (one segment). The analog voltages of the estimated values were measured using the same measuring instrument described in Section 3.2. The measured voltages were converted to resistance and capacitance values.   Table 3 demonstrates the usage of the FPGA resources of the proposed processor in the target FPGA (Z-7020). Z-7020 is a model with medium-sized FPGA circuit resources, and consumed up to 73% of the LUTs among those resources. Table 3. Usage of the FPGA resources of the proposed processor in the target FPGA (Z-7020).

FPGA Resources
Available (Z-7020, xc7z020clg400-1 Table 3 demonstrates the usage of the FPGA resources of the proposed processor in the target FPGA (Z-7020). Z-7020 is a model with medium-sized FPGA circuit resources, and consumed up to 73% of the LUTs among those resources. Table 3. Usage of the FPGA resources of the proposed processor in the target FPGA (Z-7020).

FPGA Resources Available (Z-7020, xc7z020clg400-1) Utilization
Look up  Table 4 shows the comparison of execution times. The FPGA execution time was calculated using Equation ( Table 4, it became obvious that the proposed FPGA-based processor could perform 0.11 ms faster on average than the recent CPU with a clock frequency difference of ≥10 times. Moreover, the Raspberry Pi consumed 2.551 ± 0.622 ms (Min.-Max.: 1.047-3.193 ms) and took 16.6 ± 4.06 times (Min.-Max.: 6.8-20.8 times) longer than the processor. Table 4. Comparison of execution time for a single CIS when R x = 1.0 kΩ, C x = 10 nF, and M was set as 19th order *.

Environments Execution Time (ms) Ratio
FPGA-based proposed processor @150 MHz The period of oscillation waveform was 1.48 ms. Because the processing of the processor ended in a single cycle, it could output the result while acquiring the oscillation waveform. Theoretically, the lower the clock frequency, the less power is consumed. Therefore, the proposed FPGA-based processor could be expected to obtain the same response as a PC with less power than a PC. Figure 7 shows an example of the input oscillation waveforms of v 1 (t) and v 2 (t), and resulting output voltages of V Rx and V Cx from the proposed FPGA-based processor when R x = 1.0 kΩ and C x = 10 nF. The circuit parameters of R x and C x were estimated and converted to the voltages for each segment (four cycles). Because the proposed FPGA-based processor was estimated using four-cycle oscillation waveforms, the voltage waveform V Rx was changed in each segment. V Rx and V Cx were the output voltage under the measurable maximum value of R max and C max , which were set at 10 kΩ and 100 nF, respectively. V Rx and V Cx were about 330 mV. By converting from Equations (42) and (43), the estimated R x and C x were 1.0 kΩ and 10 nF, respectively. From these results, it was confirmed that the proposed FPGA-based processor could estimate R x and C x values close to the true value, and output them.  Figure 8 shows the estimated results of the metal film resistors Rx (0.2-10 kΩ) and polypropylene film capacitors Cx (1-10 nF) using the proposed FPGA-based processor. The plots and error bars in Figure 8 are the mean values and standard deviations within 100 ms obtained using the oscilloscope (12.5 k samples per second). Each figure in Figure  8 is the (a) mean estimated Rx value, (b) mean absolute error of the estimated Rx value, (c) mean estimated Cx value, or (d) relative error of the estimated Cx value, respectively. From Figure 8b, the mean absolute errors of the estimated Rx values were −150 Ω to 300 Ω. When Rx was less than 9.1 kΩ, the errors were within ±150 Ω, and when Cx was 5 and 10 nF, the errors were within ±100 Ω. When Rx was 2.0 k to 9.1 kΩ, the errors were within 5%, and when Cx was 1 nF, the errors increased to negative dozens of ohms. Furthermore, the standard deviations increased. However, the error was within ±150 Ω. When Rx was 10 kΩ, the errors increased. Because the measurement range was set at a maximum of 100 kΩ, it was considered that the tendency was different from that of other Rx values.

Measurement Results of Fixed Resistors and Capacitors
However, the mean relative errors of the estimated Cx values were −6% to +1%, and when Cx was 5 and 10 nF, the relative errors were ±1.5%. When Cx was 1 nF, the relative errors increased to −3% or above; however, the maximum range was −6% or less. Moreover, for all Cx values, the relative errors of Cx increased as Rx increased. Oscillatory voltages v input to the processor (V) Figure 7. An example of oscillatory voltage v 1 (t) and v 2 (t) being inputted into the processor, resulting in output voltages of V Rx and V Cx from the proposed FPGA-based processor when R x = 1.0 kΩ, C x = 10 nF, M was set as 19th order, R max was set at 10 kΩ, and C max was set at 100 nF. The top plot is the output of the nonsinusoidal oscillator circuit when connected to the measurement object through capacitive coupling and the input waveform of the proposed processor. v 1 (t) and v 2 (t) have nothing else to convert. The bottom two plots show the results of the R x and C x circuit parameters estimated and converted into voltages for each segment (four cycles). These voltages were converted back into estimated values R x and C x , and are shown on the right side of the y-axis as the estimated values corresponding to the voltage. Figure 8 shows the estimated results of the metal film resistors R x (0.2-10 kΩ) and polypropylene film capacitors C x (1-10 nF) using the proposed FPGA-based processor. The plots and error bars in Figure 8 are the mean values and standard deviations within 100 ms obtained using the oscilloscope (12.5 k samples per second). Each figure in Figure 8 is the (a) mean estimated R x value, (b) mean absolute error of the estimated R x value, (c) mean estimated C x value, or (d) relative error of the estimated C x value, respectively. From Figure 8b, the mean absolute errors of the estimated R x values were −150 Ω to 300 Ω. When R x was less than 9.1 kΩ, the errors were within ±150 Ω, and when C x was 5 and 10 nF, the errors were within ±100 Ω. When R x was 2.0 k to 9.1 kΩ, the errors were within 5%, and when C x was 1 nF, the errors increased to negative dozens of ohms. Furthermore, the standard deviations increased. However, the error was within ±150 Ω. When R x was 10 kΩ, the errors increased. Because the measurement range was set at a maximum of 100 kΩ, it was considered that the tendency was different from that of other R x values.  Figure 9 shows an example of the measured result for a CdS photocell using the proposed FPGA-based processor when IPh = 0.4 mA (Low) and IPh = 10 mA (High). Figure 9a shows the input oscillation waveform of 1 ( ) and 2 ( ), resulting in output voltages of VRx and VCx from the proposed FPGA-based processor. Circuit parameters of Rx and Cx were estimated and converted to the voltages for each segment (four cycles). Figure 9b shows the enlarged view near 0 μs (−1000 μs to 1000 μs) in Figure 9a. In Figure 9a, the output voltage VRx changed according to the optical response in the resistance of the CdS photocell. Furthermore, in Figure 9b, the proposed FPGA-based processor outputted the estimated values at 200-300 μs. From these results, the processor could read out the timevarying resistance Rx and the capacitance Cx independently in real-time. Figure 10 shows the resistance Rx of each IPh value for a CdS photocell during the high period using the proposed FPGA-based processor. Figure 10a shows the time-resistance curves of Rx at each IPh value, and Figure 10b shows the saturation value at each IPh value.  However, the mean relative errors of the estimated C x values were −6% to +1%, and when C x was 5 and 10 nF, the relative errors were ±1.5%. When C x was 1 nF, the relative errors increased to −3% or above; however, the maximum range was −6% or less. Moreover, for all C x values, the relative errors of C x increased as R x increased. Figure 9 shows an example of the measured result for a CdS photocell using the proposed FPGA-based processor when I Ph = 0.4 mA (Low) and I Ph = 10 mA (High). Figure 9a shows the input oscillation waveform of v 1 (t) and v 2 (t), resulting in output voltages of V Rx and V Cx from the proposed FPGA-based processor. Circuit parameters of R x and C x were estimated and converted to the voltages for each segment (four cycles). Figure 9b shows the enlarged view near 0 µs (−1000 µs to 1000 µs) in Figure 9a. In Figure 9a, the output voltage V Rx changed according to the optical response in the resistance of the CdS photocell. Furthermore, in Figure 9b, the proposed FPGA-based processor outputted the estimated values at 200-300 µs. From these results, the processor could read out the time-varying resistance R x and the capacitance C x independently in real-time. The circuit parameters of Rx were estimated and converted to the voltages for each segment (four cycles). The estimated Rx values according to the changed IPh values were observed.

Measurement Results of CdS Photocell
(a) (b)   Figure 10 shows the resistance R x of each I Ph value for a CdS photocell during the high period using the proposed FPGA-based processor. Figure 10a shows the time-resistance curves of R x at each I Ph value, and Figure 10b

Discussion
In comparing the execution times (Table 4), the proposed FPGA-based processor had the shortest execution time. The PC and Raspberry Pi could also conduct processing sufficiently briefly, indicating that the CIS method could calculate IS in the order of milliseconds. Moreover, if the C program is improved to a multithread instead of a single thread, the execution time can become even shorter. However, an oscilloscope or a data-acquisition board will be needed to obtain the oscillation waveforms using a PC; hence, the system might become large. Similarly, external equipment or an analog input circuit are necessary to obtain oscillation waveforms when using a Raspberry Pi. The execution time of the proposed FPGA-based processor depends on the time of the oscillation waveform for a single cycle. In the processor, the calculation starts after the waveform for a single cycle is saved. The most time-consuming process is DFT, which was repeated (M + 1)/2 times in the current configuration. However, each frequency component can be calculated independently and parallel in CIS calculation. Therefore, the execution time can be reduced by preparing a CIS calculation block to parallelize the calculation using a FPGA with more circuit resources. These improvements are required to support higher frequencies, which is a future study. Furthermore, as a strict comparison of execution time, it will be necessary to perform a comparison including the process of converting to an analog voltage. Figure 7 shows that the VRx and VCx oscillated ±5 mV, considered to be due to ΔΣDAC. By converting the oscillation of ±5 mV to resistance and capacitance, the resistance was ±1.52 Ω when Rmax was set at 1.0 kΩ, and the capacitance was ±0.0152 nF when Cmax was set at 10 nF. Therefore, these were errors of ±0.15%. Figure 8 shows that, when Cx was 5 and 10 nF, the mean absolute errors of the estimated Rx value were ±5%, and the mean relative errors of the estimated Cx value were ±1.5%. However, when Cx was 1 nF, these errors increased due to the increasing oscillation frequency. The oscillation frequency f0 will be high with decreasing Cx. When Cx was 1 nF, f0 was in the order of several kHz. Above the 10th order, the oscillation frequency exceeded 100 kHz, and the relative errors increased. Therefore, the order was adjusted so that the oscillation frequency was less than 100 kHz. The sampling frequency of the ADC

Discussion
In comparing the execution times (Table 4), the proposed FPGA-based processor had the shortest execution time. The PC and Raspberry Pi could also conduct processing sufficiently briefly, indicating that the CIS method could calculate IS in the order of milliseconds. Moreover, if the C program is improved to a multithread instead of a single thread, the execution time can become even shorter. However, an oscilloscope or a data-acquisition board will be needed to obtain the oscillation waveforms using a PC; hence, the system might become large. Similarly, external equipment or an analog input circuit are necessary to obtain oscillation waveforms when using a Raspberry Pi. The execution time of the proposed FPGA-based processor depends on the time of the oscillation waveform for a single cycle. In the processor, the calculation starts after the waveform for a single cycle is saved. The most time-consuming process is DFT, which was repeated (M + 1)/2 times in the current configuration. However, each frequency component can be calculated independently and parallel in CIS calculation. Therefore, the execution time can be reduced by preparing a CIS calculation block to parallelize the calculation using a FPGA with more circuit resources. These improvements are required to support higher frequencies, which is a future study. Furthermore, as a strict comparison of execution time, it will be necessary to perform a comparison including the process of converting to an analog voltage. Figure 7 shows that the V Rx and V Cx oscillated ±5 mV, considered to be due to ∆ΣDAC. By converting the oscillation of ±5 mV to resistance and capacitance, the resistance was ±1.52 Ω when R max was set at 1.0 kΩ, and the capacitance was ±0.0152 nF when C max was set at 10 nF. Therefore, these were errors of ±0.15%. Figure 8 shows that, when C x was 5 and 10 nF, the mean absolute errors of the estimated R x value were ±5%, and the mean relative errors of the estimated C x value were ±1.5%. However, when C x was 1 nF, these errors increased due to the increasing oscillation frequency. The oscillation frequency f 0 will be high with decreasing C x . When C x was 1 nF, f 0 was in the order of several kHz. Above the 10th order, the oscillation frequency exceeded 100 kHz, and the relative errors increased. Therefore, the order was adjusted so that the oscillation frequency was less than 100 kHz. The sampling frequency of the ADC caused the error because of the change in errors related to the oscillation frequency. The sampling frequency of the ADC in the current processor was approximately 1 MHz. The harmonic components analyzed using DFT were approximately 500 kHz according to the sampling theorem. However, the upper-limit frequency required to ensure CIS calculation accuracy will reduce. Therefore, improvement can be expected when using a dedicated ADC IC with a high sampling frequency and high resolution, instead of a FPGA internal ADC. Furthermore, the oscillation frequency can be decreased by increasing the R F . However, the current flowing through the measurement object would decrease with increasing resistance R F of a Schmitt trigger inverter. Therefore, the error should increase in the voltage waveform occurring in R A . The analog input circuit, sampling frequency, and ADC and DAC resolution affected the measurement accuracy of the proposed FPGA-based processor. In the DAC, improvement could be expected using a dedicated DAC IC or multibit ∆ΣDAC instead of a simple 1-bit ∆ΣDAC. These are future studies. Figures 9 and 10 show that, in the measurement of a CdS photocell, the time-varying impedance was estimated using the proposed FPGA-based processor. Furthermore, the resistance changes according to the changes in current I Ph were also measured. The estimation results were output from 200 to 300 µs. Therefore, there were 3000-5000 estimations per second. The results indicated that simultaneous measurements in real-time depended on the time-varying impedance changing with the analog voltage. Figure 9b shows that the output voltage was blunted at the transition of the estimated value because of the LPF effect of CR in the ∆ΣDAC. In the future, if the oscillation frequency becomes high, the circuit constants of the resistors and capacitances that make up the LPF must be reviewed.
The estimated frequency was approximately 100 kHz in the proposed FPGA-based processor, and it was considered almost equivalent to AD5933. However, the proposed CIS method has the advantage of measuring resistance and capacitance simultaneously. In real time, although the execution time depends on the time of oscillation waveform for a single cycle, thousands of estimates in 1 s are possible, which is considered useful. However, we consider that improvements are required for the measurable impedance range, precision, and supported frequency range.
Even in our prototype, the resistance and capacitance values were obtained from IS with a frequency of hundreds of Hz to about 100 kHz in milliseconds order, and the size was within about 20 × 20 × 3. Although the size of the prototype was a bit large, for example, it could be expected to be applied in cancer screening [34] using EIS of 100-100,000 Hz to reduce the size of the measurement system. Furthermore, since the measurement time affected the frequency of the excitation voltage, it took 100 ms or more for measurement at a relatively low frequency, such as 100 Hz. Even in a prototype, it can be expected to obtain results in a shorter time than the conventional method of switching sine waveforms.
The prototype is the first approach, and the versatility of the prototype is not high compared to that of a PC. However, in the future, for example, we would like to examine application in portable multi-channel simultaneous measurement systems and sensor modules mounted on a mobile robot system. As the number of channels increases, the amount of calculation and the processing time increase. Devices mounted on a moving robot are required to be real-time and responsive. Even in such cases, it can be expected to obtain the same performance as a PC. Furthermore, we think that our prototype will need to be enhanced in consideration of the thresholds required for real-time system operation, and tuning will be necessary when using it in real applications.
The size of this system, including the proposed FPGA-based processor, was approximately 20 × 20 × 3 cm. Because this system was a prototype, a standard and simple FPGA evaluation board without advanced external ADC and DAC ICs was used. The FPGA evaluation board was the largest in our prototype system. If a dedicated board is developed, it will be much smaller and can be used in wearable devices. It is a future task to develop a dedicated small board for miniaturization that does not fundamentally disrupt the subject's behavior in a wearable application.
The prototype can handle only one equivalent circuit. Thus, the applicable range may be narrowed. For this (lower) price, the customer will receive a narrowly specialized solution without the possibility of applying it in other areas of interest. However, an advantage of employing FPGA is that the circuit can be rewritten. The advantages of using FPGA will be demonstrated, and the usefulness of this study will be further enhanced if we increase the number of equivalent circuits that can be supported and provide a function to dynamically switch the equivalent circuit according to the measurement target. It is unnecessary to change the CIS calculation unit when changing the measurement object, and it can be handled only by changing the circuit parameter estimation unit. If these enhancements can be applied, the proposed FPGA-based processor can expect the realization of inexpensive and flexible equipment.

Conclusions
In the first approach, this study presents a dedicated processor that is implemented as a FPGA to perform CIS, estimation of R x and C x , and their digital-to-analog conversions at a certain time and to repeat them continually. Even if there is a change in the circuit model to be estimated in the future, it is possible to respond flexibly by reconfiguring the FPGAbased processor. By performing circuit parameter estimation based on IS, more detailed impedance changes for the measurement object can be monitored in real-time. Furthermore, the proposed FPGA-based processor was evaluated through three examinations. The proposed processor could execute 19th-order CIS in 0.153 ms and a whole sequence in the order of milliseconds. The execution time comparison with other environments showed that the execution time of the proposed FPGA-based processor was shorter than that of a PC and a microprocessor. Furthermore, the measurement results from metal film resistors and polypropylene film capacitors suggested that estimating the resistance R x and capacitance C x with reasonable accuracy is possible. The processor estimated fixed R x within a relative error of ±5% for the metal film resistor (2.0-9.1 kΩ) and fixed C x , and within ±6% for the polypropylene film capacitor (1-10 nF). Moreover, in the measurement of a CdS photocell, the proposed processor was detected to have a rapid optical response to the resistance of the CdS photocell. The results indicated that simultaneous measurements in real time depend on the time-varying impedance changing with the analog voltage. It is considered that the purpose of demonstrating the real-time measurability based on the novel algorithm CIS method has been almost achieved by using the prototype shown in this paper. As our prototype is a simple configuration, there is room for improvement in practicality and size.
Future studies will focus on improving measurement accuracy by improving the processor and further reducing the execution time by parallelizing the CIS block. Furthermore, we will examine application to different circuit models, and practicality and size improvements.

Data Availability Statement:
The data that support the findings of this study are available from the corresponding author, A.T., upon reasonable request.