Universal Filter Based on Compact CMOS Structure of VDDDA
Abstract
:1. Introduction
2. Proposed Universal Filter
2.1. Basic Concept of the VDDDA
2.2. The CMOS Structure of the VDDDA
2.3. The Universal Biquad Filter based on VDDDAs
- Noninverting low-pass filter with unity voltage gain is given at the output voltage node vo of the proposed filter by applying the input signal into the input voltage node vi2 while the other input voltage nodes are grounded.
- Noninverting band-pass filter with unity voltage gain is given at the output voltage node vo of the proposed filter by applying the input signal into the input voltage node vi3 while the other input voltage nodes are grounded.
- Inverted high-pass filter with unity voltage gain is given at the output voltage node vo of the proposed filter by applying the input signal into the input voltage nodes vi2, vi3 and vi4 while the input voltage node vi1 is grounded.
- Inverted band-stop filter with unity voltage gain is given at the output voltage node vo of the proposed filter by applying the input signal into the input voltage nodes vi3 and vi4 while other nodes are grounded.
- Inverted all-pass filter with unity voltage gain is given at the output voltage node vo of the proposed filter by setting gm1 = gm2 and applying the input signal into the input voltage nodes vi1, vi3 and vi4 while the input voltage node vi2 is grounded. Although it requires the matching conditions of gm1 and gm2, this is the active matching condition that is easier to control than the passive matching one.
- Inverted all-pass filter without the matching condition is given at the output voltage node vo of the proposed filter by connecting the z terminal to the p terminal of the VDDDA2, then applying the input signal into the input volage nodes vi3 and vi4 while the other input voltage nodes are grounded.
2.4. Effects of Nonideal VDDDA Characteristics
3. Simulation Results
4. Experimental Results
5. Comparison
6. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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Ref | Filtering Category | No. of VDDDA | No. of R + C | Use of all Grounded Capacitors | High Impedance of all Input Nodes | Low output Impedance for all Output Node | Electronic Tune of Q without Affecting ω0 | Filtering Functions | Constant Passband Gain during Tuning ω0 and Q for all Responses | Technology | Additional Circuit | Results | Power supply Voltages & Power Consumption* | Dynamic Range & Noise |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
[13] | MIMO | 3 | 1 + 2 | Yes | Yes | No | Yes | LP, BP, HP, BR, AP | No | 0.18 μm TSMC CMOS | No | Simulation | ±0.9 V & N/A | N/A |
[14] | MIMO | 3 | 1 + 2 | Yes | Yes | No | Yes | LP, BP, HP, BR, AP | No | 0.18 μm TSMC CMOS | No | Simulation | ±0.9 V & N/A | N/A |
[15] | SIMO | 2 | 2 + 2 | Yes | Yes | No | No | LP, BP, HP | Yes | 0.18 μm TSMC CMOS | No | Simulation | ±0.9 V & N/A | N/A |
[16] | MISO | 1 | 1 + 2 | No | No | No | No | LP, BP, HP, BR, AP | Yes | 0.25 μm TSMC CMOS | Inverting Amp. & double gain Amp. | Simulation | ±1.25 V & 1.58 mW | N/A |
[17] | SIMO | 2 | 0 + 2 | Yes | Yes | No | No | LP, BP, HP, BR | Yes | 0.18 μm TSMC CMOS | No | Simulation | ±0.9 V & 0.21 mW | N/A |
[18] | MISO | 1 | 2 + 2 | No | No | No | No | LP, BP, HP, BR, AP | Yes | 0.25 μm TSMC CMOS | Inverting Amp. | Simulation | ±1.25 V & N/A | N/A |
[19] | MISO | 2 | 0 + 2 | Yes | Yes | Yes | No | LP, BP, HP, BR, AP | Yes | Commercial ICs | No | Simulation & Experiment | ± 5 V | N/A |
[20] | SIMO | 3 | 1 + 2 | Yes | Yes | No | Yes | LP, BP, HP, BR, AP | Yes | 0.18 μm TSMC CMOS & Commercial ICs | No | Simulation & Experiment | ±0.9 V & 0.34 mW | N/A |
[21] | MISO | 3 | 1 + 2 | Yes | Yes | Yes | Yes | LP, BP, HP, BR, AP | Yes | Commercial ICs | No | Simulation &Experiment | ± 5 V & N/A | N/A |
[22] | SIMO | 3 | 1 + 2 | Yes | Yes | No | Yes | LP, BP, HP, BR, AP | No | 0.18 μm TSMC CMOS & Commercial ICs | No | Simulation & Experiment | ±0.9 V & N/A | N/A |
[23] | MIMO | 1 | 1 + 2 | Yes | Yes | No | No | LP, BP | Yes | 0.18 μm TSMC CMOS | No | Simulation | ±0.9 V & 0.73 mW | N/A |
[24] | MISO | 1 | 2 + 2 | No | No | No | No | LP, BP, HP, BR, AP | Yes | Commercial ICs | Inverting Amp. | Simulation | ±5 V & N/A | N/A |
Proposed Filter | MISO | 2 | 1 + 2 | Yes | Yes | Yes | Yes | LP, BP, HP, BR, AP | Yes | 0.18 μm TSMC CMOS & Commercial ICs | No | Simulation & Experiment | ±0.9 V & 0.99 mW | 73.27 dB & 46 µVrms |
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Jaikla, W.; Khateb, F.; Kulej, T.; Pitaksuttayaprot, K. Universal Filter Based on Compact CMOS Structure of VDDDA. Sensors 2021, 21, 1683. https://doi.org/10.3390/s21051683
Jaikla W, Khateb F, Kulej T, Pitaksuttayaprot K. Universal Filter Based on Compact CMOS Structure of VDDDA. Sensors. 2021; 21(5):1683. https://doi.org/10.3390/s21051683
Chicago/Turabian StyleJaikla, Winai, Fabian Khateb, Tomasz Kulej, and Koson Pitaksuttayaprot. 2021. "Universal Filter Based on Compact CMOS Structure of VDDDA" Sensors 21, no. 5: 1683. https://doi.org/10.3390/s21051683
APA StyleJaikla, W., Khateb, F., Kulej, T., & Pitaksuttayaprot, K. (2021). Universal Filter Based on Compact CMOS Structure of VDDDA. Sensors, 21(5), 1683. https://doi.org/10.3390/s21051683