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Technical Note

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial

ARIES Research Center, Universidad Antonio Nebrija, 28040 Madrid, Spain
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Academic Editor: Mario Marchese
Sensors 2021, 21(4), 1392; https://doi.org/10.3390/s21041392
Received: 25 January 2021 / Revised: 12 February 2021 / Accepted: 12 February 2021 / Published: 17 February 2021
(This article belongs to the Section Communications)
Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper. View Full-Text
Keywords: communication modules; emulation; fault injection debugger; FIR filter; SEM IP; SEU; Xilinx communication modules; emulation; fault injection debugger; FIR filter; SEM IP; SEU; Xilinx
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MDPI and ACS Style

Ruano, Ó.; García-Herrero, F.; Aranda, L.A.; Sánchez-Macián, A.; Rodriguez, L.; Maestro, J.A. Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors 2021, 21, 1392. https://doi.org/10.3390/s21041392

AMA Style

Ruano Ó, García-Herrero F, Aranda LA, Sánchez-Macián A, Rodriguez L, Maestro JA. Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors. 2021; 21(4):1392. https://doi.org/10.3390/s21041392

Chicago/Turabian Style

Ruano, Óscar, Francisco García-Herrero, Luis A. Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, and Juan A. Maestro. 2021. "Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial" Sensors 21, no. 4: 1392. https://doi.org/10.3390/s21041392

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