Next Article in Journal
Event-Driven Data Gathering in Pure Asynchronous Multi-Hop Underwater Acoustic Sensor Networks
Next Article in Special Issue
Fast Approximations of Activation Functions in Deep Neural Networks when using Posit Arithmetic
Previous Article in Journal
Feasibility of Social-Network-Based eHealth Intervention on the Improvement of Healthy Habits among Children
Previous Article in Special Issue
Distillation of an End-to-End Oracle for Face Verification and Recognition Sensors
Article

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis

Department of Electronics and Telecommunication (DET), Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Turin, Italy
*
Author to whom correspondence should be addressed.
This paper is an extended version of our paper published in Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2019.
Sensors 2020, 20(5), 1405; https://doi.org/10.3390/s20051405
Received: 30 January 2020 / Revised: 24 February 2020 / Accepted: 28 February 2020 / Published: 4 March 2020
In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding (HEVC) standard, which represents the state of the art in video coding standards. Nevertheless, in the last years, new algorithms and techniques to improve coding efficiency have been proposed. One promising approach relies on embedding direction capabilities into the transform stage. Recently, the Steerable Discrete Cosine Transform (SDCT) has been proposed to exploit directional DCT using a basis having different orientation angles. The SDCT leads to a sparser representation, which translates to improved coding efficiency. Preliminary results show that the SDCT can be embedded into the HEVC standard, providing better compression ratios. This paper presents a hardware architecture for the SDCT, which is able to work at a frequency of 188 M Hz , reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz , which is one of the best resolutions supported by HEVC. View Full-Text
Keywords: video coding; discrete cosine transform; directional transform; VLSI video coding; discrete cosine transform; directional transform; VLSI
Show Figures

Figure 1

MDPI and ACS Style

Peloso, R.; Capra, M.; Sole, L.; Ruo Roch, M.; Masera, G.; Martina, M. Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis. Sensors 2020, 20, 1405. https://doi.org/10.3390/s20051405

AMA Style

Peloso R, Capra M, Sole L, Ruo Roch M, Masera G, Martina M. Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis. Sensors. 2020; 20(5):1405. https://doi.org/10.3390/s20051405

Chicago/Turabian Style

Peloso, Riccardo, Maurizio Capra, Luigi Sole, Massimo Ruo Roch, Guido Masera, and Maurizio Martina. 2020. "Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis" Sensors 20, no. 5: 1405. https://doi.org/10.3390/s20051405

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop