## 1. Introduction

The adjustable current amplifiers [

1,

2] have significant application over many electronic circuits and systems. Several interesting solutions have been introduced during the last decades as shown in comparison

Table 1. The development of these devices goes in parallel with development of so-called current conveyors (CC) and their adjustable features [

2]. The first attempts were evaluated in works [

3,

4] as parts of CCs (partial two-port transfer available by the device). Both cases implement a ratio of two bias currents for current gain adjustment. This way of adjustment is used very often also in further solutions. More advanced devices were proposed in [

5,

6,

7,

8,

9,

10,

11,

12,

13,

14,

15,

16,

17,

18,

19,

20] for example. They offer interesting features discussed in detail in

Table 1 Work [

8] presents current amplifier feature allowing gain setting by ratio of resistors (no electronic adjustment is shown). However, this concept of current gain setting (unfortunately of the fixed value) is also possible. This can be extended to adjustable control through the replacement of passive element (appropriate replacement is a digital potentiometer or linear operational transconductance amplifier). Many concepts intend digital adjustment of the current gain [

5], [

14,

15,

16,

17] that is useful for direct cooperation with microprocessors. However, continuous adjustment of the gain is more beneficial for many applications (smooth tuning of filters or automatic amplitude stabilization in oscillators [

18]).

Table 1 shows that the majority of solutions is based on bipolar junction transistors, exploiting the benefit of exponential characteristics specially in the accurate current multipliers discussed below. These bipolar topologies meet well the requirements for the exact functionality, good dynamic range and speed (commonly in tens of MHz and more), but at the cost of a large area and current consumption (standardly not mentioned), which is no longer acceptable in the small CMOS technologies [

3,

4,

7,

9,

10,

11,

12,

16,

17]. A large number of previous concepts (CMOS especially) was not tested experimentally, mostly just simple simulation results are shown (without modeling of real effects in many cases) [

5,

6,

7,

8,

10,

11,

13,

14,

15,

17]. Very high input impedance (DC resistive component) as well as low output impedance indicate significant drawback of many previous solutions. Special cases are the solutions presented in [

7,

15]. However, the adjustability of any parameter, but especially the gain, can be often welcomed for electronic tuning of applications in many cases [

12,

13,

16,

17]. The output impedance of current output circuits is the most significant issue because of the parasitic behavior occurring in high-impedance nodes of applications (typically in active filters [

9]). We can see that situation of state-of-the-art is insufficient in many BJT-based cases [

9,

11,

15,

17]. The CMOS-based topologies have significantly better output features, see [

21,

22]. Work presented by Esparza-Alfaro [

21] demonstrates a concept using two CCs and resistor feedback for current gain setting.

The current-mode multipliers are important for our discussion due to similarity of newly proposed concept also using principle of two-quadrant multiplier. Comprehensive comparison [

28,

29,

30,

31,

32,

33,

34,

35,

36,

37,

38,

39,

40,

41,

42,

43,

44,

45,

46,

47,

48,

49,

50,

51,

52,

53,

54,

55,

56,

57,

58,

59,

60,

61,

62,

63,

64,

65,

66,

67,

68] in

Table 2 indicates missing details and incomplete topologies for full implementation in current multiplication or amplification because structures are not designed as fully symmetrical form. They operate with intentional superposition of DC component or principal topology, not including all important parts, in order to obtain behavior required in this work. However, many works [

31,

33,

47,

60,

67,

68] use single or two partial active devices (specified types of current conveyors) in design of current-mode multipliers and fully symmetrical operation (processing of both signal polarities) is easily possible in this form. Usage of OTA-based structures seems to be also very interesting in these nonlinear designs [

32,

39,

44]. It offers building blocks for many nonlinear functions [

69]. Logarithmic-domain-based structures are also known in reported concepts [

32]. Also, concepts combining conveyors and operational transconductance amplifiers are known [

34,

64]. There are many possible design approaches exist. However, each of them can be used differently for various purposes and requirements on resulting circuit and application.

Many works from

Table 2 suffer from very limited input range of current (below 100 µA), some solutions operate even in nA range that is really insufficient in many practical cases. Despite extremely low power consumption, there are issues with noise and bandwidth limitations. Advantages of the newly proposed solution include quite large input range of linearity ±200 µA (in comparison with other works in

Table 2), very low total harmonic distortion (THD) below 0.25%, extremely low input resistance (below 2 Ω), very high output resistance (4 MΩ), and beneficial power consumption. The linearity error is expressed as the ratio error between the maximum and minimum value of the parameter obtained by derivation of the transfer function in the given linearity range and was measured below 6% for the presented circuit. There are solutions having even lower power requirements, unfortunately, there are costs (bandwidth, input range, DC accuracy, etc.) for such benefit in corresponding works. Unfortunately, many detailed parameters of compared solutions are unknown.

As the objective of this work, the precise highly linear current amplifier has been requested for measurement applications handling current signal, conveniently in current sensor processing circuits, especially for the smart sensor ASIC measurement solution. Currently, the main intended usage of the circuit is an automatic gain control current amplifier for precise harmonic reference generator used in Capacitive sensor measurement. The similar solution of the precise sinus reference source like in [

70] is assumed to be used and is just under development. While, the referenced circuit is based on the digitally generated voltage reference signal with tunable low-pass filter, the new solution uses the current reference generator, with fixed frequency filter, followed by the current amplifier with gain controlled by the similar principle as is described in the paper [

70]. Due to the demand of the supposed capacitive measurement method, this amplifier was developed serving the very low THD as the main parameter because of the assumed derivative signal processing, emphasizing any higher harmonic components of the reference signal.

Furthermore, many modern sensor applications use a high-quality ADC for digitization of the signal where any signal distortion during the analog pre-processing degrades the performance of the ADC.

Generally, this type of circuit is especially suitable to realize tunable multi-output current-mode generators as well, where good accuracy and low THD is also requested. Amplitude modulation of the current signal is another tailor-made application for the presented circuit. However, the designed amplifier prototype has been optimized for use in precise measurement applications processing high current signals.

With respect to the intended application requirements an objective of the work was to develop and design an adjustable accurate current amplifier for current sensor signal processing, and other precise current measurement application, having fulfilled these features simultaneously:

- (a)
low total harmonic distortion of the processed current signal as the most considered parameter (<1%)

- (b)
wide and linear input range (about ±200 µA)

- (c)
very low input resistance (<10 Ω)

- (d)
high output impedance (>1 MΩ)

- (e)
adjustability of current gain (theoretically 0–2)

- (f)
high linearity of the gain control for current gain B < 0.8

- (g)
acceptable power consumption (comparing to the process signal current) below 5 mW

## 2. Circuit Principle and Design

Considering all requirements, the idea of the classical quadratic current multiplier topology was rejected mainly because of the high linearity (low THD) demand, simultaneously with wide input range and lower current consumption. With an experience with design of linear or trans-linear circuits using modular approach for compiling the convenient blocks we decided to build-up the current amplifier from a highly linear transimpedance stage, followed by the tunable transconductance stage, both exploiting MOS transistors in their linear region. To meet the requirement of low input impedance a feedback topology based on the differential Miller-OTA amplifier was used. Unfortunately, this solution reduces the frequency bandwidth of the final circuit, but sufficient for many sensor measurement applications. A principal topology of the presented circuit is shown in

Figure 1.

The operational amplifier structure at the input provides low impedance for input current I(in). The input current is then copied to the output of the block. In fact, this input block works as a current conveyor CCII. The conveyed input current is converted to two differential currents in differentiator and lowered by factor 4 because of lowering current consumption and transistor area. All the procedure is made by the high accuracy and high output impedance cascoded current mirrors. Differential currents flow to the fixed impedances created by NMOS transistors. As obvious, playing with V_{ref} brings the other degree of freedom to set gain. As it can come with degradation of linearity for unadvised large changes and is not necessary, it stays fixed in the presented design. Voltage signals at the outputs of the transimpedance stage are then processed by the adjustable gm stage. All parts have been designed with maximum respect to linearity and accuracy. Although, the transconductance output stage gives its best THD parameter in the differential connection, therefore the differentiator and differential transimpedance stage was used.

#### 2.1. Input Stage and Transimpedance Stage in Detail

The target of this block is to provide low impedance current input and then transfer the input current to defined impedance where it is converted to the voltage driving the following transconductance stage.

The main requirement for the transimpedance stage is to make this conversion as much linear as possible but conveniently also dual to the transconductance stage in the sense of the total amplifier gain stabilization with respect to manufacture and temperature corners. Considering utilization of the NMOS transistor as the active component in the transconductance stage, it has been used also here. As long as the main components of both stages have the same technology parameters (mainly ${K}_{PN}={\mu}_{N}.{C}_{OX}$) and temperature characteristics, the effect of corners is minimized.

The full principle turns around the generally known equation for MOS transistor working in the linear region, mentioned in (1),

from which, by solving the quadratic equation, we obtain,

Derivation according to

I_{D} gives the

R_{DS} value of the MOS serving as the resistor,

From Equation (3) there it is obvious that the

R_{DS} is dependent on the

I_{D}. For good linearity it is necessary to keep

$2.\frac{{K}_{PN}W}{L}.{I}_{D}$ much smaller than

${\left[\frac{{K}_{PN}W}{L}.\left({V}_{GS}-{V}_{TH}\right)\right]}^{2}$. Satisfying that condition requires high

V_{GS} and low

I_{D} and brings linear MOS transistor resistance of the “ideal” value:

Unfortunately, when reasonably high current is processed by this way then it is very difficult to keep linearity under 10%. On the other hand, if the differential topology is used at the cell output, the differential output voltage

V_{PN} =

V_{ZP} −

V_{ZN} corresponds to the sum of both linear MOS resistances. However, when

I_{D} current increases through one of them, as a result of the input current change, the second one decreases simultaneously. It suppresses the parasitic non-linear phenomenon significantly. With respect to the developed presented topology the

I_{D} current in (3), flowing through the linear transistors, is represented by some part of input current added to and/or subtracted from a pre-biasing current respectively in the individual branches. Considering that the input current

I_{IN} is reduced 4 times (lower consumption as well as the non-linearity effect) the differential transimpedance exhibits value,

with opposite effect of the parasitic part for each linear MOS resistance. The graphic solution of this effect is presented in

Figure 2.

Now there is seen that the non-linearity reduction depends on the ratio of the fixed part of the equation ${\left[\frac{{K}_{PN}W}{L}.\left({V}_{GS}-{V}_{TH}\right)\right]}^{2}-2.\frac{{K}_{PN}W}{L}.{I}_{BIAS}$ and the input current dependent part $2.\frac{{K}_{PN}W}{L}.\frac{{I}_{IN}}{4}$. The I_{BIAS} current should be designed as small as possible to maximize the fixed part of the transimpedance. In the presented circuit the I_{BIAS} = 50 µA and then the appropriate currents through each transistor vary in range (0 ÷ 100) µA.

The final schematic of the presented input transimpedance stage is shown in

Figure 3. The low input I

_{IN} impedance is satisfied by operational amplifier consisting of M

_{1}–M

_{4}, M

_{59} with follower M

_{19}, working in the unity feedback. M

_{9} senses the input current change (as the difference of fixed current of bias source M

_{60}, while M

_{5} makes some small pre-bias due to linearity) and mirrors it by factor 1/4 to current sources M

_{10}, M

_{11}. While M

_{11} sources the current directly to transimpedance transistor M

_{64}, the second transimpedance transistor M

_{63} is sourced by the complementary current. The output differential voltage

V_{PN} is taken between the terminals Z

_{P} and Z

_{N}. The realized circuit differs only in matters of ESD protection.

As the sensed input current has been decreased by factor 4 before it is applied to the transimpedance transistors M

_{63}, M

_{64}, because of the linearity demand discussed above, then the same factor must be included in the full circuit transimpedance gain equation. The differential output voltage of the whole input transimpedance block is then ideally:

The differential transimpedance gain of the realized circuit is calculated as R

_{TIG} = 2400 Ω.

Figure 4a presents the simulated output voltages

V_{ZP} and

V_{ZN} together with differential output voltage

V_{PN} as the functions of the input current

I_{IN}. Derivations of these voltages according to input current, representing the transconductance gain of the whole block, are presented in

Figure 4b. The red dashed line represents the transconductance gain of the Z

_{P} output branch re-calculated to the differential transconductance gain. Then, it corresponds to

Figure 2, considering the factor 4. Due to the differential topology the linearity error is decreased from approx. 28% at one transistor to 2.8% in differential signal.

#### 2.2. Tunable Transconductance Stage

As the base topology for the transconductance stage the circuit presented and thoroughly discussed in [

71] has been used in its differential connection. This introduced topology was improved, compared to the original version, in tunability, current output impedance and in linearity of the regulation as well. All these improvements have led to the circuit introduced in

Figure 5.

The circuit operation consists of a differential connection of two transconducting transistors M_{72}, M_{69} working in their linear region. It means, they both work according to the Equation (1) as well. From that equation can be seen that if V_{DS} is kept constant then the drain current I_{D} is controlled just by V_{GS} of the transistor with strongly linear dependence, called transconductance gm. The transconductance is then adjusted by V_{DS} as a parameter.

Drain to source voltage

V_{DS} across these transistors must be kept low to stay in triode operation and is equal to the difference between the overdrive voltages of transistors M

_{53}, M

_{52} (and M

_{49}, M

_{48} respectively), which both work in their saturation region and draw a constant current. The feedback loop consisting of transistors M

_{53}, M

_{52} and M

_{47} (and M

_{49}, M

_{48} and M

_{46}) keeps the voltage

V_{DS} of the main M

_{72}, M

_{69} transistors constant when an input signal is applied [

71]. Despite this topology there stays a parasitic effect of the small

V_{DS} variation (contemplating the branch of M

_{72} for instance) caused by

V_{GS} shift of M

_{47} due to the

I_{D} modulation. It corresponds to the M

_{47} transconductance and is compensated by the feedback loop gain. In case of infinity feedback gain the error is zero. Inspecting the real ∆

V_{DS} of M

_{72}, we get,

where

r_{d} is a dynamic impedance of the net of M

_{52} drain and together with transconductance of that transistor they define the feedback gain. As it should be kept high the lower currents and long channels of the connected transistors are recommended.

In the presented case of the differential topology usage the equation for transconductance stage output current is then as follows, assuming

V_{INdiff} is the differential input voltage of the stage,

| | |

| Linearity error | |

with

${A}_{FBloop}=gm\left({M}_{52}\right).{r}_{d}$ (and complementary about M

_{49} in the opposite branch too) as the gain of the closed feedback loop that regulates voltage across the main linear transistors as it is set by difference of the M

_{53} and M

_{52} drain-to-source voltages. The respective

r_{d} is dynamic impedance of the nets where drains of M

_{52} (M

_{49}) are connected to and can be calculated as the parallel connection of all impedances connected to that net. For the discussed case it can be expressed as the appropriate MOS transistors output impedance combination like

${r}_{d}\left(M52\right)=\frac{{r}_{DS}\left(M52\right).{r}_{DS}\left(M17\right).{r}_{DS}\left(M29\right)}{{r}_{DS}\left(M17\right).{r}_{DS}\left(M29\right)+{r}_{DS}\left(M52\right).{r}_{DS}\left(M29\right)+{r}_{DS}\left(M52\right).{r}_{DS}\left(M17\right)}$.

The deliberation of the Equation (8) gives us the recommendations for design to minimize the linearity error. For the best linearity result we need to keep V_{GS} of the M_{72}, M_{69} high and their V_{DS} sufficiently low to keep these transistors in true linear region. Simultaneously the high gm of M_{47}, M_{46} is convenient as well as the feedback gain A_{FBloop}.

In [

71], just modifying the current through M

_{52} (M

_{49}) causes the

V_{DS} of M

_{72}, (M

_{69}) change and in this manner it allows to tune transconductance parameter

gm of the circuit. Unfortunately, the higher tunability needs a high range of the control current within which tuning nonlinearity comes. The presented improved transconductance circuit changes both appropriate currents differentially, through current sources consisting of M

_{73}, M

_{74}, M

_{30}, M

_{29} (and M

_{67}, M

_{68}, M

_{23}, M

_{24} in the opposite branch) which increase/decrease the current in both transistors, setting the ∆

V_{DS} across the main linear MOS. It brings high

gm tuning range as well as linearity of the control with lower control current

I_{CTRL} amplitude. Another improvement was done in the output stage to increase current output impedance by cascoded mirror as well as input level-shifter adapting circuit to the more convenient input range and setting the higher quiescent

V_{GS} of the M

_{72}, M

_{69} to ensure the linear region.

## 4. Discussion

The careful circuit analysis confirms that the newly developed modular topology of the designed tunable amplifier, working internally on the not very common fully linear principle, can be used with very interesting results. The good accordance between simulation results and measurement speaks about robustness of the introduced topology and of the whole design, as well. Acceptable deviations of measurements from simulations (decreasing gain and input range slightly but always in technology defined corners) are most likely caused by smaller internal bias against the ideal one. Moreover, the experimental measurement is influenced by increasing terminal and nodal parasitic capacities of ESD structures and PCB (approximately 10 pF), especially concerning the frequency response.

By observing the comparison

Table 1, we can state that the presented circuit is almost the best one between the referred adjustable amplifiers in the maximum THD parameter. Only [

14] reports lower harmonic distortion together with low power consumption, but with the digitally controlled topology, undefined input current range and even with purely theoretical results. Although the THD parameter is usually not the most important one for the amplifiers, it is reported only in limited number of publications. It can be seen that the discussed circuit is very good in the input/output impedance values and is at least well-comparable with other CMOS amplifiers regarding the input current range. In contrast, the BJT solutions are invincible in the input range and frequency bandwidth. However, their input/output impedances make them often unusable in the current mode signal processing chain for the precise measurement and their power consumption is not specified in the referred papers.

As could be expected in

Table 2 comparing the current multipliers, much more references can be found stating the value of harmonic distortion. From this group only two circuits report slightly lower THD parameter than the presented one. The CMOS circuit from [

65] also boasts the slightly better bandwidth and power consumption but its input current range is significantly lower. Furthermore, the terminal impedances are not reported. As the second one, the bipolar solution from [

39] simultaneously shows significantly higher input range and bandwidth. This bipolar circuit was not realized and its impedances are not reported in the paper.

Even though the analyzed input offset is not really stunning, the presented circuit could be one of the better ones between current mode circuits with respect to precision. Unfortunately, there is no relevant comparison because most publications do not address this parameter. Furthermore, using an ADC in the modern sensor applications allows to easily subtract the DC offset from the signal. In that case the precise linearity is probably the most important parameter.

Despite the fact that this presented prototype was optimized especially for good linearity and accuracy properties, with the modified design it can be conveniently used in a wide range of applications from filters, precise generators to any signal processing where the signal multiplication is demanded. Specially in comparison with usual quadratic or exponential multiplier topologies it is able to report very good ratio of linear input range and power consumption.

The authors expect that the presented circuit is going to be beneficial in the field of sensor measurement and it could bring a little bit different approach to design of the precise adjustable circuits.