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Article

A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

Faculty of Electronics, Gdańsk University of Technology, 80-233 Gdańsk, Poland
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Author to whom correspondence should be addressed.
Sensors 2020, 20(11), 3303; https://doi.org/10.3390/s20113303
Received: 7 May 2020 / Revised: 4 June 2020 / Accepted: 8 June 2020 / Published: 10 June 2020
(This article belongs to the Section Biomedical Sensors)

Abstract

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.
Keywords: very low frequency; operational transconductance amplifier (OTA); biomedical sensor interface; biomedical electronics; low-voltage low-power electronics; CMOS very low frequency; operational transconductance amplifier (OTA); biomedical sensor interface; biomedical electronics; low-voltage low-power electronics; CMOS

1. Introduction

Operational transconductance amplifiers (OTAs) with a very low conversion ratio of 10−11 to 10−7 A/V (hereinafter referred to as low-transconductance amplifiers, LTA) are used in analog pre-processing of very-low-frequency biomedical signals. Before digitalization, the analog biomedical signal is amplified and pre-filtered as illustrated in Figure 1 [1,2,3,4,5]. First, the signal is amplified by a low noise amplifier (LNA). Then, the signal amplitude is corrected by a variable gain amplifier (VGA) in order to make it suitable for the input of an analog-to-digital converter (ADC). The analog filter reduces the bandwidth to minimize signal distortion that results from the aliasing effect. LNA, VGA and the filter constitute an analog front-end. It should be noted that the filter does not have to be implemented as an individual block. Instead, the filtering component can be embedded into LNA and VGA through the limitation of their bandwidth [1,6].
The amplitude of biomedical signal ranges from a few µV to several tens of mV, and its frequency is from 0.01 Hz to 3 kHz [6]. To achieve optimal processing dynamics, the front-end is integrated with ADC in a single chip. However, the integration of low-frequency circuits is a challenge. The corner frequency is associated with the RC-time-constant, i.e., f ≈ 1/(2πRC). In a typical CMOS process, resistors can be made of polysilicon with a resistivity of 103 Ω/square, and capacitors made of polysilicon-insulator-polysilicon or metal-insulator-metal layers with a unit capacitance of 10−15 F/µm2. Due to large area requirements, the practical values of the resistances and capacitances in integrated circuits are R < 100 kΩ and C < 100 pF, whereas the corresponding corner frequency is f > 15 kHz. For further reduction of frequency, the RC-time-constant can be increased using active techniques such as the capacitance multiplication and resistance emulation. Examples of using the capacitance (Miller’s) multiplication in front-ends can be found in [1,7]. However, the majority of the available literature focuses on LTA-based emulation of large resistances [2,3,8,9,10,11,12,13,14,15,16,17,18]. LTAs emulate resistors as large as 107–1011 Ω while occupying a reasonable area of 0.01 mm2 to 0.1 mm2 [2,3,8,9,10,11,12,13,14,15,16,17,18]. However, when compared to passive components, the performance figures of active resistors such as linearity, temperature stability and noise are worse. Improvement of these parameters is one of the main goals of contemporary research studies [12].
This work presents an innovative LTA that is developed and manufactured in a 0.18-µm CMOS technology at the Taiwan Semiconductor Manufacturing Company (TSMC). LTA uses the so-called Early effect (channel-length-modulation effect) in a field effect transistor (FET) to directly emulate high resistance. The relationship between the output current and the input voltage of LTA is linear from the ground to the supply voltage. The circuit design is relatively simple and does not require special optimization. Owing to the use of sub-microwatt power consumption and 1-V supply, it is suitable for use in low-power low-voltage biomedical interfaces. The following chapters present the operating principle, circuit details, theoretical analysis and prototype measurement results.

2. Voltage-to-Current Conversion Using Channel-Length-Modulation Effect

2.1. Operation Principles

The proposed voltage-to-low-current converter is shown in Figure 2a. The conversion mechanism is the same as in [18]; however, the proposed converter circuit is improved so as to support operation with low-supply voltage. Furthermore, the structure can be rail-to-rail driven.
The input signal is ∆Vi and the output signal is ∆I. Here, saturation of all transistors is assumed. The transistor M1 is a DC current source that is generating the bias current IBIAS. M2 is a bulk-driven voltage follower. It transfers ∆Vi from the bulk of M2 to the drain of M1 with a factor of about 0.25 V/V. The deviation in the drain current of M1 caused by the channel-length-modulation can be expressed as follows:
ID1 − ∆ID1 = IBIAS − ∆I = IBIAS(1 + λpVSD1) = IBIAS(1 + λp(∆VDD − ∆VD1))
where λp is the channel-length-modulation factor in a p-channel device for given channel length. The deviation of current can also be calculated using an alternative formula.
ID1 − ∆ID1 = IBIAS − ∆I = IBIAS(1 + ∆VSD1/(VEpL1)) = IBIAS(1 + (∆VDD − ∆VD1)/(VEpL1))
where VEp is the p-channel devices Early voltage per unit-channel-length [19], and L1 is the length of the M1 channel.
Assuming ∆VD1 ≈ 0.25∆Vi and ∆VDD = 0, the I-V conversion factor, defined as transconductance Gm = ∆I/∆Vi, can be simply calculated from Equation (1) or (2):
Gm = ∆I/∆Vi ≈ 0.25·IBIAS·λp
Gm = ∆I/∆Vi ≈ 0.25·IBIAS/(VEp·L1).
When M1 and M2 are saturated, Equations (1)–(4) are valid regardless of the inversion levels in M1 and M2. However, to achieve Gm of the order of 10−9 A/V, the inversion levels of M1 and M2 should be weak or at most moderate. The selected operating points, shown in Figure 2a, ensure the proper transistor operating range for the standard 180-nm CMOS process. For example, transistors with L1 = 200 nm, VEp = 8.8 V/µm and IBIAS = 10 nA will give Gm ≈ 1.4 nA/V (1.4 nS).
The resistance seen from the M2 source is much smaller than the output resistance of M1; thus, ∆I is entirely transferred from the M1 drain to the converter’s output (out). Next, ∆I is reflected in a current mirror, part of which is the diode-connected transistor M3.

2.2. Robustness to Unfavorable Factors

As long as FET remains saturated, the channel-length-modulation effect in FET is linear over a wide range of operating points [20]. Therefore, the impact of undesirable effects, such as transistor mismatch, tolerances of the manufacturing process or temperature variations on the linearity of the converter, are limited. Notwithstanding, the mentioned factors affect the Gm through changes of IBIAS, λp (or VEpL1) and the follower’s gain (factor 0.25). However, measurements of the prototype converter show that the real value of Gm differs from a predicted value by about only 10%.
Another aspect that requires detailed analysis involves the demonstration of the effect of temperature on Gm. The increase of the current in M1 (∆I) is equal to the product of the drain voltage increase (∆VD1) and the drain-source conductance (gDS1), i.e., ∆I = ∆VD1 · gDS1. The conductance gDS1 = IBIAS/(VEpL1) results from the effect of channel length modulation. Hence, Gm can be expressed by the formula that is more accurate than Equation (4), i.e.,
G m = Δ I Δ V i = Δ V D 1 Δ V i g D S 1 = Δ V D 1 Δ V i I B I A S V E p L 1
Here, VEp and L1 do not depend on the temperature, whereas IBIAS can be stabilized. The only temperature dependent factor in Equation (5) is ∆VD1/∆Vi, i.e., the gain of the M2 follower. It can be determined as
Δ V D 1 Δ V i = g m b 2 g m b 2 + g m 2 + g D S 2 + g D S 1 + g D S 1 g D S 2 g m 3 + g D S 3 1 g m 2 g m b 2 + 1     0.25
where gm2 and gmb2 are the gate and bulk transconductances of M2, respectively.
Using the detailed formulas of [20], one can show that the dependence of the gm2/gmb2 ratio on temperature is relatively weak. This implies that for stable IBIAS in the M1-M2-M3 branch, Gm does not depend on temperature.

3. Low-Gm OTA (LTA)

Based on the two converters from Figure 2a, an amplifier with differential input was developed (cf. Figure 3). The currents ΔI+ and ΔI from the two converters flow to the amplifier’s output (out) through two independent tracks. In other words, ΔI+ flows in the non-inverting path containing one mirror composed of the transistors M3+ to M6+. The ΔI flows through the inverting path containing two mirrors formed by transistors M3− to M11−. All mirrors have a 1:1 ratio.
The amplifier’s transconductance for differential input (Gm,diff) is exactly equal to Gm, i.e.,
G m , d i f f = Δ I o u t Δ V i , d i f f = Δ I + Δ I Δ V i + Δ V i = G m Δ V i + G m Δ V Δ V i + Δ V i = G m .
The output conductance of the amplifier (Gout) should be much smaller than Gm, i.e., Gout << 1 nS. This was achieved by using long-channel transistors and cascodes. The cascodes consisting of n-channel transistors are biased by VG3,6. The latter is generated by the M12−M16 branch. The “p-channel” cascodes are biased by the VG8,11 generated by M7−. All transistors in Figure 3 are standard 1.8-V thin-oxide with nominal-threshold-voltages of 0.42 V and −0.5 V for n-channel and p-channel transistors, respectively. Transistors’ dimensions (width/length expressed in µm/µm) are given in the schematic, whereas the rationale behind selecting specific dimensions is explained in Section 4.2. The schematic also shows the DC bias voltages at VDD of 1 V. Two capacitors of C1 attenuate a possible overshoot in the step transient response of the source followers M2+ and M2− [21]. A real pole (p) due to the parallel combination of C1 and gm4 (i.e., pgm4/C1) cancels a zero (z) due to Csb2 and gmb2 (i.e., zgmb2/Csb2) in M2+ and M2−. A capacitor of C2 is a “by-pass” for an AC current flowing through the bias transistor M7−. It should be emphasized that these capacitors are not critical elements and have been added to the prototype circuit for research purposes only.
Figure 4 shows a selected fragment of a prototype microchip that embeds LTAs. The size of a single LTA (marked using a white rectangle) is 174 µm × 156 µm. The capacitors, located close to the microstructure surface, are clearly visible. There are two 12-picofarad capacitors, each of which is composed of 10 smaller capacitors (two arrays of capacitors, each of which contains 10 components), and one 970-femtofarad capacitor (small array consisting of 2 capacitors).

4. Performances of the Prototype

4.1. Linearity of Current-Voltage Characteristics

The linearity of current-voltage characteristics was measured for unfavorable asymmetrical excitation when the input Vi+ was fixed at a constant potential of 0.5 V, and while the Vi− was swept from 0 V to VDD = 1 V. The measured DC characteristics Iout vs. Vi− for several values of the IBIAS source ranging from 5 nA to 50 nA are plotted in Figure 5a. The characteristics obtained from the pre-production simulation (dashed lines) are also shown.
To calculate a linearity error of the measured Iout vs. Vi−, the ideal responses were first obtained using the linear regression and the least squares method. Next, the linearity error was calculated as the difference between the measured Iout and the corresponding ideal Iout divided by a full range of Iout values, i.e., (Iout,measIout,ideal)/Iout,full-range. The calculated results (expressed in percent) were plotted in Figure 5c. The obtained error values are relatively low and range from −1% to +1.5% max. The curvature of the Iout vs. the Vi− plots is better visualized using derivatives dIout/dVi, as shown in Figure 5b.
The value of dIout/dVi at 0.5 V is equal to the nominal transconductance of the amplifier, i.e., Gm = dIout/dVi|Vi = 0.5. The nominal Gm can be tuned from 0.62 nA/V to 6.28 nA/V by changing the source IBIAS from 5 nA to 50 nA. The percentage difference between dIout/dVi and the target Gm (i.e., the Gm-deviation error) is at most ±12% over an entire (rail-to-rail) input range. Detailed plots of the Gm deviation error are in Figure 5d.
The amplifier was also tested for harmonic distortion. The results of measuring the harmonic content in Iout for 1-kHz sinusoidal excitation are shown in Figure 6. The THD reaches 0.8% for the maximal Vi− of 1 Vpp.
Clearly, nonlinearities are smaller when both inputs of the amplifier are driven symmetrically, as such a configuration ensures the highest suppression of even harmonics. It should be emphasized that in practice, an input differential signal, (Vi+Vi−), is never balanced in amplifier applications with a non-differential output. However, it is worth providing results for a symmetrical excitation, because the circuit in Figure 3 can be easily equipped with a second output and adapted to “fully-balanced” applications. With symmetrical excitation with a maximum value of Vi+Vi = 2 Vpp, THD reaches only 0.18%. The Gm,diff deviation is ±1.5% over the 2-Vpp input range. Detailed plots of the derivative dIout/(dVi+ − dVi) are in Figure 7a, and the corresponding plots of the Gm,diff deviation error are in Figure 7b.
It should be emphasized that the prototype amplifier features better linearity than predicted by the simulations. This is clearly visible in Figure 5b in the area for Vi− < 0.2 V (see also Figure A1 and Figure A2 in Appendix A). The bulk-effect (body-effect) in FET is not accurately modelled for the low potentials of bulk.

4.2. Frequency and Noise Characteristics

A small-signal transconductance was measured in the range of 1 Hz–200 kHz. Measurements were performed separately for each of the inputs. Figure 8a shows the results only for the Vi− input, because this is the worst case in terms of frequency properties (because the inverting track is longer than the non-inverting track). The values of Gm for the considered frequencies are consistent with the values of dIout/dVi at Vi− = 0.5 V obtained from the DC measurements shown in Figure 5b. The measured −3-dB frequency is lower than the one predicted in simulations by about 90–200 kHz. This is because the values of correcting capacitors used in the prototype amplifier are too large. The boost of the Gm characteristic for IBIAS = 5 nA is caused by undercompensation of the measuring path.
Noise characteristics obtained from the simulation are plotted in Figure 8b. In the range below 1 Hz, the 1/f noise reaches over 200 µV/(Hz)1/2. Above 100 Hz, the thermal noise is about 50 µV/(Hz)1/2. The current mirrors, particularly the transistors M4, M4+, M5, M5+, M9 and M10, are the greatest contributors to the total noise. This can be explained using the electrical diagram depicted in Figure 9. The schematic contains only the transistors that significantly contribute to the total output noise. The cascode transistors (and their biasings) are removed because their contributions to the noise are minor. Also, the noise of M2+ and M2− is omitted, as those devices acts as cascodes for M1+ and M1−.
In Figure 9, the all noise currents propagate through the current mirrors with a gain of 1, so the total mean-square output noise can be expressed as the sum of the particular noise currents:
i n , o u t 2 = 2 i n 1 2 + 2 i n 4 2 + 2 i n 5 2 + i n 9 2 + i n 10 2 = 2 i n 1 2 + 4 i n 4 , 5 2 + 2 i n 9 , 10 2 .
The noise current source (thermal + flicker) of MOSFET can be modelled as follows [22]:
i n 2 = 4 k T γ g m + K F g m 2 f C O X W L   [ A 2 / Hz ]
where k is Boltzmann’s constant, T is temperature, γ is a constant coefficient (γ ≈ 2/3), KF is the technological flicker-noise parameter and f is the frequency. Furthermore, COX denotes gate- capacitance-per-unit-area, whereas W and L represent the width and length of MOSFET, respectively.
For weak-inversion, a MOSFET transconductance (gm) is mainly determined by a biasing current and almost does not depend on W and L. Consequently, the parameter gm is almost the same for all the devices shown in Figure 9, i.e.,
g m 1 g m 4 , 5 g m 9 , 10 = g m I B I A S q / k T
where q is the electron charge.
It should be noted that contribution of all the transistors in Figure 9 to the thermal noise—the first component of Equation (9)—is equal. Similarly, their contribution to the flicker noise—the second component of Equation (9)—is nearly equal. Notwithstanding, flicker noise can be reduced by large values of W and L.
Based on Equations (7)–(10) and Figure 2b, the input-referred noise of the LTA in Figure 3 is given as:
e n , i n 2 = i n , o u t 2 G m , d i f f 2 = 32 q V E p 2 L 1 2 [ 16 γ I B I A S + q k 2 T 2 f C O X ( K F P W 1 L 1 + K F P W 9 , 10 L 9 , 10 + 2 K F N W 4 , 5 L 4 , 5 ) ]   [ V 2 / Hz ]
where KFP and KFN denote the KF for the p-channel and n-channel transistors, respectively.
As can be seen from Equation (11), the low value of the total noise of LTA for the given IBIAS can be maintained using current mirrors characterized by large W4,5,9,10 and large L4,5,9,10, as well as M1+ and M1− with large W1 and small L1. The parameter L1 was set to 0.20 µm, which is close to the technological minimum of 0.18 µm, but still sufficient to achieve a Gm of the order of nS (cf. Section 2.1). It is worth noting that parameters L2 and W2 do not affect the noise. They have been set to L2 = 0.20 µm and W2 = 100 µm in order to minimize the gate-source voltage of M2. Similarly, parameters L3,6,8,11 and W3,6,8,11 do not affect the noise, but they have been set to over 10 µm for better matching.

4.3. PSRR and CMRR

Owing to p-channel-based implementation, the amplifier’s input stage features small flicker noise (KFP < KFN) and supports rail-to-rail bulk driving [23]. However, for proper operation, the biasing voltage VG2 must be generated so that the difference VDDVG2 is constant. Otherwise, the unwanted AC signal on the VDD line will be visible in ∆I, resulting in a reduced power-supply-rejection-ratio (PSRR). The VG2 can be generated in a relatively simple way, as shown in Figure 10.
The input stage does not attenuate the common component of the input differential signal. Hence, it is pseudo-differential. The common component is suppressed at the amplifier’s output node by subtracting the currents. However, mismatch of the transistors causes the inverting and non-inverting tracks to not be perfectly matched and for the currents to not be perfectly subtracted. As a consequence, the rejection of the common component is not complete. The same mechanism resulting from the mismatch also weakens the amplifier’s resistance to interferences from the VDD line. The mismatch phenomenon is random. Out of the 12 fabricated amplifier prototypes, the worst one had a CMRR (common-mode rejection ratio) of 57 dB and a PSRR of 48 dB.

4.4. Temperature

As already explained in Section 2.2, for stable IBIAS, the effect of temperature changes on Gm is negligible. However, for the circuit of Figure 3, the temperature affects the copy of IBIAS in the non-cascoded mirrors MBIAS-M1+ and MBIAS-M1−. As indicated by the simulations, increase of the temperature from 0 °C to 70 °C, affects the increase of the Gm by 15%. To put that into perspective, drift of the Gm is 2.1 pS/°C and 9.7 pS/°C for IBIAS = 5 nA and IBIAS = 50 nA, respectively. The simulations were carried out under the assumption that the drift of the IBIAS source is at the level of a typical band-gap source (100 ppm/°C [24]).

4.5. Summary of the Performance Properties

The performance properties of the prototype are summarized in Table 1.

5. Application Example (Simulation Results)

The LTA performance properties have been be validated using the popular application scenario, i.e., the low-pass anti-aliasing Gm-C filter for the EEG/ECG band (0.05~100 Hz). For the system shown in Figure 1, the filter may have a smooth attenuation characteristic, i.e., its order may be low (from 2 to 4) [25,26,27,28]. Furthermore, approximation can be realized using Butterworth [28,29] or Bessel functions. Advanced, “sharp” filtration is performed in a digital signal processor (DSP). The advantage of smooth filters is that they do not have significant requirements with respect to the performance of transconductance amplifiers. On the other hand, such filters are often insufficient for performing thorough tests of amplifier circuits. Therefore, in this example, a more demanding 6th order Chebyshev filter is used (cf. Figure 11).
Under the assumption that transconductors are ideal, the frequency parameters of the filter in Figure 11 are as follows: the gain in the pass-band is 1 v/v (0 dB), the amplitude slope is −120 dB/dec and the attenuation in the stop-band is infinite. In reality, however, non-ideal parameters of transconductors that include finite output resistance, as well as parasitic zeros and transmittance poles, contribute to a more gradual slope of the characteristic and limited stop-band attenuation. Figure 12 shows a comparison of an ideal filter (dashed lines) with the one that implements the transconductors shown in Figure 3 (solid lines). The corner frequency of the filter can be tuned from 14.6 Hz to 144.8 Hz by changing the IBIAS between 5 nA and 50 nA. As can be seen, the considered transconductors accurately reproduce characteristics of the filter down to −90 dB, which is a very good result when it comes to analog Gm-C filters. When it comes to the large-signal properties, the output THD is below 1% (−40 dB) for sinusoidal excitation with a Vpp amplitude of 0.6 and frequency ten-fold lower than the corner one. When the excitation frequency is close to the corner one, i.e., near the end of the pass-band, the output distortions HD2 = −36 dB and HD3 = −55 dB, respectively.

6. Discussion and Conclusions

Linear LTAs are realized using various techniques such as current division (current splitting), current cancellation, bulk driving, source degeneration or floating gates. The examples can be found in many literature references, e.g., [2,3,8,9,10,12,13,14,15,16,17,30,31]. To the best of authors’ knowledge, to date, the channel-length-modulation effect for LTA realization has been reported only in [18]. The prototype amplifier solution in [18] is interesting, but it operates with a relatively high supply voltage of 5 V.
The proposed solution has been compared against state-of-the-art circuits from the literature comprising the linear transconductors with possibly close Gm values. The results are collected in Table 2. Most of the solutions are characterized by differential input/output and are only symmetrically driven. In such conditions, the proposed transconductor is the only one that maintains linearity when driven by a signal (2 Vpp) greater than the supply voltage (1 V). However, in the proposed solution, the noise is relatively high and, despite maintaining linearity in a wide range, it does not feature improved SNR as compared other solutions. On the other hand, the proposed circuit features improved performance in terms of low power consumption (0.3 µW) and low supply voltage (1 V). Temperature parameters cannot be compared because this parameter is not reported in majority of the available literature.
The presented transconductor solution is dedicated to working in a system where high gain is provided by the input LNA. From this perspective, the noise of an antialiasing transconductor-C filter is not of primary concern. Nevertheless, the noise in the proposed transconductor can be reduced through implementation in a single stage topology. It should be worth noting, however, that the single-stage topology is characterized by a narrower driving range. Therefore, choice between the single- and multi-stage topologies is a compromise between maintaining a low-noise and high-driving amplitude. The use of low-noise analog-dedicated CMOS technology (with lower technological parameters KFN and KFP in Equation (11) can also be considered to address the mentioned challenges.

Author Contributions

Conceptualization, J.J. and W.J.; methodology, J.J. and W.J.; formal analysis, W.J.; investigation, J.J., G.B. and M.K.; writing—original draft preparation, J.J. and W.J.; writing—review and editing, G.B. and S.S.; supervision, S.S.; project administration, S.S. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded in part by National Science Centre of Poland under the grant 2016/23/B/ST7/03733.

Conflicts of Interest

The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

Appendix A

Figure A1 and Figure A2 present simulation results obtained for all corners (worst case analysis). The responses represent supplementary data to the characteristics of Figure 5b and Figure 7b.
Figure A1. Corner simulations of the amplifier of Figure 3 at the asymmetrical input drive: (a) for 5-nA IBIAS; (b) for 50-nA IBIAS. VDD is 1 V.
Figure A1. Corner simulations of the amplifier of Figure 3 at the asymmetrical input drive: (a) for 5-nA IBIAS; (b) for 50-nA IBIAS. VDD is 1 V.
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Figure A2. Corner simulations of the amplifier of Figure 3 at the symmetrical input drive: (a) for 5-nA IBIAS; (b) for 50-nA IBIAS. VDD is 1 V.
Figure A2. Corner simulations of the amplifier of Figure 3 at the symmetrical input drive: (a) for 5-nA IBIAS; (b) for 50-nA IBIAS. VDD is 1 V.
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Figure 1. The main components of a microelectronic system processing low-frequency signals.
Figure 1. The main components of a microelectronic system processing low-frequency signals.
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Figure 2. A voltage-to-low-current conversion utilizing the channel-length-modulation effect in MOSFET: (a) the realization in CMOS technology; (b) MOSFET’s notation.
Figure 2. A voltage-to-low-current conversion utilizing the channel-length-modulation effect in MOSFET: (a) the realization in CMOS technology; (b) MOSFET’s notation.
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Figure 3. Complete electrical diagram of the low-Gm OTA (LTA) prototype. The dashed lines represent an in-chip generator of VG1.
Figure 3. Complete electrical diagram of the low-Gm OTA (LTA) prototype. The dashed lines represent an in-chip generator of VG1.
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Figure 4. Micro photography of the prototype integrated circuit. A single piece of LTA is marked using a white rectangle.
Figure 4. Micro photography of the prototype integrated circuit. A single piece of LTA is marked using a white rectangle.
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Figure 5. DC characteristics of the amplifier from Figure 3 at asymmetrical drive: (a) Iout vs. Vi−; (b) derivatives dIout/dVi−; (c) linearity error of the measured Iout vs. Vi− plots; (d) deviation error of the measured dIout/dVi− plots (i.e., deviation error of Gm). The Vi+ is fixed at 0.5 V, VDD is 1 V and temperature is 27 °C.
Figure 5. DC characteristics of the amplifier from Figure 3 at asymmetrical drive: (a) Iout vs. Vi−; (b) derivatives dIout/dVi−; (c) linearity error of the measured Iout vs. Vi− plots; (d) deviation error of the measured dIout/dVi− plots (i.e., deviation error of Gm). The Vi+ is fixed at 0.5 V, VDD is 1 V and temperature is 27 °C.
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Figure 6. Measured THD (total harmonic distortion) of Iout at an asymmetrical input driving. VDD is 1 V and T is 27 °C.
Figure 6. Measured THD (total harmonic distortion) of Iout at an asymmetrical input driving. VDD is 1 V and T is 27 °C.
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Figure 7. DC characteristics of the amplifier of Figure 3 at the symmetrical input drive: (a) derivatives dIout/d(Vi+Vi−); (b) deviation error of the measured dIout/d(Vi+Vi−) plots (i.e., deviation error of Gm,diff). VDD is 1 V and T is 27 °C.
Figure 7. DC characteristics of the amplifier of Figure 3 at the symmetrical input drive: (a) derivatives dIout/d(Vi+Vi−); (b) deviation error of the measured dIout/d(Vi+Vi−) plots (i.e., deviation error of Gm,diff). VDD is 1 V and T is 27 °C.
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Figure 8. Small-signal characteristics: (a) of the transconductance; (b) of the input-referred noise. AC signal is applied to the inverting input Vi−. DC levels on inputs are Vi− = Vi+ = 0.5 V. The VDD is 1 V.
Figure 8. Small-signal characteristics: (a) of the transconductance; (b) of the input-referred noise. AC signal is applied to the inverting input Vi−. DC levels on inputs are Vi− = Vi+ = 0.5 V. The VDD is 1 V.
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Figure 9. The simplified electrical diagram of the LTA for the noise calculation.
Figure 9. The simplified electrical diagram of the LTA for the noise calculation.
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Figure 10. The off-chip generator of VG2 used for tests of the prototype LTA of Figure 3.
Figure 10. The off-chip generator of VG2 used for tests of the prototype LTA of Figure 3.
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Figure 11. The 6th-order low-pass Gm-C (transconductor-C) filter with Chebyshev approximation.
Figure 11. The 6th-order low-pass Gm-C (transconductor-C) filter with Chebyshev approximation.
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Figure 12. Simulated amplitude responses of the filter from Figure 8.
Figure 12. Simulated amplitude responses of the filter from Figure 8.
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Table 1. Parameters of the prototype LTA at VDD = 1 V and 27 °C.
Table 1. Parameters of the prototype LTA at VDD = 1 V and 27 °C.
ParameterSimulatedMeasured
Technology/VendorStandard 180 nm CMOS 1P6M/TSMC
Physical dimensions 1174 µm × 156 µm
Supply voltage VDD1 V (min. 0.8 V, max. 1.8 V)
Average current consumption 132–290 nA28–270 nA
Gm tuning range (IBIAS range 5–50 nA)0.7–6.75 nS0.62–6.28 nS
Gm temperature drift 22.1 pS/°C @ IBIAS = 5 nA
9.7 pS/°C @ IBIAS = 50 nA
-
-
Input common-mode range0.1–1 V0–1 V (rail-to-rail)
THD of Iout
non-symmetrical driving
symmetrical driving
2.4% @ 1 Vpp, 1% @ 0.64 Vpp
0.47% @ 2.0 Vpp
0.8% @ 1 Vpp
0.18% @ 2 Vpp
Gm deviation (linearity) error
non-symmetrical driving
symmetrical driving
±22% @ 1 Vpp
±12% @ 2 Vpp
±12% @ 1 Vpp
±1.5% @ 2 Vpp
Input-reffered noise760 µVRMS
(integrated over 1–100 Hz)
-
Signal to noise ratio (SNR)
non-symmetrical driving
symmetrical driving
49.5 dB @ THD = 1%
59.3 dB @ THD = 0.47%
-
-
CMRR, PSRRmin. 56 dB, 47 dB 3min. 57 dB, 48 dB 4
Input offset voltage (VOS)max. ± 25 mV 325–50 mV 4
Mismatch-induced deviation of Gmmax. ± 4.5% 3-
1 Without the circuits drawn with dashed lines in Figure 3. 2 Gm deviation is 15% max when temperature varies from 0 to 70 °C. 3 200 Monte Carlo runs. 4 For 12 fabricated amplifier samples.
Table 2. Comparison of linear LTAs (linear low-Gm OTAs).
Table 2. Comparison of linear LTAs (linear low-Gm OTAs).
ParameterThis Work[12]
(BD+CD Case)
[16]
(Simulated)
[17][18]
Type of input/outputdiff./singlediff./singlediff./diff.diff./singlediff./diff.
Gm0.62–6.28 nS9.4 nS39.5–367.2 nS0.46–82 nS30 pS–25 µS
Supply voltage1 V2.7 V (±1.35 V)5 V (±2.5 V)1.5 V5 V (±2.5 V)
Power consumption<0.3 µW (28–270 nW)4.05 µW (sim.)160 µW<1 µW<300 µW
Input comm.-mode rangerail-to-rail--rail-to-rail-
Linear range for symmetrical input2 Vpp
@ 0.18% THD
0.9 Vpp
@ 1% HD3
2 Vpp
@ 0.13% THD
1.2 Vpp
@ 1% THD
2.6 Vpp
@ 1% THD
Input-referred noise760 µVRMS (sim.)
(1–100 Hz)
104.7 µVRMS
(0.01–10 Hz)
332 µVRMS
(10–30 kHz)
110 µVRMS
(1–100 Hz)
635 µVRMS
(1 Hz–2 MHz)
SNR59.3 dB (sim.)
@ 0.47% THD
69.6 dB
@ 1% HD3
~66.5 dB
@ 0.13% THD
70 dB
@ 1% THD
62 dB
@ 1% THD
CMRR/PSRR56 dB/47 dB->44.8 dB/n.a.->80 dB/>80 dB
CMOS process0.18 µm1.2 µm0.35 µm0.8 µm0.35 µm
Layout area0.027 mm20.22 mm20.006 mm20.04 mm20.046 mm2
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