#### 4.1. Linearity of Current-Voltage Characteristics

The linearity of current-voltage characteristics was measured for unfavorable asymmetrical excitation when the input

V_{i+} was fixed at a constant potential of 0.5 V, and while the

V_{i−} was swept from 0 V to

V_{DD} = 1 V. The measured DC characteristics

I_{out} vs.

V_{i−} for several values of the

I_{BIAS} source ranging from 5 nA to 50 nA are plotted in

Figure 5a. The characteristics obtained from the pre-production simulation (dashed lines) are also shown.

To calculate a linearity error of the measured

I_{out} vs.

V_{i−}, the ideal responses were first obtained using the linear regression and the least squares method. Next, the linearity error was calculated as the difference between the measured

I_{out} and the corresponding ideal

I_{out} divided by a full range of

I_{out} values, i.e., (

I_{out,meas} −

I_{out,ideal})/

I_{out,full-range}. The calculated results (expressed in percent) were plotted in

Figure 5c. The obtained error values are relatively low and range from −1% to +1.5% max. The curvature of the

I_{out} vs. the

V_{i−} plots is better visualized using derivatives d

I_{out}/d

V_{i}_{−}, as shown in

Figure 5b.

The value of d

I_{out}/d

V_{i}_{−} at 0.5 V is equal to the nominal transconductance of the amplifier, i.e.,

G_{m} = d

I_{out}/d

V_{i}_{−}|

_{Vi}_{−} _{= 0.5}. The nominal

G_{m} can be tuned from 0.62 nA/V to 6.28 nA/V by changing the source I

_{BIAS} from 5 nA to 50 nA. The percentage difference between d

I_{out}/d

V_{i}_{−} and the target

G_{m} (i.e., the

G_{m}-deviation error) is at most ±12% over an entire (rail-to-rail) input range. Detailed plots of the

G_{m} deviation error are in

Figure 5d.

The amplifier was also tested for harmonic distortion. The results of measuring the harmonic content in

I_{out} for 1-kHz sinusoidal excitation are shown in

Figure 6. The THD reaches 0.8% for the maximal

V_{i−} of 1 V

_{pp}.

Clearly, nonlinearities are smaller when both inputs of the amplifier are driven symmetrically, as such a configuration ensures the highest suppression of even harmonics. It should be emphasized that in practice, an input differential signal, (

V_{i+}–

V_{i−}), is never balanced in amplifier applications with a non-differential output. However, it is worth providing results for a symmetrical excitation, because the circuit in

Figure 3 can be easily equipped with a second output and adapted to “fully-balanced” applications. With symmetrical excitation with a maximum value of

V_{i+} −

V_{i}_{−} = 2 V

_{pp}, THD reaches only 0.18%. The

G_{m,diff} deviation is ±1.5% over the 2-V

_{pp} input range. Detailed plots of the derivative d

I_{out}/(d

V_{i+} − d

V_{i}_{−}) are in

Figure 7a, and the corresponding plots of the

G_{m,diff} deviation error are in

Figure 7b.

It should be emphasized that the prototype amplifier features better linearity than predicted by the simulations. This is clearly visible in

Figure 5b in the area for

V_{i−} < 0.2 V (see also

Figure A1 and

Figure A2 in

Appendix A). The bulk-effect (body-effect) in FET is not accurately modelled for the low potentials of bulk.

#### 4.2. Frequency and Noise Characteristics

A small-signal transconductance was measured in the range of 1 Hz–200 kHz. Measurements were performed separately for each of the inputs.

Figure 8a shows the results only for the

V_{i−} input, because this is the worst case in terms of frequency properties (because the inverting track is longer than the non-inverting track). The values of

G_{m} for the considered frequencies are consistent with the values of d

I_{out}/d

V_{i}_{−} at

V_{i−} = 0.5 V obtained from the DC measurements shown in

Figure 5b. The measured −3-dB frequency is lower than the one predicted in simulations by about 90–200 kHz. This is because the values of correcting capacitors used in the prototype amplifier are too large. The boost of the

G_{m} characteristic for

I_{BIAS} = 5 nA is caused by undercompensation of the measuring path.

Noise characteristics obtained from the simulation are plotted in

Figure 8b. In the range below 1 Hz, the 1/f noise reaches over 200 µV/(Hz)

^{1/2}. Above 100 Hz, the thermal noise is about 50 µV/(Hz)

^{1/2}. The current mirrors, particularly the transistors M

_{4}_{−}, M

_{4+}, M

_{5}_{−}, M

_{5+}, M

_{9}_{−} and M

_{10}_{−}, are the greatest contributors to the total noise. This can be explained using the electrical diagram depicted in

Figure 9. The schematic contains only the transistors that significantly contribute to the total output noise. The cascode transistors (and their biasings) are removed because their contributions to the noise are minor. Also, the noise of M

_{2}+ and M

_{2}− is omitted, as those devices acts as cascodes for M

_{1}+ and M

_{1}−.

In

Figure 9, the all noise currents propagate through the current mirrors with a gain of 1, so the total mean-square output noise can be expressed as the sum of the particular noise currents:

The noise current source (thermal + flicker) of MOSFET can be modelled as follows [

22]:

where

k is Boltzmann’s constant,

T is temperature,

γ is a constant coefficient (

γ ≈ 2/3),

K_{F} is the technological flicker-noise parameter and

f is the frequency. Furthermore,

C_{OX} denotes gate- capacitance-per-unit-area, whereas

W and

L represent the width and length of MOSFET, respectively.

For weak-inversion, a MOSFET transconductance (

g_{m}) is mainly determined by a biasing current and almost does not depend on

W and

L. Consequently, the parameter

g_{m} is almost the same for all the devices shown in

Figure 9, i.e.,

where

q is the electron charge.

It should be noted that contribution of all the transistors in

Figure 9 to the thermal noise—the first component of Equation (9)—is equal. Similarly, their contribution to the flicker noise—the second component of Equation (9)—is nearly equal. Notwithstanding, flicker noise can be reduced by large values of

W and

L.

Based on Equations (7)–(10) and

Figure 2b, the input-referred noise of the LTA in

Figure 3 is given as:

where

K_{FP} and

K_{FN} denote the

K_{F} for the p-channel and n-channel transistors, respectively.

As can be seen from Equation (11), the low value of the total noise of LTA for the given

I_{BIAS} can be maintained using current mirrors characterized by large

W_{4,5,9,10} and large

L_{4,5,9,10}, as well as M

_{1+} and M

_{1−} with large

W_{1} and small

L_{1}. The parameter

L_{1} was set to 0.20 µm, which is close to the technological minimum of 0.18 µm, but still sufficient to achieve a

G_{m} of the order of nS (cf.

Section 2.1). It is worth noting that parameters

L_{2} and

W_{2} do not affect the noise. They have been set to

L_{2} = 0.20 µm and

W_{2} = 100 µm in order to minimize the gate-source voltage of M

_{2}. Similarly, parameters

L_{3,6,8,11} and

W_{3,6,8,11} do not affect the noise, but they have been set to over 10 µm for better matching.

#### 4.3. PSRR and CMRR

Owing to p-channel-based implementation, the amplifier’s input stage features small flicker noise (

K_{FP} <

K_{FN}) and supports rail-to-rail bulk driving [

23]. However, for proper operation, the biasing voltage

V_{G}_{2} must be generated so that the difference

V_{DD} −

V_{G}_{2} is constant. Otherwise, the unwanted AC signal on the

V_{DD} line will be visible in ∆

I, resulting in a reduced power-supply-rejection-ratio (PSRR). The

V_{G}_{2} can be generated in a relatively simple way, as shown in

Figure 10.

The input stage does not attenuate the common component of the input differential signal. Hence, it is pseudo-differential. The common component is suppressed at the amplifier’s output node by subtracting the currents. However, mismatch of the transistors causes the inverting and non-inverting tracks to not be perfectly matched and for the currents to not be perfectly subtracted. As a consequence, the rejection of the common component is not complete. The same mechanism resulting from the mismatch also weakens the amplifier’s resistance to interferences from the V_{DD} line. The mismatch phenomenon is random. Out of the 12 fabricated amplifier prototypes, the worst one had a CMRR (common-mode rejection ratio) of 57 dB and a PSRR of 48 dB.

#### 4.4. Temperature

As already explained in

Section 2.2, for stable

I_{BIAS}, the effect of temperature changes on

G_{m} is negligible. However, for the circuit of

Figure 3, the temperature affects the copy of

I_{BIAS} in the non-cascoded mirrors M

_{BIAS}-M

_{1+} and M

_{BIAS}-M

_{1−}. As indicated by the simulations, increase of the temperature from 0 °C to 70 °C, affects the increase of the

G_{m} by 15%. To put that into perspective, drift of the

G_{m} is 2.1 pS/°C and 9.7 pS/°C for

I_{BIAS} = 5 nA and

I_{BIAS} = 50 nA, respectively. The simulations were carried out under the assumption that the drift of the

I_{BIAS} source is at the level of a typical band-gap source (100 ppm/°C [

24]).