A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

Abstract

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-V_pp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-V_pp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

1. Introduction

Operational transconductance amplifiers (OTAs) with a very low conversion ratio of 10⁻¹¹ to 10⁻⁷ A/V (hereinafter referred to as low-transconductance amplifiers, LTA) are used in analog pre-processing of very-low-frequency biomedical signals. Before digitalization, the analog biomedical signal is amplified and pre-filtered as illustrated in Figure 1 [1,2,3,4,5]. First, the signal is amplified by a low noise amplifier (LNA). Then, the signal amplitude is corrected by a variable gain amplifier (VGA) in order to make it suitable for the input of an analog-to-digital converter (ADC). The analog filter reduces the bandwidth to minimize signal distortion that results from the aliasing effect. LNA, VGA and the filter constitute an analog front-end. It should be noted that the filter does not have to be implemented as an individual block. Instead, the filtering component can be embedded into LNA and VGA through the limitation of their bandwidth [1,6].

The amplitude of biomedical signal ranges from a few µV to several tens of mV, and its frequency is from 0.01 Hz to 3 kHz [6]. To achieve optimal processing dynamics, the front-end is integrated with ADC in a single chip. However, the integration of low-frequency circuits is a challenge. The corner frequency is associated with the RC-time-constant, i.e., f ≈ 1/(2πRC). In a typical CMOS process, resistors can be made of polysilicon with a resistivity of 10³ Ω/square, and capacitors made of polysilicon-insulator-polysilicon or metal-insulator-metal layers with a unit capacitance of 10⁻¹⁵ F/µm². Due to large area requirements, the practical values of the resistances and capacitances in integrated circuits are R < 100 kΩ and C < 100 pF, whereas the corresponding corner frequency is f > 15 kHz. For further reduction of frequency, the RC-time-constant can be increased using active techniques such as the capacitance multiplication and resistance emulation. Examples of using the capacitance (Miller’s) multiplication in front-ends can be found in [1,7]. However, the majority of the available literature focuses on LTA-based emulation of large resistances [2,3,8,9,10,11,12,13,14,15,16,17,18]. LTAs emulate resistors as large as 10⁷–10¹¹ Ω while occupying a reasonable area of 0.01 mm² to 0.1 mm² [2,3,8,9,10,11,12,13,14,15,16,17,18]. However, when compared to passive components, the performance figures of active resistors such as linearity, temperature stability and noise are worse. Improvement of these parameters is one of the main goals of contemporary research studies [12].

This work presents an innovative LTA that is developed and manufactured in a 0.18-µm CMOS technology at the Taiwan Semiconductor Manufacturing Company (TSMC). LTA uses the so-called Early effect (channel-length-modulation effect) in a field effect transistor (FET) to directly emulate high resistance. The relationship between the output current and the input voltage of LTA is linear from the ground to the supply voltage. The circuit design is relatively simple and does not require special optimization. Owing to the use of sub-microwatt power consumption and 1-V supply, it is suitable for use in low-power low-voltage biomedical interfaces. The following chapters present the operating principle, circuit details, theoretical analysis and prototype measurement results.

2. Voltage-to-Current Conversion Using Channel-Length-Modulation Effect

2.1. Operation Principles

The proposed voltage-to-low-current converter is shown in Figure 2a. The conversion mechanism is the same as in [18]; however, the proposed converter circuit is improved so as to support operation with low-supply voltage. Furthermore, the structure can be rail-to-rail driven.

The input signal is ∆V_i and the output signal is ∆I. Here, saturation of all transistors is assumed. The transistor M₁ is a DC current source that is generating the bias current I_BIAS. M₂ is a bulk-driven voltage follower. It transfers ∆V_i from the bulk of M₂ to the drain of M₁ with a factor of about 0.25 V/V. The deviation in the drain current of M₁ caused by the channel-length-modulation can be expressed as follows:

I_D1 − ∆I_D1 = I_BIAS − ∆I = I_BIAS(1 + λ_p∆V_SD1) = I_BIAS(1 + λ_p(∆V_DD − ∆V_D1))

(1)

where λ_p is the channel-length-modulation factor in a p-channel device for given channel length. The deviation of current can also be calculated using an alternative formula.

I_D1 − ∆I_D1 = I_BIAS − ∆I = I_BIAS(1 + ∆V_SD1/(V_EpL₁)) = I_BIAS(1 + (∆V_DD − ∆V_D1)/(V_EpL₁))

(2)

where V_Ep is the p-channel devices Early voltage per unit-channel-length [19], and L₁ is the length of the M₁ channel.

Assuming ∆V_D1 ≈ 0.25∆V_i and ∆V_DD = 0, the I-V conversion factor, defined as transconductance G_m = ∆I/∆V_i, can be simply calculated from Equation (1) or (2):

G_m = ∆I/∆V_i ≈ 0.25·I_BIAS·λ_p

(3)

G_m = ∆I/∆V_i ≈ 0.25·I_BIAS/(V_Ep·L₁).

(4)

When M₁ and M₂ are saturated, Equations (1)–(4) are valid regardless of the inversion levels in M₁ and M₂. However, to achieve G_m of the order of 10⁻⁹ A/V, the inversion levels of M₁ and M₂ should be weak or at most moderate. The selected operating points, shown in Figure 2a, ensure the proper transistor operating range for the standard 180-nm CMOS process. For example, transistors with L₁ = 200 nm, V_Ep = 8.8 V/µm and I_BIAS = 10 nA will give G_m ≈ 1.4 nA/V (1.4 nS).

The resistance seen from the M₂ source is much smaller than the output resistance of M₁; thus, ∆I is entirely transferred from the M₁ drain to the converter’s output (out). Next, ∆I is reflected in a current mirror, part of which is the diode-connected transistor M₃.

2.2. Robustness to Unfavorable Factors

As long as FET remains saturated, the channel-length-modulation effect in FET is linear over a wide range of operating points [20]. Therefore, the impact of undesirable effects, such as transistor mismatch, tolerances of the manufacturing process or temperature variations on the linearity of the converter, are limited. Notwithstanding, the mentioned factors affect the G_m through changes of I_BIAS, λ_p (or V_EpL₁) and the follower’s gain (factor 0.25). However, measurements of the prototype converter show that the real value of G_m differs from a predicted value by about only 10%.

Another aspect that requires detailed analysis involves the demonstration of the effect of temperature on G_m. The increase of the current in M₁ (∆I) is equal to the product of the drain voltage increase (∆V_D1) and the drain-source conductance (g_DS1), i.e., ∆I = ∆V_D1 · g_DS1. The conductance g_DS1 = I_BIAS/(V_EpL₁) results from the effect of channel length modulation. Hence, G_m can be expressed by the formula that is more accurate than Equation (4), i.e.,

$$G_m=\frac{\mathsf{\Delta }I}{\mathsf{\Delta }{V}_i}=\frac{\mathsf{\Delta }{V}_{D1}}{\mathsf{\Delta }{V}_i}\cdot g_{DS1}=\frac{\mathsf{\Delta }{V}_{D1}}{\mathsf{\Delta }{V}_i}\cdot \frac{I_{BIAS}}{V_{Ep}{L}_1}$$

(5)

Here, V_Ep and L₁ do not depend on the temperature, whereas I_BIAS can be stabilized. The only temperature dependent factor in Equation (5) is ∆V_D1/∆V_i, i.e., the gain of the M₂ follower. It can be determined as

$$\frac{\mathsf{\Delta }{V}_{D1}}{\mathsf{\Delta }{V}_i}=\frac{g_{mb2}}{g_{mb2}+g_{m2}+g_{DS2}+g_{DS1}+\frac{g_{DS1}{g}_{DS2}}{g_{m3}+g_{DS3}}}\cong \frac{1}{\frac{g_{m2}}{g_{mb2}}+1} \approx 0.25$$

(6)

where g_m2 and g_mb2 are the gate and bulk transconductances of M₂, respectively.

Using the detailed formulas of [20], one can show that the dependence of the g_m2/g_mb2 ratio on temperature is relatively weak. This implies that for stable I_BIAS in the M1-M2-M3 branch, G_m does not depend on temperature.

3. Low-G_m OTA (LTA)

Based on the two converters from Figure 2a, an amplifier with differential input was developed (cf. Figure 3). The currents ΔI₊ and ΔI₋ from the two converters flow to the amplifier’s output (out) through two independent tracks. In other words, ΔI₊ flows in the non-inverting path containing one mirror composed of the transistors M₃₊ to M₆₊. The ΔI₋ flows through the inverting path containing two mirrors formed by transistors M₃₋ to M₁₁₋. All mirrors have a 1:1 ratio.

The amplifier’s transconductance for differential input (G_m,diff) is exactly equal to G_m, i.e.,

$$G_{m,diff}=\frac{\mathsf{\Delta }{I}_{out}}{\mathsf{\Delta }{V}_{i,diff}}=\frac{\mathsf{\Delta }{I}_{+}-\mathsf{\Delta }{I}_{-}}{\mathsf{\Delta }{V}_{i+}-\mathsf{\Delta }{V}_{i-}}=\frac{G_m\mathsf{\Delta }{V}_{i+}-G_m\mathsf{\Delta }{V}_{-}}{\mathsf{\Delta }{V}_{i+}-\mathsf{\Delta }{V}_{i-}}=G_m.$$

(7)

The output conductance of the amplifier (G_out) should be much smaller than G_m, i.e., G_out << 1 nS. This was achieved by using long-channel transistors and cascodes. The cascodes consisting of n-channel transistors are biased by V_G3,6. The latter is generated by the M₁₂₋M₁₆ branch. The “p-channel” cascodes are biased by the V_G8,11 generated by M₇₋. All transistors in Figure 3 are standard 1.8-V thin-oxide with nominal-threshold-voltages of 0.42 V and −0.5 V for n-channel and p-channel transistors, respectively. Transistors’ dimensions (width/length expressed in µm/µm) are given in the schematic, whereas the rationale behind selecting specific dimensions is explained in Section 4.2. The schematic also shows the DC bias voltages at V_DD of 1 V. Two capacitors of C₁ attenuate a possible overshoot in the step transient response of the source followers M₂₊ and M₂₋ [21]. A real pole (p) due to the parallel combination of C₁ and g_m4 (i.e., p ≅ g_m4/C₁) cancels a zero (z) due to C_sb2 and g_mb2 (i.e., z ≅ g_mb2/C_sb2) in M₂₊ and M_2−. A capacitor of C₂ is a “by-pass” for an AC current flowing through the bias transistor M₇₋. It should be emphasized that these capacitors are not critical elements and have been added to the prototype circuit for research purposes only.

Figure 4 shows a selected fragment of a prototype microchip that embeds LTAs. The size of a single LTA (marked using a white rectangle) is 174 µm × 156 µm. The capacitors, located close to the microstructure surface, are clearly visible. There are two 12-picofarad capacitors, each of which is composed of 10 smaller capacitors (two arrays of capacitors, each of which contains 10 components), and one 970-femtofarad capacitor (small array consisting of 2 capacitors).

4. Performances of the Prototype

4.1. Linearity of Current-Voltage Characteristics

The linearity of current-voltage characteristics was measured for unfavorable asymmetrical excitation when the input V_i+ was fixed at a constant potential of 0.5 V, and while the V_i− was swept from 0 V to V_DD = 1 V. The measured DC characteristics I_out vs. V_i− for several values of the I_BIAS source ranging from 5 nA to 50 nA are plotted in Figure 5a. The characteristics obtained from the pre-production simulation (dashed lines) are also shown.

To calculate a linearity error of the measured I_out vs. V_i−, the ideal responses were first obtained using the linear regression and the least squares method. Next, the linearity error was calculated as the difference between the measured I_out and the corresponding ideal I_out divided by a full range of I_out values, i.e., (I_out,meas − I_out,ideal)/I_{out,full-range}. The calculated results (expressed in percent) were plotted in Figure 5c. The obtained error values are relatively low and range from −1% to +1.5% max. The curvature of the I_out vs. the V_i− plots is better visualized using derivatives dI_out/dV_i−, as shown in Figure 5b.

The value of dI_out/dV_i− at 0.5 V is equal to the nominal transconductance of the amplifier, i.e., G_m = dI_out/dV_i−|_{Vi− = 0.5}. The nominal G_m can be tuned from 0.62 nA/V to 6.28 nA/V by changing the source I_BIAS from 5 nA to 50 nA. The percentage difference between dI_out/dV_i− and the target G_m (i.e., the G_m-deviation error) is at most ±12% over an entire (rail-to-rail) input range. Detailed plots of the G_m deviation error are in Figure 5d.

The amplifier was also tested for harmonic distortion. The results of measuring the harmonic content in I_out for 1-kHz sinusoidal excitation are shown in Figure 6. The THD reaches 0.8% for the maximal V_i− of 1 V_pp.

Clearly, nonlinearities are smaller when both inputs of the amplifier are driven symmetrically, as such a configuration ensures the highest suppression of even harmonics. It should be emphasized that in practice, an input differential signal, (V_i+–V_i−), is never balanced in amplifier applications with a non-differential output. However, it is worth providing results for a symmetrical excitation, because the circuit in Figure 3 can be easily equipped with a second output and adapted to “fully-balanced” applications. With symmetrical excitation with a maximum value of V_i+ − V_i− = 2 V_pp, THD reaches only 0.18%. The G_m,diff deviation is ±1.5% over the 2-V_pp input range. Detailed plots of the derivative dI_out/(dV_i+ − dV_i−) are in Figure 7a, and the corresponding plots of the G_m,diff deviation error are in Figure 7b.

It should be emphasized that the prototype amplifier features better linearity than predicted by the simulations. This is clearly visible in Figure 5b in the area for V_i− < 0.2 V (see also Figure A1 and Figure A2 in Appendix A). The bulk-effect (body-effect) in FET is not accurately modelled for the low potentials of bulk.

4.2. Frequency and Noise Characteristics

A small-signal transconductance was measured in the range of 1 Hz–200 kHz. Measurements were performed separately for each of the inputs. Figure 8a shows the results only for the V_i− input, because this is the worst case in terms of frequency properties (because the inverting track is longer than the non-inverting track). The values of G_m for the considered frequencies are consistent with the values of dI_out/dV_i− at V_i− = 0.5 V obtained from the DC measurements shown in Figure 5b. The measured −3-dB frequency is lower than the one predicted in simulations by about 90–200 kHz. This is because the values of correcting capacitors used in the prototype amplifier are too large. The boost of the G_m characteristic for I_BIAS = 5 nA is caused by undercompensation of the measuring path.

Noise characteristics obtained from the simulation are plotted in Figure 8b. In the range below 1 Hz, the 1/f noise reaches over 200 µV/(Hz)^1/2. Above 100 Hz, the thermal noise is about 50 µV/(Hz)^1/2. The current mirrors, particularly the transistors M₄₋, M₄₊, M₅₋, M₅₊, M₉₋ and M₁₀₋, are the greatest contributors to the total noise. This can be explained using the electrical diagram depicted in Figure 9. The schematic contains only the transistors that significantly contribute to the total output noise. The cascode transistors (and their biasings) are removed because their contributions to the noise are minor. Also, the noise of M₂+ and M₂− is omitted, as those devices acts as cascodes for M₁+ and M₁−.

In Figure 9, the all noise currents propagate through the current mirrors with a gain of 1, so the total mean-square output noise can be expressed as the sum of the particular noise currents:

$$i_{n,out}^2=2i_{n1}^2+2i_{n4}^2+2i_{n5}^2+i_{n9}^2+i_{n10}^2=2i_{n1}^2+4i_{n4,5}^2+2i_{n9,10}^2.$$

(8)

The noise current source (thermal + flicker) of MOSFET can be modelled as follows [22]:

$$i_n^2=4kT\gamma g_m+\frac{K_F{g}_m^2}{f{C}_{OX}WL} [{\mathrm{A}}^2/\mathrm{Hz}]$$

(9)

where k is Boltzmann’s constant, T is temperature, γ is a constant coefficient (γ ≈ 2/3), K_F is the technological flicker-noise parameter and f is the frequency. Furthermore, C_OX denotes gate- capacitance-per-unit-area, whereas W and L represent the width and length of MOSFET, respectively.

For weak-inversion, a MOSFET transconductance (g_m) is mainly determined by a biasing current and almost does not depend on W and L. Consequently, the parameter g_m is almost the same for all the devices shown in Figure 9, i.e.,

$$g_{m1}\cong g_{m4,5}\cong g_{m9,10}=g_m\cong I_{BIAS}q/kT$$

(10)

where q is the electron charge.

It should be noted that contribution of all the transistors in Figure 9 to the thermal noise—the first component of Equation (9)—is equal. Similarly, their contribution to the flicker noise—the second component of Equation (9)—is nearly equal. Notwithstanding, flicker noise can be reduced by large values of W and L.

Based on Equations (7)–(10) and Figure 2b, the input-referred noise of the LTA in Figure 3 is given as:

$$e_{n,in}^2=\frac{i_{n,out}^2}{G_{m,diff}^2}=32q{V}_{Ep}^2{L}_1^2\left[\frac{16\gamma }{I_{BIAS}}+\frac{q}{k^2{T}^{2}f{C}_{OX}}\left(\frac{K_{FP}}{W_1{L}_1}+\frac{K_{FP}}{W_{9,10}{L}_{9,10}}+\frac{2K_{FN}}{W_{4,5}{L}_{4,5}}\right)\right] [{\mathrm{V}}^2/\mathrm{Hz}]$$

(11)

where K_FP and K_FN denote the K_F for the p-channel and n-channel transistors, respectively.

As can be seen from Equation (11), the low value of the total noise of LTA for the given I_BIAS can be maintained using current mirrors characterized by large W_4,5,9,10 and large L_4,5,9,10, as well as M₁₊ and M₁₋ with large W₁ and small L₁. The parameter L₁ was set to 0.20 µm, which is close to the technological minimum of 0.18 µm, but still sufficient to achieve a G_m of the order of nS (cf. Section 2.1). It is worth noting that parameters L₂ and W₂ do not affect the noise. They have been set to L₂ = 0.20 µm and W₂ = 100 µm in order to minimize the gate-source voltage of M₂. Similarly, parameters L_3,6,8,11 and W_3,6,8,11 do not affect the noise, but they have been set to over 10 µm for better matching.

4.3. PSRR and CMRR

Owing to p-channel-based implementation, the amplifier’s input stage features small flicker noise (K_FP < K_FN) and supports rail-to-rail bulk driving [23]. However, for proper operation, the biasing voltage V_G2 must be generated so that the difference V_DD − V_G2 is constant. Otherwise, the unwanted AC signal on the V_DD line will be visible in ∆I, resulting in a reduced power-supply-rejection-ratio (PSRR). The V_G2 can be generated in a relatively simple way, as shown in Figure 10.

The input stage does not attenuate the common component of the input differential signal. Hence, it is pseudo-differential. The common component is suppressed at the amplifier’s output node by subtracting the currents. However, mismatch of the transistors causes the inverting and non-inverting tracks to not be perfectly matched and for the currents to not be perfectly subtracted. As a consequence, the rejection of the common component is not complete. The same mechanism resulting from the mismatch also weakens the amplifier’s resistance to interferences from the V_DD line. The mismatch phenomenon is random. Out of the 12 fabricated amplifier prototypes, the worst one had a CMRR (common-mode rejection ratio) of 57 dB and a PSRR of 48 dB.

4.4. Temperature

As already explained in Section 2.2, for stable I_BIAS, the effect of temperature changes on G_m is negligible. However, for the circuit of Figure 3, the temperature affects the copy of I_BIAS in the non-cascoded mirrors M_BIAS-M₁₊ and M_BIAS-M₁₋. As indicated by the simulations, increase of the temperature from 0 °C to 70 °C, affects the increase of the G_m by 15%. To put that into perspective, drift of the G_m is 2.1 pS/°C and 9.7 pS/°C for I_BIAS = 5 nA and I_BIAS = 50 nA, respectively. The simulations were carried out under the assumption that the drift of the I_BIAS source is at the level of a typical band-gap source (100 ppm/°C [24]).

4.5. Summary of the Performance Properties

The performance properties of the prototype are summarized in

Table 1. Parameters of the prototype LTA at V_DD = 1 V and 27 °C.

Parameter	Simulated	Measured
Technology/Vendor	Standard 180 nm CMOS 1P6M/TSMC
Physical dimensions 1	174 µm × 156 µm
Supply voltage VDD	1 V (min. 0.8 V, max. 1.8 V)
Average current consumption 1	32–290 nA	28–270 nA
Gm tuning range (IBIAS range 5–50 nA)	0.7–6.75 nS	0.62–6.28 nS
Gm temperature drift 2	2.1 pS/°C @ IBIAS = 5 nA 9.7 pS/°C @ IBIAS = 50 nA	- -
Input common-mode range	0.1–1 V	0–1 V (rail-to-rail)
THD of Iout non-symmetrical driving symmetrical driving	2.4% @ 1 Vpp, 1% @ 0.64 Vpp 0.47% @ 2.0 Vpp	0.8% @ 1 Vpp 0.18% @ 2 Vpp
Gm deviation (linearity) error non-symmetrical driving symmetrical driving	±22% @ 1 Vpp ±12% @ 2 Vpp	±12% @ 1 Vpp ±1.5% @ 2 Vpp
Input-reffered noise	760 µVRMS (integrated over 1–100 Hz)	-
Signal to noise ratio (SNR) non-symmetrical driving symmetrical driving	49.5 dB @ THD = 1% 59.3 dB @ THD = 0.47%	- -
CMRR, PSRR	min. 56 dB, 47 dB 3	min. 57 dB, 48 dB 4
Input offset voltage (VOS)	max. ± 25 mV 3	25–50 mV 4
Mismatch-induced deviation of Gm	max. ± 4.5% 3	-

¹ Without the circuits drawn with dashed lines in Figure 3. ² G_m deviation is 15% max when temperature varies from 0 to 70 °C. ³ 200 Monte Carlo runs. ⁴ For 12 fabricated amplifier samples.

.

5. Application Example (Simulation Results)

The LTA performance properties have been be validated using the popular application scenario, i.e., the low-pass anti-aliasing G_m-C filter for the EEG/ECG band (0.05~100 Hz). For the system shown in Figure 1, the filter may have a smooth attenuation characteristic, i.e., its order may be low (from 2 to 4) [25,26,27,28]. Furthermore, approximation can be realized using Butterworth [28,29] or Bessel functions. Advanced, “sharp” filtration is performed in a digital signal processor (DSP). The advantage of smooth filters is that they do not have significant requirements with respect to the performance of transconductance amplifiers. On the other hand, such filters are often insufficient for performing thorough tests of amplifier circuits. Therefore, in this example, a more demanding 6th order Chebyshev filter is used (cf. Figure 11).

Under the assumption that transconductors are ideal, the frequency parameters of the filter in Figure 11 are as follows: the gain in the pass-band is 1 v/v (0 dB), the amplitude slope is −120 dB/dec and the attenuation in the stop-band is infinite. In reality, however, non-ideal parameters of transconductors that include finite output resistance, as well as parasitic zeros and transmittance poles, contribute to a more gradual slope of the characteristic and limited stop-band attenuation. Figure 12 shows a comparison of an ideal filter (dashed lines) with the one that implements the transconductors shown in Figure 3 (solid lines). The corner frequency of the filter can be tuned from 14.6 Hz to 144.8 Hz by changing the I_BIAS between 5 nA and 50 nA. As can be seen, the considered transconductors accurately reproduce characteristics of the filter down to −90 dB, which is a very good result when it comes to analog G_m-C filters. When it comes to the large-signal properties, the output THD is below 1% (−40 dB) for sinusoidal excitation with a V_pp amplitude of 0.6 and frequency ten-fold lower than the corner one. When the excitation frequency is close to the corner one, i.e., near the end of the pass-band, the output distortions HD₂ = −36 dB and HD₃ = −55 dB, respectively.

6. Discussion and Conclusions

Linear LTAs are realized using various techniques such as current division (current splitting), current cancellation, bulk driving, source degeneration or floating gates. The examples can be found in many literature references, e.g., [2,3,8,9,10,12,13,14,15,16,17,30,31]. To the best of authors’ knowledge, to date, the channel-length-modulation effect for LTA realization has been reported only in [18]. The prototype amplifier solution in [18] is interesting, but it operates with a relatively high supply voltage of 5 V.

The proposed solution has been compared against state-of-the-art circuits from the literature comprising the linear transconductors with possibly close G_m values. The results are collected in

Table 2. Comparison of linear LTAs (linear low-G_m OTAs).

Parameter	This Work	[12] (BD+CD Case)	[16] (Simulated)	[17]	[18]
Type of input/output	diff./single	diff./single	diff./diff.	diff./single	diff./diff.
Gm	0.62–6.28 nS	9.4 nS	39.5–367.2 nS	0.46–82 nS	30 pS–25 µS
Supply voltage	1 V	2.7 V (±1.35 V)	5 V (±2.5 V)	1.5 V	5 V (±2.5 V)
Power consumption	<0.3 µW (28–270 nW)	4.05 µW (sim.)	160 µW	<1 µW	<300 µW
Input comm.-mode range	rail-to-rail	-	-	rail-to-rail	-
Linear range for symmetrical input	2 Vpp @ 0.18% THD	0.9 Vpp @ 1% HD3	2 Vpp @ 0.13% THD	1.2 Vpp @ 1% THD	2.6 Vpp @ 1% THD
Input-referred noise	760 µVRMS (sim.) (1–100 Hz)	104.7 µVRMS (0.01–10 Hz)	332 µVRMS (10–30 kHz)	110 µVRMS (1–100 Hz)	635 µVRMS (1 Hz–2 MHz)
SNR	59.3 dB (sim.) @ 0.47% THD	69.6 dB @ 1% HD3	~66.5 dB @ 0.13% THD	70 dB @ 1% THD	62 dB @ 1% THD
CMRR/PSRR	56 dB/47 dB	-	>44.8 dB/n.a.	-	>80 dB/>80 dB
CMOS process	0.18 µm	1.2 µm	0.35 µm	0.8 µm	0.35 µm
Layout area	0.027 mm2	0.22 mm2	0.006 mm2	0.04 mm2	0.046 mm2

. Most of the solutions are characterized by differential input/output and are only symmetrically driven. In such conditions, the proposed transconductor is the only one that maintains linearity when driven by a signal (2 V_pp) greater than the supply voltage (1 V). However, in the proposed solution, the noise is relatively high and, despite maintaining linearity in a wide range, it does not feature improved SNR as compared other solutions. On the other hand, the proposed circuit features improved performance in terms of low power consumption (0.3 µW) and low supply voltage (1 V). Temperature parameters cannot be compared because this parameter is not reported in majority of the available literature.

The presented transconductor solution is dedicated to working in a system where high gain is provided by the input LNA. From this perspective, the noise of an antialiasing transconductor-C filter is not of primary concern. Nevertheless, the noise in the proposed transconductor can be reduced through implementation in a single stage topology. It should be worth noting, however, that the single-stage topology is characterized by a narrower driving range. Therefore, choice between the single- and multi-stage topologies is a compromise between maintaining a low-noise and high-driving amplitude. The use of low-noise analog-dedicated CMOS technology (with lower technological parameters K_FN and K_FP in Equation (11) can also be considered to address the mentioned challenges.