Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via †
Abstract
:1. Introduction
2. Fabrication of Encapsulation Cap
- (a)
- A 4-inch silicon wafer with a low resistivity (0.0009 Ω·cm) was used to realize a low loss electrical interconnection. The substrate was patterned by photolithography and an 8-μm thick photoresist acted as the mask for deep silicon etching.
- (b)
- The mature deep reactive ion etch (DRIE) process was utilized to etch silicon of 350 μm to form silicon molds for the glass reflow process. The photoresist was removed and the chemical cleaning of the wafer was carefully conducted for the following anodic bonding.
- (c)
- The silicon substrate was bonded to the Pyrex glass wafer in a vacuum environment. The silicon substrate and the glass wafer had the same thickness and a similar coefficient of thermal expansion (CTE) to minimize the warp and distortion of the bonded wafer. It should be noted that it is necessary to hold the vacuum conditions of 10−2 mTorr (1 Torr ≈ 133 Pa) for enough time to achieve vacuum outgassing, which can prevent generating voids during the glass reflow process.
- (d)
- The bonded wafer was then placed in the furnace at 1050 °C for 2 h to ensure that the silicon molds were fully filled with the fused glass. When the temperature was elevated above 750 °C, the fused glass started to be pushed into the silicon molds under the large pressure difference between inside and outside the hermetic cavity. Subsequently, the glass was cooled by a cooling process.
- (e)
- The reflowed wafer was lapped and thinned on double sides until the formation of the silicon vertical feedthrough. A chemical mechanical polishing (CMP) process was exploited to provide good surface quality for later wafer bonding.
- (f)
- To form the encapsulation cavity, the silicon was etched by an Inductively Coupled Plasma (ICP) process to a certain depth according to design requirements. The cavity acted as the gap of the sensing capacitor when the following anodic bonding was accomplished.
3. Characterization and Measurement
4. Application and Discussion
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
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Zhang, M.; Yang, J.; He, Y.; Yang, F.; Yang, F.; Han, G.; Si, C.; Ning, J. Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via. Sensors 2019, 19, 93. https://doi.org/10.3390/s19010093
Zhang M, Yang J, He Y, Yang F, Yang F, Han G, Si C, Ning J. Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via. Sensors. 2019; 19(1):93. https://doi.org/10.3390/s19010093
Chicago/Turabian StyleZhang, Meng, Jian Yang, Yurong He, Fan Yang, Fuhua Yang, Guowei Han, Chaowei Si, and Jin Ning. 2019. "Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via" Sensors 19, no. 1: 93. https://doi.org/10.3390/s19010093
APA StyleZhang, M., Yang, J., He, Y., Yang, F., Yang, F., Han, G., Si, C., & Ning, J. (2019). Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via. Sensors, 19(1), 93. https://doi.org/10.3390/s19010093