In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm2
including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of −60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.
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