The architecture of the EIS AFE chip is shown in

Figure 3. The chip allows for fully-differential voltage readout (VR, four channels) and single-ended rail-to-rail output current readout (CR, two channels). The CR channels are equipped with an automatic gain control (AGC) unit that allows extension of the signal dynamic range. The AGC comprises a peak detector (PD), a comparison stage (COMP) and a control logic unit (off-chip). In the VR mode, bandwidth-limited (BW) low-noise operation (up to 80 kHz) or high-frequency recording (HF, up to 8 MHz) can be selected. The BW channel can be used when extracellular voltage recording is needed in a frequency range from sub-Hz to kHz [

28]. In this case, chopper-stabilized op-amps switching at a frequency of 100 kHz are used to allow for low-noise measurements to be performed. The HF channel allows for electrochemical sensing and solution conductivity mapping at frequencies higher than 10 kHz and up to 1 MHz [

11]. Impedance measurements in the MHz regime are more sensitive to intracellular changes and can be used to characterize the cell membrane impedance [

29]. Each channel has programmable gain stages, operational bandwidth and enable signals that can turn off entire sections of the chip to save power. The chip is powered by a single 1.8-V supply. The common-mode voltage,

${V}_{CM}$, is set to 0.9 V by an internal voltage generator. The chip can be programmed via a microcontroller using a serial-to-peripheral interface (SPI) consisting of 11 registers. The chip is also equipped with two 10-bit successive-approximation ADCs with a maximum sampling rate of 200 kS/s. The output of the ADCs can be read serially though an on-chip parallel-in-serial-out (PISO) interface. The analogue outputs of the VR and CR units are directly available externally and can be readily connected to the on-chip ADCs for digitization. The operation of the chip described in this paper was limited to spectroscopy studies in a frequency range between 100 Hz and 100 kHz.

#### 2.1. Current-Readout AFE

The CR-AFE consists of a TIA input stage followed by a programmable gain amplifier (PGA) stage controlled by an AGC unit, as shown in

Figure 4. The TIA can be implemented using either discrete-time (DT) or continuous-time (CT) architectures. DT topologies offer very low-noise performance, but are limited to low frequency operation due to the need to reset the integrating capacitor [

30,

31,

32,

33]. Among CT topologies, integrator-differentiator (ID) and resistor-feedback (RF) architectures are suitable candidates to implement TIAs in CMOS [

34,

35]. ID structures have several advantages, including low-noise and high-bandwidth operation [

36], but require the implementation of very large resistors or DC-feedback loops to provide a DC current path, which introduces complexity and stability issues.

The TIA in this paper was implemented by a resistor-feedback op-amp configuration. This offers a straightforward implementation that can handle DC currents. In addition, input currents in the range of nA–

$\mathsf{\mu}$A, consistent with the sensors used in this study, require small TIA gains (kΩ) to avoid the saturation of the amplifier, which can be better implemented using resistors. The gain of the TIA is programmable by switching the feedback resistor to 10 kΩ, 50 kΩ or 100 kΩ. A resistor-feedback programmable-gain amplifier is used to perform further amplification between 1 V/V and 14 V/V using

${G}_{0}$ and 4 V/V and 54 V/V using switch

${G}_{1}$. Fine gain tuning is controlled by changing the input resistance of the amplifier,

${R}_{1}$, so that the PGA gain is given by:

where

${R}_{2}$ is the feedback resistance and

${R}_{u}$ is the value of the unit resistor of the array,

d is the control code of the input resistor array and

n is the number of bits and is equal to four.

Amplifiers

$A1$ and

$A2$ in

Figure 4 are implemented by a two-stage Class AB amplifier with a minimum-current selector for high drive capability, rail-to-rail output and high-efficiency [

37]. A simplified schematic of the Class AB amplifier is shown in

Figure 5. The amplifier achieves a simulated DC gain of 120 dB, a unity gain bandwidth of approximately 34 MHz with a phase margin of 60° and consumes 105

$\mathsf{\mu}$A. The simulated input-referred noise is 98 nV/

$\sqrt{Hz}$ at 10 kHz and 35 nV/

$\sqrt{Hz}$ at 100 kHz.

#### 2.1.1. TIA Stability

The architecture of a TIA is shown in

Figure 6. The sensor is modelled by a current source in parallel with a capacitance,

${C}_{IN}$, and resistance,

${R}_{IN}$, which represent the total impedance seen at the input of the amplifier. The feedback resistor

${R}_{F}$ determines the closed-loop DC gain of the amplifier, and the capacitor

${C}_{C}$ is used for compensation, as described in the following section. The noise sources associated with the TIA are modelled as a noise current source,

${i}_{nf}^{2}$, associated with the feedback resistor, and a noise voltage source,

${v}_{inn,op}^{2}$, that represents the noise in the amplifier devices.

The TIA transfer function is given by:

where

${f}_{P}$ = 1/(2

π${R}_{F}$${C}_{C}$) is the pole of the amplifier.

The stability of the amplifier depends on the magnitude of the total input capacitance,

${C}_{IN}$, of the amplifier, which generates a zero in the noise gain,

${G}_{N}\left(f\right)$, given by:

In order to guarantee stability, the TIA needs to have enough phase margin for

$A\left(f\right)$$\beta \left(f\right)$ ≥ 1, where

$A\left(f\right)$ is the open-loop gain of the TIA op-amp and

$\beta \left(f\right)$ is the feedback factor, given by 1/

${G}_{N}\left(f\right)$. The intercept frequency between

$A\left(f\right)$ and

${G}_{N}\left(f\right)$,

${f}_{X}$, is then a critical point for stability analysis. Ensuring that the difference in the slopes between the two curves in ≤20 dB, the TIA will have enough phase margin and grant stability. The compensation capacitor,

${C}_{C}$, can be adjusted in order to introduce a pole and flatten the noise gain response before the crossover frequency.

Figure 6b shows simulated results of the

$A\left(f\right)$ and

${G}_{N}\left(f\right)$ for different values of

${C}_{C}$ of 100 fF and 10 pF, with

${C}_{IN}$ set to 100 pF and

${R}_{F}$ equal to 100 kΩ. If the capacitance is too small, the pole frequency,

${f}_{PUC}$, will be beyond the intersect point and will cause instability. This will result in peaking in the closed-loop response of the TIA.

${C}_{C}$ can then be increased to shift the pole frequency,

${f}_{PC}$, below

${f}_{X}$. The frequency of the pole generated by

${R}_{F}$ and

${C}_{C}$ will set the overall bandwidth of the TIA.

#### 2.1.2. TIA Noise

The equivalent input-referred current noise of the TIA can be derived as the sum of the contributions of device noise from the amplifier devices and the noise of the feedback resistor,

${R}_{F}$. The output voltage noise of the op-amp,

${v}_{on,amp}^{2}$, can be derived with the amplifier configured as a non-inverting stage and is given by:

where

${v}_{inn,op}^{2}$ is the op-amp input-referred voltage noise and

${Z}_{IN}$ and

${Z}_{F}$ are the input and feedback impedances, respectively.

Expanding Equation (4), with

${R}_{IN}$ $>>$ ${R}_{F}$, yields:

The input-referred noise of the op-amp relating to

${v}_{outn,op}^{2}$ can then be derived from Equations (2) and (6) as:

The total equivalent input-referred current noise of the TIA,

${i}_{n,eq}^{2}$ is then given by:

Equation (9) shows how the total equivalent noise of the TIA is inversely proportional to the feedback resistor,

${R}_{F}$. Maximising

${R}_{F}$, therefore, will decrease the input-referred noise at the cost, however, of the TIA bandwidth. The op-amp input-referred noise source,

${v}_{inn,op}^{2}$, is given by:

where the first term in Equation (10) represents the low-frequency flicker (

1/f) noise and the second terms represents the thermal noise.

${K}_{F}$ is the flicker noise coefficient and depends on the CMOS technology, with

${K}_{F}^{\prime}$ =

${K}_{F}/\mu $,

${C}_{OX}$ is the device oxide capacitance and

${g}_{m}^{2}=\mu {C}_{OX}(W/L){I}_{DS}$ is the device transconductance. As EIS is usually performed over a wide frequency range (e.g., 10

${}^{2}$ Hz–10

${}^{6}$ Hz), the frequency range over which the op-amp noise is dominated by either the

1/f or the thermal noise components, can be identified by estimating the noise corner frequency,

${f}_{c}$, when the frequency at which the asymptotes of the

1/f and thermal noise components cross. This is determined from Equation (10) as:

The device sizes and bias current of the op-amp can be selected to set

${f}_{c}$ below the lowest frequency of interest. Combining Equations (9) and (10), we can derive the total input-referred noise of the TIA as:

Equation (12) shows that the overall TIA noise is inversely proportional to the feedback resistors, ${R}_{F}$, and proportional to 1/f at low frequencies (<${f}_{c}$) and ${f}^{2}$ at high frequencies (≫${f}_{c}$).

#### 2.1.3. Automatic Gain Control

The AGC unit tracks the amplitude of the TIA output, ${V}_{OUT\_TIA}$, by means of a PD. The PD consists of an error amplifier, $A3$, a switch, ${M}_{PD}$, a capacitor, ${C}_{PD}$, and a discharge current source, ${I}_{B}$. Amplifier $A3$ senses the difference between the output of the TIA, ${\mathrm{V}}_{OUT\_TIA}$, and the voltage of the PD capacitor, ${V}_{PD}$. As the input signal increases, ${M}_{PD}$ is open, and ${C}_{PD}$ is charged. After the input signal reaches its peak value, it will start decreasing, causing the error amplifier to saturate, due to its high open-loop gain and turn off ${M}_{PD}$. The peak amplitude of the input signal is held on ${C}_{PD}$. As the input signal starts decreasing, ${C}_{PD}$ can be discharged passively, through the output impedance of the PD plus parasitic resistances, or actively, by shorting it to ${V}_{SS}$. A full discharge of the track-and-hold capacitor is acceptable so long as the frequency of the input signal is low. If the frequency of the input signal is high, the peak detector may be too slow at tracking the input signal and charging up to the input signal peak value.

A novel active discharge strategy was employed, whereby the switched current source,

${I}_{B}$, is used to ‘relax’ the capacitor after a peak is detected.

${I}_{B}$ is switched at the frequency of the input signal with variable duty cycle, resulting in three phases of operation. During the tracking phase,

${\varphi}_{0}$ is open, and

${V}_{OUT\_TIA}$ is stored on

${C}_{PD}$. Once the peak amplitude is reached,

${V}_{OUT\_TIA}$ is held on

${C}_{PD}$. After a programmable delay,

${C}_{PD}$ can be actively discharged by

${I}_{B}$. The transient behaviour of the adaptive PD is shown in

Figure 7 for a 10-kHz input signal. The output capacitor is 300 pF, and the switch current is set to 10 nA (

Figure 7a) and 100 nA (

Figure 7b).

The benefit of this architecture over conventional ones is two-fold. Firstly, a large output capacitor can be used, which allows for a more accurate reading of the peak input voltage. In the conventional PD architecture, a trade-off exists between the value of the storing capacitor and the speed or tracking of the PD. Passive discharge limits the response to the PD signals, which rapidly change in amplitude. Secondly, by using a programmable discharge current, the behaviour of the PD can be made independent of the input frequency.

#### 2.2. Voltage-Readout AFE

Each VR channel comprises two stages of fully-differential current-mode variable-gain amplifiers, which provide low-noise and high CMRR [

38]. The architecture of a current-mode amplifier is shown in

Figure 8a and consists of a transconductor (TC) stage and a transimpedance (TI) stage. The TC stage buffers the input voltage, which appears across the resistor,

${R}_{S}$, and results in a current,

${i}_{in}$, flowing in the input stage. This current is then copied to the output stage,

${i}_{out}$, which flows through the load resistor,

${R}_{L}$, and generates an output voltage

${V}_{out}$ with a gain determined by

${R}_{L}/{R}_{S}$. The input TC dominates the noise profile of the current-mode amplifier.

Figure 8b shows a schematic of the input TC with equivalent noise sources. The noise contributions of

${M}_{5}$ are negligible, as it appears as a common-mode signal cancelled by the differential stage. The noise of the current-mirror load,

${M}_{3}$-

${M}_{4}$, is assumed to be much smaller than the noise of the input pair as

${g}_{m3,4}$ $<<$ ${g}_{m1,2}$.

The TC transfer function is given approximately by:

The total output noise current is given by the contributions of the input-pair transistors,

$\overline{{i}_{nM}^{2}}$ and the source-degeneration resistors

$\overline{{i}_{RS}^{2}}$ as:

The total input-referred noise is then determined by Equations (13) and (15) as:

Assuming

${g}_{m}$${R}_{S}>>$ 1, Equation (16) becomes:

The TC input-referred thermal noise is then given by:

Note that a series degeneration resistance was preferred over a shunt topology. If the latter is chosen, the noise contribution of the tail current sources will no longer be negligible, and the total input-referred thermal noise will be increased by a factor of

$4kT(2/3){g}_{mS}$, where

${g}_{mS}$ is the transconductance of the tail current source (equivalent to

${M}_{5}$ in

Figure 8b).

The first stage buffer architecture is shown in

Figure 9. The input pair formed by

${M}_{1}$ and

${M}_{2}$ is degenerated by a source resistor,

${R}_{S}$, resulting in an AC current equal to the ratio between the input voltage,

${V}_{IN}$, and the sum of the source resistance of the input pair (= 1/2

${g}_{m}$) and

${R}_{S}$.

The current is copied to the output by load transistor ${M}_{3}$ and ${M}_{4}$. The gain of the amplifier is proportional to the ratio of the load resistor, ${R}_{L}$ and ${R}_{S}$.

By switching

${R}_{S}$, instead of

${R}_{L}$, the amplifier gain can be varied while keeping its bandwidth approximately constant.

${R}_{S}$ is implemented by a three-bit resistor array, shown in the inset of

Figure 9.

${R}_{L}$ is set to

$2.1$ kΩ, and the unit resistor of the bank is set to

$3.5$ kΩ. Extensive simulations were performed to optimized the sizing of the resistor bank to obtain accurate gain values.

A common-mode feedback (CMFB) circuit was implemented in order to stabilize the output common mode voltage to mid-rail (0.9 V). This is based on a difference-differential amplifier that senses the differential output and injects common-mode current to the amplifier output via current sources

${M}_{14}$ and

${M}_{15}$. The sink transistors

${M}_{10}$–

${M}_{13}$ are scaled to provide a larger current than the source transistors,

${M}_{6}$–

${M}_{9}$, in order to make the CMFB effective. The sink transistors are also switched depending on the output current settings

$SW1$ and

$SW2$ in order to save power when the low gain setting is selected. The gain range can be selected by controlling switches

$SW1$ and

$SW2$ in

Figure 9.

The buffer is biased with a tail current source of 120 $\mathsf{\mu}$A, resulting in the input pair source resistance, $1/{g}_{m}$, of 700 Ω. The output current through each branch is switched between 60 $\mathsf{\mu}$A and 300 $\mathsf{\mu}$A. The on-resistance of the switches was designed to be in the order of 20 Ω, a factor of 10 smaller than the lowest value of ${R}_{S}$, which is set to 200 Ω.

The second stage buffer of the VR AFE is split into a high-frequency channel (HF) and a bandwidth-limited (BW) channel. Both channels share a common

${g}_{m}$-stage, which is equivalent to the

${g}_{m}$-stage of the first-stage buffer. The output stage TIA of the BW channel, shown in

Figure 10, is loaded by a tunable capacitor,

${C}_{L}$, which allows one to select the amplifier bandwidth between 30 kHz and 80 kHz with a six-bit resolution. The capacitor array consists of 500 fF unit capacitors. The BW channel was designed to have a high gain between 12 dB and 42 dB, whereas the HF channel gain ranges between −6 dB and 22 dB.

Due to the large gain range that the VR AFE provides, an offset trimming unit was included. This is based on the use of current-steering DACs, which unbalance the current in the ${g}_{m}$-stage input pair, in order to reduce the output offset voltage to zero. A four-bit DAC biased with a 750-nA current is used for offset coarse calibration, and a six-bit DAC biased with a 10-nA current is used for fine calibration. The offset calibration unit is designed to compensate for input offsets as high as ±20 mV.