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Open AccessArticle

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

Department of Electronic and Electrical Engineering, University College London, WC1E 7JE London, UK
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Author to whom correspondence should be addressed.
Academic Editor: Vittorio M. N. Passaro
Sensors 2016, 16(8), 1159; https://doi.org/10.3390/s16081159
Received: 21 May 2016 / Revised: 15 July 2016 / Accepted: 19 July 2016 / Published: 25 July 2016
(This article belongs to the Section Physical Sensors)

Abstract

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis.
Keywords: analogue readout; electrical impedance spectroscopy (EIS); integrated circuits analogue readout; electrical impedance spectroscopy (EIS); integrated circuits

1. Introduction

Electrical impedance spectroscopy (EIS) has recently gained widespread interest in electrochemical and biomedical research as a tool to study the electrical and physical properties of biological interfaces and to provide valuable diagnostic information about potential pathological conditions of biological cells, tissues and organs. EIS is applied to the measurement of tissue impedance for disease and cancer detection [1,2,3,4] and single-cell analysis [5,6] or used for imaging purposes, in electrical impedance tomography [7]. In the field of electrochemical analysis, EIS can be employed to interrogate functionalized biosensors to detect changes in impedance due to the presence of target analytes, including enzymes, antibodies and DNA [8,9,10], and to perform impedance microbiology [11].
In impedance microbiology, changes in the impedance of an electrochemical cell, formed by a set of microelectrodes immersed in a solution, is measured over time. These changes are due to the cell ionic metabolism, which directly affects the solution conductivity [12,13,14]. Most impedance methods measure only the conductivity of the medium using a pair of electrodes at a fixed frequency using a bipolar configuration. However, the measured impedance is the result of contributions from both the medium impedance and the electrode/interface impedance [15].
The contributions of the electrode and medium impedances are separated by changing the interrogation frequency, where the electrode impedance is predominant at low frequencies (~100 Hz), whereas the medium impedance is more significant at high frequencies (>10 kHz) [15]. The frequency range, however, depends greatly on the size and dimension of the interdigitated electrodes (IDEs) used for the measurements [11].
In addition, conventional impedance microbiology is not suitable for systems where bacterial concentration is determined by measuring the degradation of pH-sensitive polymer coatings of IDEs, which appears as a capacitance change over time [16]. In such cases, a single equivalent model cannot be used to describe the binding process, and the extraction of medium conductivity from the cell impedance profile becomes more complex. Moreover, the IDE capacitance is usually extracted at frequencies of kHz [16], thus increasing the frequency at which the medium conductivity is the sole contribution to the overall impedance.
In order to increase the flexibility of the impedance measurement, dual-mode EIS, based on both bipolar and tetrapolar configurations, can be exploited to measure the medium conductivity independently of the electrode impedance [17,18,19]. The use of two dedicated readouts for electrode and medium impedance measurement, however, puts a serious constraint on the cost-effectiveness and size of this type of impedimetric device, if targeted for point-of-care, wearable or implanted systems. Full integration of multichannel dual-mode readouts can provide low-cost solutions and potentially eliminate set-up time and calibration efforts required for separate units. Conventional EIS systems are designed for either voltage-mode measurements [17,20,21] or current-mode measurements [22,23,24]. Previous efforts in the design of flexible dual-mode systems are limited to the use of discrete units [25,26] or have been designed to detect small changes in solution or electrode impedance [27]. This paper presents the design of a multi-channel dual-mode analogue front-end (AFE) for EIS and bioimpedance analysis, which integrates two readout units for both bipolar (current-mode) and tetrapolar (voltage-mode) measurements.
Figure 1 shows the concept of a dual-mode EIS system, where an array of IDEs is interrogated by both a voltage source and current source for both bipolar and tetrapolar measurements. In the former case, an AC voltage is applied across two terminals of one or more electrodes, and a transimpedance amplifier (TIA) is used to bias the electrode to a desired DC potential and to convert the IDE current into a voltage. The real and imaginary parts of the electrode admittance can then be extracted using a demodulator and converted into digital signals by an analogue-to-digital converter (ADC) for further processing of the electrode capacitive and resistive components. In the latter case, a differential current is applied through two terminals of one IDE, and differential voltages are measured by different IDEs, placed at different locations within the sample solution, using instrumentation amplifiers (INAs). This allows for the conductivity of the solution to be determined. The proposed integrated AFE is designed to interface with a set of carbon screen-printed IDEs coated with a pH-sensitive polymer (Eudragit S100) and shown in the inset of Figure 2. The impedance of the electrode shows nearly pure capacitive behaviour at frequencies around 20 kHz [16], thus allowing one to relate the change in capacitance of the electrode (from fully-coated to a degree of degradation) during a binding process to the concentration of the target analytes. The change of capacitance has been quantified (Figure 2) during wet experiments to a range of four orders of magnitude between a few pF to a few nF [16]. At 20 kHz the impedance of the IDE ranges approximately between 1 kΩ and 500 kΩ–1 MΩ. By using an excitation voltage of 10 mV, the resulting electrode current ranges between 10–20 nA and 10 μ A. The capacitance of the dry electrode ranges between 2 pF and 5 pF.
Although full characterization of the IDEs is beyond the scope of this paper, the performance of the AFE has been tested by measuring the capacitance of dry IDEs, the impedance of the electrodes in different buffer solutions and, concurrently, the conductivity of different solutions.

2. Analogue Front-End Chip

The architecture of the EIS AFE chip is shown in Figure 3. The chip allows for fully-differential voltage readout (VR, four channels) and single-ended rail-to-rail output current readout (CR, two channels). The CR channels are equipped with an automatic gain control (AGC) unit that allows extension of the signal dynamic range. The AGC comprises a peak detector (PD), a comparison stage (COMP) and a control logic unit (off-chip). In the VR mode, bandwidth-limited (BW) low-noise operation (up to 80 kHz) or high-frequency recording (HF, up to 8 MHz) can be selected. The BW channel can be used when extracellular voltage recording is needed in a frequency range from sub-Hz to kHz [28]. In this case, chopper-stabilized op-amps switching at a frequency of 100 kHz are used to allow for low-noise measurements to be performed. The HF channel allows for electrochemical sensing and solution conductivity mapping at frequencies higher than 10 kHz and up to 1 MHz [11]. Impedance measurements in the MHz regime are more sensitive to intracellular changes and can be used to characterize the cell membrane impedance [29]. Each channel has programmable gain stages, operational bandwidth and enable signals that can turn off entire sections of the chip to save power. The chip is powered by a single 1.8-V supply. The common-mode voltage, V C M , is set to 0.9 V by an internal voltage generator. The chip can be programmed via a microcontroller using a serial-to-peripheral interface (SPI) consisting of 11 registers. The chip is also equipped with two 10-bit successive-approximation ADCs with a maximum sampling rate of 200 kS/s. The output of the ADCs can be read serially though an on-chip parallel-in-serial-out (PISO) interface. The analogue outputs of the VR and CR units are directly available externally and can be readily connected to the on-chip ADCs for digitization. The operation of the chip described in this paper was limited to spectroscopy studies in a frequency range between 100 Hz and 100 kHz.

2.1. Current-Readout AFE

The CR-AFE consists of a TIA input stage followed by a programmable gain amplifier (PGA) stage controlled by an AGC unit, as shown in Figure 4. The TIA can be implemented using either discrete-time (DT) or continuous-time (CT) architectures. DT topologies offer very low-noise performance, but are limited to low frequency operation due to the need to reset the integrating capacitor [30,31,32,33]. Among CT topologies, integrator-differentiator (ID) and resistor-feedback (RF) architectures are suitable candidates to implement TIAs in CMOS [34,35]. ID structures have several advantages, including low-noise and high-bandwidth operation [36], but require the implementation of very large resistors or DC-feedback loops to provide a DC current path, which introduces complexity and stability issues.
The TIA in this paper was implemented by a resistor-feedback op-amp configuration. This offers a straightforward implementation that can handle DC currents. In addition, input currents in the range of nA– μ A, consistent with the sensors used in this study, require small TIA gains (kΩ) to avoid the saturation of the amplifier, which can be better implemented using resistors. The gain of the TIA is programmable by switching the feedback resistor to 10 kΩ, 50 kΩ or 100 kΩ. A resistor-feedback programmable-gain amplifier is used to perform further amplification between 1 V/V and 14 V/V using G 0 and 4 V/V and 54 V/V using switch G 1 . Fine gain tuning is controlled by changing the input resistance of the amplifier, R 1 , so that the PGA gain is given by:
A P G A = - R 2 R 1 = - ( G 0 R u + 4 G 1 R u ) · n = 0 3 d n 2 n R u
where R 2 is the feedback resistance and R u is the value of the unit resistor of the array, d is the control code of the input resistor array and n is the number of bits and is equal to four.
Amplifiers A 1 and A 2 in Figure 4 are implemented by a two-stage Class AB amplifier with a minimum-current selector for high drive capability, rail-to-rail output and high-efficiency [37]. A simplified schematic of the Class AB amplifier is shown in Figure 5. The amplifier achieves a simulated DC gain of 120 dB, a unity gain bandwidth of approximately 34 MHz with a phase margin of 60° and consumes 105 μ A. The simulated input-referred noise is 98 nV/ H z at 10 kHz and 35 nV/ H z at 100 kHz.

2.1.1. TIA Stability

The architecture of a TIA is shown in Figure 6. The sensor is modelled by a current source in parallel with a capacitance, C I N , and resistance, R I N , which represent the total impedance seen at the input of the amplifier. The feedback resistor R F determines the closed-loop DC gain of the amplifier, and the capacitor C C is used for compensation, as described in the following section. The noise sources associated with the TIA are modelled as a noise current source, i n f 2 , associated with the feedback resistor, and a noise voltage source, v i n n , o p 2 , that represents the noise in the amplifier devices.
The TIA transfer function is given by:
G T I A ( f ) = v O U T i s ( f ) = - R F 1 + j f f P
where f P = 1/(2π R F C C ) is the pole of the amplifier.
The stability of the amplifier depends on the magnitude of the total input capacitance, C I N , of the amplifier, which generates a zero in the noise gain, G N ( f ) , given by:
G N ( f ) = 1 + j ω R F ( C I N + C C ) 1 + j ω R F C C
In order to guarantee stability, the TIA needs to have enough phase margin for A ( f ) β ( f ) ≥ 1, where A ( f ) is the open-loop gain of the TIA op-amp and β ( f ) is the feedback factor, given by 1/ G N ( f ) . The intercept frequency between A ( f ) and G N ( f ) , f X , is then a critical point for stability analysis. Ensuring that the difference in the slopes between the two curves in ≤20 dB, the TIA will have enough phase margin and grant stability. The compensation capacitor, C C , can be adjusted in order to introduce a pole and flatten the noise gain response before the crossover frequency. Figure 6b shows simulated results of the A ( f ) and G N ( f ) for different values of C C of 100 fF and 10 pF, with C I N set to 100 pF and R F equal to 100 kΩ. If the capacitance is too small, the pole frequency, f P U C , will be beyond the intersect point and will cause instability. This will result in peaking in the closed-loop response of the TIA. C C can then be increased to shift the pole frequency, f P C , below f X . The frequency of the pole generated by R F and C C will set the overall bandwidth of the TIA.

2.1.2. TIA Noise

The equivalent input-referred current noise of the TIA can be derived as the sum of the contributions of device noise from the amplifier devices and the noise of the feedback resistor, R F . The output voltage noise of the op-amp, v o n , a m p 2 , can be derived with the amplifier configured as a non-inverting stage and is given by:
v o u t n , o p 2 = v i n n , o p 2 1 + Z F Z I N 2
where v i n n , o p 2 is the op-amp input-referred voltage noise and Z I N and Z F are the input and feedback impedances, respectively.
Expanding Equation (4), with R I N > > R F , yields:
v o u t n , o p 2 = v i n n , o p 2 1 + 4 π 2 f 2 R F 2 ( C C + C I N ) 2 ( 1 + 4 π 2 f 2 C C 2 R F 2 )
The input-referred noise of the op-amp relating to v o u t n , o p 2 can then be derived from Equations (2) and (6) as:
(6) i i n n , o p 2 = v o u t n , o p 2 G T I A 2 (7) = v i n n , o p 2 1 + 4 π 2 f 2 R F 2 ( C C + C I N ) 2 R F 2
The total equivalent input-referred current noise of the TIA, i n , e q 2 is then given by:
(8) i n , e q 2 ¯ = i n f 2 ¯ + i i n n , o p 2 ¯ (9) = 4 k T R F + v i n n , o p 2 ¯ 1 + 4 π 2 f 2 R F 2 ( C C + C I N ) 2 R F 2
Equation (9) shows how the total equivalent noise of the TIA is inversely proportional to the feedback resistor, R F . Maximising R F , therefore, will decrease the input-referred noise at the cost, however, of the TIA bandwidth. The op-amp input-referred noise source, v i n n , o p 2 , is given by:
v i n n , o p 2 ¯ = K F W L C O X 2 1 f + 16 k T 3 g m
where the first term in Equation (10) represents the low-frequency flicker (1/f) noise and the second terms represents the thermal noise. K F is the flicker noise coefficient and depends on the CMOS technology, with K F = K F / μ , C O X is the device oxide capacitance and g m 2 = μ C O X ( W / L ) I D S is the device transconductance. As EIS is usually performed over a wide frequency range (e.g., 10 2 Hz–10 6 Hz), the frequency range over which the op-amp noise is dominated by either the 1/f or the thermal noise components, can be identified by estimating the noise corner frequency, f c , when the frequency at which the asymptotes of the 1/f and thermal noise components cross. This is determined from Equation (10) as:
f c = 6 K F I D 16 k T g m C O X L 2
The device sizes and bias current of the op-amp can be selected to set f c below the lowest frequency of interest. Combining Equations (9) and (10), we can derive the total input-referred noise of the TIA as:
i i n n , t 2 ¯ = 4 k T R F + K F W L C O X 2 g m 1 f + 16 k T 3 g m 2 1 + 4 π 2 f 2 R F 2 ( C C + C I N ) 2 R F 2
Equation (12) shows that the overall TIA noise is inversely proportional to the feedback resistors, R F , and proportional to 1/f at low frequencies (< f c ) and f 2 at high frequencies (≫ f c ).

2.1.3. Automatic Gain Control

The AGC unit tracks the amplitude of the TIA output, V O U T _ T I A , by means of a PD. The PD consists of an error amplifier, A 3 , a switch, M P D , a capacitor, C P D , and a discharge current source, I B . Amplifier A 3 senses the difference between the output of the TIA, V O U T _ T I A , and the voltage of the PD capacitor, V P D . As the input signal increases, M P D is open, and C P D is charged. After the input signal reaches its peak value, it will start decreasing, causing the error amplifier to saturate, due to its high open-loop gain and turn off M P D . The peak amplitude of the input signal is held on C P D . As the input signal starts decreasing, C P D can be discharged passively, through the output impedance of the PD plus parasitic resistances, or actively, by shorting it to V S S . A full discharge of the track-and-hold capacitor is acceptable so long as the frequency of the input signal is low. If the frequency of the input signal is high, the peak detector may be too slow at tracking the input signal and charging up to the input signal peak value.
A novel active discharge strategy was employed, whereby the switched current source, I B , is used to ‘relax’ the capacitor after a peak is detected. I B is switched at the frequency of the input signal with variable duty cycle, resulting in three phases of operation. During the tracking phase, ϕ 0 is open, and V O U T _ T I A is stored on C P D . Once the peak amplitude is reached, V O U T _ T I A is held on C P D . After a programmable delay, C P D can be actively discharged by I B . The transient behaviour of the adaptive PD is shown in Figure 7 for a 10-kHz input signal. The output capacitor is 300 pF, and the switch current is set to 10 nA (Figure 7a) and 100 nA (Figure 7b).
The benefit of this architecture over conventional ones is two-fold. Firstly, a large output capacitor can be used, which allows for a more accurate reading of the peak input voltage. In the conventional PD architecture, a trade-off exists between the value of the storing capacitor and the speed or tracking of the PD. Passive discharge limits the response to the PD signals, which rapidly change in amplitude. Secondly, by using a programmable discharge current, the behaviour of the PD can be made independent of the input frequency.

2.2. Voltage-Readout AFE

Each VR channel comprises two stages of fully-differential current-mode variable-gain amplifiers, which provide low-noise and high CMRR [38]. The architecture of a current-mode amplifier is shown in Figure 8a and consists of a transconductor (TC) stage and a transimpedance (TI) stage. The TC stage buffers the input voltage, which appears across the resistor, R S , and results in a current, i i n , flowing in the input stage. This current is then copied to the output stage, i o u t , which flows through the load resistor, R L , and generates an output voltage V o u t with a gain determined by R L / R S . The input TC dominates the noise profile of the current-mode amplifier. Figure 8b shows a schematic of the input TC with equivalent noise sources. The noise contributions of M 5 are negligible, as it appears as a common-mode signal cancelled by the differential stage. The noise of the current-mirror load, M 3 - M 4 , is assumed to be much smaller than the noise of the input pair as g m 3 , 4 < < g m 1 , 2 .
The TC transfer function is given approximately by:
i o u t = v i n R S + 2 g m 1 , 2
The total output noise current is given by the contributions of the input-pair transistors, i n M 2 ¯ and the source-degeneration resistors i R S 2 ¯ as:
(14) i o u t n 2 ¯ = 2 i n M 1 , 2 2 ¯ + 2 i R S 2 ¯ (15) = 16 3 k T g m 1 , 2 + K F C O X W L 1 f + 8 k T R S
The total input-referred noise is then determined by Equations (13) and (15) as:
v i n n 2 ¯ = 2 i o u t n 2 ¯ R S + 2 g m 1 , 2 2
Assuming g m R S > > 1, Equation (16) becomes:
v i n n 2 ¯ = R S 16 3 k T g m 1 , 2 R S + K F R S C O X W L 1 f + 8 k T
The TC input-referred thermal noise is then given by:
v i n n , t h 2 ¯ = 8 k T 1 + 2 3 g m 1 , 2 R S
Note that a series degeneration resistance was preferred over a shunt topology. If the latter is chosen, the noise contribution of the tail current sources will no longer be negligible, and the total input-referred thermal noise will be increased by a factor of 4 k T ( 2 / 3 ) g m S , where g m S is the transconductance of the tail current source (equivalent to M 5 in Figure 8b).
The first stage buffer architecture is shown in Figure 9. The input pair formed by M 1 and M 2 is degenerated by a source resistor, R S , resulting in an AC current equal to the ratio between the input voltage, V I N , and the sum of the source resistance of the input pair (= 1/2 g m ) and R S .
The current is copied to the output by load transistor M 3 and M 4 . The gain of the amplifier is proportional to the ratio of the load resistor, R L and R S .
By switching R S , instead of R L , the amplifier gain can be varied while keeping its bandwidth approximately constant. R S is implemented by a three-bit resistor array, shown in the inset of Figure 9. R L is set to 2 . 1 kΩ, and the unit resistor of the bank is set to 3 . 5 kΩ. Extensive simulations were performed to optimized the sizing of the resistor bank to obtain accurate gain values.
A common-mode feedback (CMFB) circuit was implemented in order to stabilize the output common mode voltage to mid-rail (0.9 V). This is based on a difference-differential amplifier that senses the differential output and injects common-mode current to the amplifier output via current sources M 14 and M 15 . The sink transistors M 10 M 13 are scaled to provide a larger current than the source transistors, M 6 M 9 , in order to make the CMFB effective. The sink transistors are also switched depending on the output current settings S W 1 and S W 2 in order to save power when the low gain setting is selected. The gain range can be selected by controlling switches S W 1 and S W 2 in Figure 9.
The buffer is biased with a tail current source of 120 μ A, resulting in the input pair source resistance, 1 / g m , of 700 Ω. The output current through each branch is switched between 60 μ A and 300 μ A. The on-resistance of the switches was designed to be in the order of 20 Ω, a factor of 10 smaller than the lowest value of R S , which is set to 200 Ω.
The second stage buffer of the VR AFE is split into a high-frequency channel (HF) and a bandwidth-limited (BW) channel. Both channels share a common g m -stage, which is equivalent to the g m -stage of the first-stage buffer. The output stage TIA of the BW channel, shown in Figure 10, is loaded by a tunable capacitor, C L , which allows one to select the amplifier bandwidth between 30 kHz and 80 kHz with a six-bit resolution. The capacitor array consists of 500 fF unit capacitors. The BW channel was designed to have a high gain between 12 dB and 42 dB, whereas the HF channel gain ranges between −6 dB and 22 dB.
Due to the large gain range that the VR AFE provides, an offset trimming unit was included. This is based on the use of current-steering DACs, which unbalance the current in the g m -stage input pair, in order to reduce the output offset voltage to zero. A four-bit DAC biased with a 750-nA current is used for offset coarse calibration, and a six-bit DAC biased with a 10-nA current is used for fine calibration. The offset calibration unit is designed to compensate for input offsets as high as ±20 mV.

3. Measurements

3.1. CR AFE

Figure 11 shows the frequency response of the CR AFE TIA in a frequency range between 100 Hz and 1 MHz. The gain of the TIA was measured to be 10 kΩ, 50 kΩ and 100 kΩ (Figure 11a). The bandwidth of the TIA was measured to be 1.59 MHz, 310 kHz and 159 kHz, respectively, when using a feedback capacitor of 10 pF in all cases. The measurements agree with the theoretical bandwidth of the TIA given by 1 / ( 2 π R F C F ) . Figure 11b shows the TIA frequency response at a gain of 100 kHz for different feedback capacitors (with values reported in the figure legend). The minimum value of the feedback capacitor is set to 10 pF in order to avoid the occurrence of unwanted gain increase (gain peaking) at high frequencies, as shown in the figure for a capacitor value of 1.5 pF.
The linearity of the TIA was measured by sweeping an input test current source between 1 nA and 100 μ A at a frequency of 10 kHz. The dynamic range of the TIA is shown in Figure 12a at different gains. The linear range was measured between the minimum and maximum input current, which resulted in a deviation of the gain larger than 1 dB from its nominal value. This range was measured to be 100 nA–100 μ A for a gain of 10 kΩ, 50 nA–20 μ A for a gain of 50 kΩ and 10 nA–1 μ A for a gain of 100 kΩ, resulting in an overall linear dynamic range between 10 nA and 100 μ A, or 80 dB.
The gain and linearity of the PGA were measured by setting the TIA input current to 1 μ A and the TIA gain to 10 kΩ, and they are shown in Figure 12b. The gain of the PGA was measured in a range between 1 and 13.8 V/V (0–23 dB) for gain setting G 0 and 5.7 and 55 V/V (15–35 dB) for gain setting G 1 .
The performance of the PD was measured in the time-domain, as the same time as the measurements of the performance of the TIA reported above. In order to measure the output range of the PD, an external 1-nF capacitor was connected to the output of the PD and I B was switched off. The output DC voltage was measured with a multimeter for input currents varying between 1 nA and 100 μ A and is reported in Figure 13. The figure shows that the PD dynamic range extends from 10 nA–100 μ A, which is consistent with the TIA linear range.
Figure 14 shows the real-time operation of the PD under different conditions in response to a 1- μ A input current at a frequency of 10 kHz. In the case shown in Figure 14a, I B is off, and V P D tracks the input signal, while this is increased and passively discharges after the input peak amplitude has been reached. In the cases reported in Figure 14b,c, I B is switched at the frequency of the input signal with a duty cycle of 50% and 25%, respectively. The three operating phases described in Section 2.1 are clearly visible. After the tracking phase, the peak amplitude of the input signal is held on V P D as long as I B is off and can, therefore, be accurately sampled during this phase. As I B is turned on, C P D is discharged to a level that depends on the amplitude of I B . By varying the duty cycle of I B _ C L K , the duration of two sampling phases (before and after the capacitor discharging) can be controlled. Finally, the PD can be forced to behave equivalently to shorting C P D to V S S by further increasing the amplitude of I B as shown in Figure 14b.

3.2. VR AFE

The frequency response of the VR AFE was measured between 100 Hz and 10 MHz by applying a 100-mV fully differential input signal with a DC offset of 0.9 V. The bandwidth of the BW channel was measured by varying the value of the load capacitance. A range between 30 kHz and 80 kHz is achievable in steps of approximately 800 Hz.
The frequency response of the HF channel is shown in Figure 15a for different gain settings. The bandwidth of the buffer was measured to be approximately 8 MHz and is substantially independent of the amplifier gain. The amplifier measured CMRR is shown in Figure 15b for a gain of 20 dB. At low frequencies below 1 kHz, the CMRR is greater than 84 dB.
The gain range and linearity of the VR AFE is reported in Figure 16 for both BW and HF channels. The overall gain can be set between −6 dB and 22 dB for the HF channel and between 12 dB and 42 dB for the BW channel.
The noise of the TIA and INA was measured using a spectrum analyser (MDO41046) within a bandwidth between 1 kHz and 1 MHz and a resolution bandwidth of 1 kHz. The inputs were grounded, and the gains were set to the maximum value (100 kΩ for the TIA and 42 dB for the INA). The noise floor of the TIA was measured at 100 kHz to be 450 fA/ H z , and the noise floor of the INA was measured to be 10 nV/ H z .
Figure 17 shows a microphotograph of the chip implemented in a 0.18- μ m CMOS process. The chip includes 84 pads and has a total area of 10 mm 2 . The active area is 4 . 2 mm 2 . The measured performance of the chip is summarized in Table 1.

3.3. Impedance Measurements

The chip was interfaced to a set of IDEs in different aqueous solutions. A set of IDEs consisted of bare carbon interdigitated screen-printed electrodes. Another set of IDEs was coated with pH-sensitive polymer (Eudragit S 100).
The IDEs were excited by a small AC signal. Voltage and current recordings were stored on a computer and coupled with a digital signal processing software unit (MATLAB) to extract impedance values for a range of frequencies between 100 Hz and 100 kHz (10 points per decade). The VR AFE HF channel was used in these experiments to measure the voltage profiles in the solutions. Chopper stabilization was not enabled during this set of experiments, due to the frequency range of the measurements and the measured current and voltage levels. The chopping switches were disabled by tying their gates to the supplies. The upper limit of 100 kHz was set by the maximum sampling rate of the on-chip 10-bit ADC of 200 kS/s.
System calibration was performed by measuring the impedance magnitude and phase of known resistor and capacitor values and correcting for gain and phase factors during post-processing.
The experimental set-up is shown in Figure 18. One IDE was excited with an AC voltage of an amplitude between 10 mV and 100 mV, and the current, I I D E , was measured using the CR channel of the chip. A tetrapolar configuration was used to measure the voltage profiles in the solution in response to a differential current, I E X T , of 1 mA.
Impedance spectra of bare and polymer-coated IDEs in DI water and pH 5.0 buffer solution were measured and compared to recordings obtained using a commercial impedance analyser (Wayne Kerr 6220B). The excitation voltage was set to 10 mV, and the gain of the CR AFE was set to 100 kΩ, by observing the lowest error compared to lower gains. Results are shown in Figure 19a,b.
The measurements show close matching between the impedance points recorded with the chip and the commercial system. The maximum discrepancies between the bare IDE cell measurements were 6% a 100 Hz and 9% at 400 Hz in pH 5.0 and DI water, respectively. For the polymer IDE cell, the largest error was estimated to be 17.4% at 100 kHz and 20.2% at 500 Hz pH 5.0 and DI water, respectively. The large error at low frequencies can be attributed to the 1/f noise of the front-end, whereas the error at high frequencies is due to the bandwidth of the CR AFE, which was set to 159 kHz. Within the frequency range of 10 kHz–100 kHz, measurement accuracy is within 5% with errors as low as 0.2% in the case of bare IDE in pH 5.0 buffer solution.
The capacitance of the bare IDE was extracted by measuring the impedance of the dry electrode within a frequency range between 10 kHz and 100 kHz, at which the electrode shows nearly pure capacitive behaviour. Figure 19c shows the measured extracted capacitance. The average measured capacitance across the frequency range was 2.05 pF, closely matching the average capacitance of 2.23 pF measured with the impedance analyser. Figure 19d shows measured voltages in saline solutions with different conductivities using the tetrapolar configuration in Figure 18c. The conductivity of the solution was changed by adding different concentrations of NaCl and measured with a conductivity meter (with values reported in the figure). A differential 1-mA current was applied to one IDE, and the voltage, V S O L , was measured differentially across the second IDE. The resulting voltages at 10 kHz were measure to be 0.74 mV, 1.2 mV and 13.5 mV for conductivities of 0.3 S/m, 8.4 S/m and 40 S/m, respectively. The ratio between I E X T and V S O L was calculated with values measured at a frequency of 10 kHz and resulted in extracted conductivity values of 0.34 S/m 8.8 S/m and 37 S/m, respectively. Figure 19 shows how the chip is capable of concurrent measurement of both IDE impedance and solution conductivities.
A comparison between the presented system and a number of AFEs developed for EIS is shown in Table 2. The system reported in this work compares favourably in terms of configurability, gain and frequency range and power consumption.

4. Conclusions

This paper has presented the design and measured performance of a dual-mode analogue front-end chip, capable of parallel measurement of multi-channel current and voltage profiles for EIS. The adoption of the dual-mode EIS microsystem can be beneficial in the field of impedance microbiology by enabling separate measurements of the electrode/interface impedance and the medium impedance, as an alternative to conventional methods of determining impedance contributions by changing the interrogation frequency [15]. A dual-mode EIS can also be potentially employed to measure cellular behaviour at the electrode interface and at a distance from the surface of the electrodes [39] and to generate cellular impedance tomographic maps [28]. This system compares favourably to previous dual-mode systems [25,26,27]. It achieves high linearity, wideband operation and wide dynamic range and provides a potential cost-effective interface for several EIS applications. The voltage sensing unit provides very wide operation bandwidth up to 8 MHz and a large linear gain range from −6 dB of attenuation to 42 dB of amplification, achieving a CMRR greater than 80 dB.
The current sensing unit provides 80 dB of linear range and a current detection limit as low as 10 nA with configurable gain and bandwidth settings. The flexibility is further enhanced by a dynamic peak detector unit, which can be operated within an automatic gain control loop to optimize the channel dynamic range under different measurement conditions. The use of small values for the feedback resistor in the TIA (Figure 4) was required to accommodate large currents flowing through the IDE (>100 nA). This, however, results in larger input-referred current noise as compared to alternative structures [33,35]. Nevertheless, given the relatively large input currents, a more power-efficient architecture was preferred. The authors are further developing the system toward a fully-integrated dual-mode EIS platform, comprised of a multi-channel dual-mode arbitrary waveform generator, a dual-mode analogue readout interface and a digital impedance processing unit [40].

Acknowledgments

This work is supported by the Engineering and Physical Sciences Research Council (EPSRC) Interdisciplinary Research Collaborations in Early-Warning Sensing Systems for Infectious Disease under Grant Reference EP/K031953/1.

Author Contributions

V. Valente conceived of, designed and tested the CMOS chip and wrote the paper. A. Demosthenous assisted in the design of the chip and contributed to the revision of the paper.

Conflicts of Interest

The authors declare no conflict of interest.

Abbreviations

The following abbreviations are used in this manuscript:
IDEs
Interdigitated electrodes
EIS
Electrical impedance spectroscopy
AFE
Analogue front-end
VR
Voltage readout
CR
Current readout
TIA
Transimpedance amplifier
INA
Instrumentation amplifier
AGC
Automatic gain control
PD
Peak detector
SPI
Serial-to-peripheral interface
PISO
Parallel-in-serial-out
HF
High frequency
BW
Bandwidth limited
CMFB
Common-mode feedback
CMRR
Common-mode rejection ratio

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Figure 1. Conceptual arrangement of a dual-mode EIS measurement system with arrays of interdigitated electrodes (IDEs) to measure solution impedance and electrode/interface impedance. The solution impedance can be measured using a tetrapolar configuration by injecting a differential current, I E X T , through an electrode and measuring the differential voltage across a second electrode. Electrode/interface impedance can be measured by exciting an electrode with a voltage source, V E X T , and reading the current flowing through the electrode. In the example in the figure, the same external source is used on multiple electrodes.
Figure 1. Conceptual arrangement of a dual-mode EIS measurement system with arrays of interdigitated electrodes (IDEs) to measure solution impedance and electrode/interface impedance. The solution impedance can be measured using a tetrapolar configuration by injecting a differential current, I E X T , through an electrode and measuring the differential voltage across a second electrode. Electrode/interface impedance can be measured by exciting an electrode with a voltage source, V E X T , and reading the current flowing through the electrode. In the example in the figure, the same external source is used on multiple electrodes.
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Figure 2. Example of measured capacitance over time of an IDE test strip shown in the figure inset. The average values of the capacitance are reported in the text for different types of IDEs. For convenience, only the first 150 s of measurement are shown. The values reported in the text refer to the steady state value after 1800 s. Each IDE test strip consists of two equal IDEs with an overall area (W × d) of 3 × 5.5 mm 2 . Each IDE consists of five digits of a length of 2 mm, a width of 0.3 mm and a spacing of 0.3 mm. The distance between the IDEs is 3 mm.
Figure 2. Example of measured capacitance over time of an IDE test strip shown in the figure inset. The average values of the capacitance are reported in the text for different types of IDEs. For convenience, only the first 150 s of measurement are shown. The values reported in the text refer to the steady state value after 1800 s. Each IDE test strip consists of two equal IDEs with an overall area (W × d) of 3 × 5.5 mm 2 . Each IDE consists of five digits of a length of 2 mm, a width of 0.3 mm and a spacing of 0.3 mm. The distance between the IDEs is 3 mm.
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Figure 3. Chip architecture.
Figure 3. Chip architecture.
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Figure 4. Architecture of the current-mode channel with automatic gain compensation.
Figure 4. Architecture of the current-mode channel with automatic gain compensation.
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Figure 5. Schematic of the Class AB op-amp used to implement the TIA and the programmable gain amplifier (PGA).
Figure 5. Schematic of the Class AB op-amp used to implement the TIA and the programmable gain amplifier (PGA).
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Figure 6. (a) Schematic of a TIA with the sensor model and noise sources; (b) simulated open-loop gain of the TIA op-amp and noise gain with different values of the compensation capacitor, C C .
Figure 6. (a) Schematic of a TIA with the sensor model and noise sources; (b) simulated open-loop gain of the TIA op-amp and noise gain with different values of the compensation capacitor, C C .
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Figure 7. Transient simulation of the adaptive PD unit at 10 kHz. The relaxation current is set to (a) 10 nA and (b) 100 nA and switched at the same frequency as the input signal with a 25% duty cycle. The output capacitor of the PD (external) is 300 pF.
Figure 7. Transient simulation of the adaptive PD unit at 10 kHz. The relaxation current is set to (a) 10 nA and (b) 100 nA and switched at the same frequency as the input signal with a 25% duty cycle. The output capacitor of the PD (external) is 300 pF.
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Figure 8. Current-mode amplifier model. (a) Architecture (b) schematic of the input TC with noise sources.
Figure 8. Current-mode amplifier model. (a) Architecture (b) schematic of the input TC with noise sources.
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Figure 9. Schematic of the VR AFE INA.
Figure 9. Schematic of the VR AFE INA.
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Figure 10. Schematic of the BW-limited TIA stage of the INA.
Figure 10. Schematic of the BW-limited TIA stage of the INA.
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Figure 11. Measured frequency response of the TIA for (a) different gain settings and (b) different feedback capacitor values at a gain of 100 kΩ.
Figure 11. Measured frequency response of the TIA for (a) different gain settings and (b) different feedback capacitor values at a gain of 100 kΩ.
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Figure 12. Measured range and linearity of the (a) TIA and (b) PGA.
Figure 12. Measured range and linearity of the (a) TIA and (b) PGA.
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Figure 13. Measured output range of the PD versus TIA input current, with an external capacitor of 300 pF. Inset: Output profile for an input current range between 1 nA and 100 μ A.
Figure 13. Measured output range of the PD versus TIA input current, with an external capacitor of 300 pF. Inset: Output profile for an input current range between 1 nA and 100 μ A.
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Figure 14. Real-time operation of the peak detector.
Figure 14. Real-time operation of the peak detector.
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Figure 15. Measured (a) frequency response and (b) CMRR at 20 dB of the INA.
Figure 15. Measured (a) frequency response and (b) CMRR at 20 dB of the INA.
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Figure 16. Measured VR AFE gain range for different gain settings.
Figure 16. Measured VR AFE gain range for different gain settings.
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Figure 17. EIS AFE chip microphotograph.
Figure 17. EIS AFE chip microphotograph.
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Figure 18. Experimental set-up. Two sets of IDEs were used in the experiments to measure the interface impedance and the solution conductivity, which was changed by varying the concentration of NaCl.
Figure 18. Experimental set-up. Two sets of IDEs were used in the experiments to measure the interface impedance and the solution conductivity, which was changed by varying the concentration of NaCl.
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Figure 19. Impedance measurements. (a) Impedance of a bare IDE and (b) a polymer-coated IDE in DI water and pH 5.0 buffer solution; (c) capacitance of a dry IDE versus frequency and (d) tetrapolar voltage measurements in saline solutions of different conductivities.
Figure 19. Impedance measurements. (a) Impedance of a bare IDE and (b) a polymer-coated IDE in DI water and pH 5.0 buffer solution; (c) capacitance of a dry IDE versus frequency and (d) tetrapolar voltage measurements in saline solutions of different conductivities.
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Table 1. Summary of chip measured performance.
Table 1. Summary of chip measured performance.
PARAMETERUNITSVALUE
Technology-0.18 μ m CMOS
Number of pads-84
Chip active areamm 2 4.2
Supply voltageV1.8
VR AFE
Gain rangedB−6 to 42
BW LFkHz30 to 80
BW HFMHz8
CMRRdB84.4
Max current consumption μ A690
CR AFE
TIA gain10, 50, 100
TIA dynamic rangedB80
PGA gainV/V1 to 55
Max current consumption μ A530
Table 2. Performance comparison of the analogue front-end for EIS.
Table 2. Performance comparison of the analogue front-end for EIS.
PARAMETERCHThis Work[35][33][21][4]
Technology 0.18 μ m CMOS0.35 μ m CMOS0.35 μ m CMOS0.18 μ m CMOS0.18 μ m CMOS
Supply voltage (V) 1.83.33.351.8
Readout modality Dual-modeCurrentCurrentVoltageVoltage
Gain (kO)CR10, 50, 10060,000---
VR−6 dB–42 dB--15 dB–32 dB18 dB–60 dB
Bandwidth (Hz)CR100 k–1.59 M4 M4k--
VR8 M--76 k100 k
Resolution (bits) 10--1014
Power/channel (mW)CR1.245523 -
VR0.95--653.4
i i n n (fA/ H z )CR45045--
v i n n (nV/ H z )VR10---36
1 Measured at 100 kHz with gain set to 100 kΩ; 2 measured at 100 kHz with gain set to 42 dB.
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