# A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording

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## Abstract

**:**

## 1. Introduction

- A microfluidic device allowing stable, reliable and automatic BLM formation.
- A fast low-noise electronic interface ables to acquire pA currents.
- A compact, robust and scalable system containing an array of microfluidic devices and electronic interface.

_{R}with A/D sampling at frequency f

_{S}>> f

_{R}, disregarding the reset behavior. In this way the folding noise due to sampling is reduced and the bandwidth is not limited by the reset. A second-order delta-sigma (ΔΣ) analog-to-digital converter (ADC) oversamples the signal at 10 MHz and generates a 1-bit 10 MS/s digital stream that is decimated by digital FIR filter implemented on a FPGA. This solution simplifies the signal routing when concurrently acquiring a great number of channels, and gives a flexible bandwidth-noise trade-off to the user by acting on the oversampling ratio (OSR) parameter in the decimator filter [22]. The system also integrates a digital offset cancellation loop (OCL) balancing any voltage offset from Ag/AgCl electrodes. The amplifier has been validated, together with microfluidic devices by measuring the activity of three different ion channels: gramicidin-A, α-haemolysin and KcsA potassium channels.

## 2. Proposed Transimpedance Amplifier

#### 2.1. Ion Channel Recording Platform

- Three disposable microfluidic devices manufactured on a glass substrate holding 4 BLMs each [12].
- A small PCB hosting two CMOS 2-channel low-noise current-to-digital amplifiers that can measure pA currents.
- A motherboard with a digital control unit implemented in a Field Programmable Gate Array (FPGA) [11].

_{STIM}to the ion channel through the low-noise amplifier (LNA) virtual short circuit; this stimulus could be either a constant voltage or a time-varying voltage. The ionic current flowing through the ion channel is translated into an electronic current by Ag/AgCl electrodes in the microfluidic device. The CMOS IC acquires the input current I

_{IN}and digitizes it into a 1-bit data stream. It uses a novel scheme for the transimpedance amplifier and a 2nd order ΔΣ modulator targeting 16-bit resolution for the A/D conversion. The analog-to-digital converter (ADC) output is filtered and decimated by a FIR filter implemented on a FPGA. Finally, PC communication is via a USB link.

_{off,ele}in Figure 3) [13]. This offset cancellation is done at the beginning of each experiment as follow:

- Read the front-end output voltage V
_{OUT}; - Compare V
_{OUT}with the reference voltage V_{CM}; - Change DC voltage V
_{OFF}so that it becomes equal to V_{CM}+ V_{off,ele}. (Note reference electrode is tight to V_{CM}).

_{C}applied to the LNA positive input is given by V

_{C}= V

_{STIM}+ V

_{OFF}so that V

_{OFF}counteracts the electrode offset, while V

_{STIM}appears as the voltage drop across bilayer membrane. The system is fully programmable via SPI. Two input ranges are implemented (±20 nA and ±200 pA) with maximum acquisition bandwidths of 100 kHz.

#### 2.2. Microfluidic Device

#### 2.3. Sensing Frontend Rationale

_{IN}, and a Sallen-Key low-pass filter. Integrator, voltage amplifier and differentiator are periodically reset to avoid saturation, while the Sallen-Key filter holds the output voltage v

_{OUT}during reset.

- Active phase. During this phase ${v}_{OUT}\left(t\right)={R}_{eq}\cdot {i}_{IN}\left(t\right)$ where R
_{eq}is the equivalent trans-resistance of the amplifier, which is given by:$${R}_{eq}=\frac{{C}_{2}{C}_{4}}{{C}_{1}{C}_{3}}{R}_{4}$$ - Reset phase. During this phase the output voltage is kept constant while the rest of the circuit reset.

_{S}is unrelated to the reset frequency f

_{R}= 1/T

_{R}; specifically f

_{S}is greater than f

_{R}. In this way the acquisition bandwidth is not limited by the periodic reset but the noise becomes cyclostationary. Detailed analysis of the effects of cyclostationary properties of noise is discussed in Section 2.7.

_{S}is the capacitance of the microfluidic setup with the BLM, and C

_{P}is the parasitic capacitances due to interconnects and input stage of the transimpedance amplifier. The combination of Equations (1) and (2) sets a trade-off on the value of the feedback capacitance C

_{1}that should be small enough to maximize R

_{eq}and minimize input noise (see Section 2.7), but large enough to speed up the integrator. C

_{1}was set to 1 pF, where GBW = 92 MHz, C

_{P}is of the order of a few pF, and C

_{S}is expected to be in the range 40–80 pF [12]. With these parameters, a 1 MHz bandwidth of the integrator is obtained. This value is ten times higher than acquisition bandwidth of the entire system and ensures a fast settling of the integrator after reset. Note that now the acquisition bandwidth is not limited by periodical reset but only by bandwidth of the OTA and parasitic capacitances as reported in Equation (2). The reduction of trans-resistance R

_{eq}due to the chosen value for C

_{1}is compensated by the gain of the voltage amplifier stage placed between integrator and differentiator.

_{R}and period T

_{R}, affect both the signal and noise. During the reset phase, the output voltage is disconnected from the input, hence the system does not see what the input current actually is, which leads to loss of information. As a result, τ

_{R}must be minimized while T

_{R}must be maximized. The same conclusion comes from noise analysis (see Section 2.7). Note that the reset period T

_{R}has an upper limit given by saturation of the first two OTAs. Assuming a maximum 200 pA DC input current (∆I

_{IN}) flowing through the input, then the system saturates after a time T

_{SAT}given by:

_{O1}is the maximum allowed voltage swing at the integrator output, which is equal to:

_{O2}= ∆V

_{OUT}since at low frequency the gain is set by the first two stages. Therefore the reset period T should be:

_{R}is linked to the time constant C

_{4}R

_{4}; thus C

_{4}and R

_{4}must be maximized. Once C

_{1}, C

_{4}and R

_{4}are chosen, the ratio C

_{2}/C

_{3}is given by the combination of Equations (5) and (6). The resistor R

_{3}, and capacitor C

_{4}, creates a first-order low-pass filter, reducing the noise before differentiation.

_{OUT}is fixed at ±450 mV by the OTA, thus R

_{eq}= 2.25 GΩ for ∆I

_{IN}= ±200 pA and R

_{eq}= 22.5 MΩ for ∆I

_{IN}= ±20 nA.

#### 2.4. ADC

_{REF+}= 2.1 V and V

_{REF−}= 1.2 V. Timing signals, ph1 and ph2, are two non-overlapping 10 MHz signals generated from an external 80 MHz clock. The use of a second-order ΔΣ converter allows keeping the quantization noise below the thermal noise of the input front-end thanks to ΔΣ noise shaping. The output of the ADC is a 10 MHz 1-bit data stream that is filtered and downsampled by a FIR digital filter implemented in the FPGA.

#### 2.5. Stimulus Generation and Offset Compensation

_{OUT}with the reference voltage V

_{CM}, which is the bias voltage of the reference electrode, and generates a DC voltage V

_{OFF}that is applied to the positive input of the integrator:

_{S}is the equivalent resistance of the ion channel. Under the assumption R

_{eq}>> R

_{S}then the offset current is almost nulled, while a small offset current still remains in case of higher value of R

_{S}. Note that offset of the LNA is compensated along with offset of the electrodes. The compensation loop is realized by means of a comparator, a latch and an 8-bit up/down counter working at 150 Hz (Figure 8).

_{STIM}is needed when working with voltage gated ion channels or for full characterization of ion channels. The signal v

_{STIM}is digitally generated by the FPGA and then sent to the CMOS amplifier through SPI interface, as shown in Figure 8. Both offset compensation and stimulus generation are addressed in the digital domain. Voltages v

_{STIM}and V

_{OFF}are added together and converted in analog domain by a 10-bit DAC to create the voltage v

_{C}that is applied to the positive input of the integrator (Figure 3):

_{STIM}and V

_{OFF}, limiting them to ±384 mV and ±128 mV, respectively. At the DAC output, a passive LPF filters out the high frequency noise. Extremely low noise acquisitions require an external capacitor of at least 1 nF. Note that a larger external capacitance reduces the noise as well as the bandwidth of the stimulus voltage. For instance, setting C

_{EXT}= 1 nF limits the bandwidth of v

_{STIM}to a few kHz.

#### 2.6. Subtractor

_{C}= v

_{STIM}+ V

_{OFF}is applied to the DUT by means of the virtual short circuit imposed by the negative feedback of the integrator. Hence the integrator behaves like a non-inverting amplifier from the v

_{C}standpoint, and the voltage v

_{01}can be written as:

_{C}signal directly propagates through the first stage as an unwanted additive component to the measured input signal. To avoid this effect, the subtractor stage multiplies v

_{C}by −1 and adds its output to integrator output (Figure 5). Obviously this stage adds noise but it is not needed for electrophysiology experiments requiring constant v

_{C}; hence, it is possible to activate or deactivate it using control signal Sub.

#### 2.7. Noise Analysis

- all the stages prior to the sampling are treated as linear time-invariant systems;
- node x takes into account low-pass filtering done by the Sallen-Key but not the sampling; there is not a direct correspondence of node x in the schematic diagram (Figure 5b).
- node OUT is renamed into y to get more compact equations.

_{IN}= C

_{S}+ C

_{P}, e

_{n}is the input-referred noise source of the OTA, f

_{p}is the dominant pole of the system that is set by the LPF, and noises generated by voltage amplifier and differentiator have been neglected. Note that G

_{x}(f) has not a white shape but it rises with f where Flicker dominates, and with f

^{2}where thermal noise dominates (Figure 9a). Simplifying G

_{x}(f) to a triangular shape the autocorrelation function of x(t) becomes:

_{x}(f). The voltage at node y can be seen as ${v}_{y}\left(t\right)={y}^{\prime}\left(t\right)+{y}^{\prime \prime}\left(t\right)$:

_{y′y″}is the cross-correlation function and T

_{R}is the reset period.

_{R}is the pulse duration of F3. Note that periodicity of y′ leads to folding of the noise PSD. However the sinc function is around zero for all n ≠ 0 since τ

_{R}<< T

_{R}; hence Equation (14) can be simplified to:

_{R}tends to zero (i.e., pure CT behavior) while the whole term in Equation (14) goes to zero when τ

_{R}tends to T

_{R}(i.e., pure DT behavior).

_{xx}(τ) has the form expressed in Equation (11), then R

_{xx}(τ

_{R}) is around zero for τ

_{R}> 1/f

_{p}. In our case τ

_{R}= 4.8 μs and f

_{p}is around 710 kHz, hence we neglect the cross-correlation term in Equation (13). If 1/f

_{p}> τ

_{R}this simplification is not valid any longer and Equation (17) should be considered.

_{x}(f) has not a standard white shape. Finally the input-referred noise is given by:

_{P}T

_{R}. Matlab analysis reveals that folding noise dominates the first term in Equation (19), although it is multiplied by a pre-factor (τ

_{R}/T

_{R})

^{2}that is much less than 1. Note that this pre-factor is near 1 in pure-DT approaches.

- -
- The most direct method of reducing folding noise is lowering the USR, which defines how many times the noise folds back into the baseband. This can be easily done by lowering f
_{p}, but this directly affects the bandwidth of the system and the sampling error [14]. Moreover, if 1/f_{p}becomes greater than the reset pulse duration τ_{R}then Equations (18) and (19) are no longer valid, since cross-correlation power computed from Equation (17) must be taken into consideration. - -
- Another important parameter is the period T
_{R}, which appears in both USR and pre-factor. It should be small to lower USR while it should be big to lower the pre-factor (τ_{R}/T_{R})^{2}. Since T_{R}is squared in the pre-factor term then it is better to make it as high as possible. This relation between noise and parameter T_{R}is confirmed by periodic-steady-state noise (pss-noise) analysis and it is predicted by our mathematical model, see Figure 10. - -
- Another way of reducing the folding noise is to keep G
_{x}(f) as low as possible. This directly translates into using a low-noise OTA and lowering the input capacitance C_{IN}as well as the feedback capacitance C_{1}, creating a noise-bandwidth trade-off.

## 3. Experimental Results

#### 3.1. Implementation

^{2}. The two-core design was dictated by the need to implement a prototype compact parallel recording platform, with 12 channels acquired concurrently [13]. A single core consumes a total of 41 mW. This power consumption includes all the circuits implemented in the CMOS chip, i.e., analog frontend, ADC, DAC, voltage references, clock buffering and digital circuits. The system can acquire signals up to 100 kHz at the highest resolution.

#### 3.2. Noise Measurements

_{eq}. Figure 12a shows the open-input input-referred noise measured at both the 200 pA and 20 nA input ranges with deactivated subtractor stage. The system has an input noise as low as 4 fA/√Hz in the 7.5 kHz bandwidth, and 6 fA/√Hz in the 175 kHz bandwidth, proving the low-noise capability and the wide acquisition bandwidth. Noise PSDs are flat at low frequencies since folding noise dominates, as discussed in Section 2.7, while they rise at high frequencies where the CT term dominates, as usual in transimpedance amplifiers [14].

_{P}T. The parameters are the followings: f

_{p}= 710 kHz, T

_{R}= 102.4 μs, τ

_{R}= 4.8 μs, C

_{1}= 1 pF, R

_{eq}= 2.25 GΩ, e

_{n}= 3 nV/√Hz. Noise simulation was done using SpectreRF

^{®}, which takes into account noise folding and cyclostationary properties of the system. Note that C

_{IN}= C

_{P}= 3 pF was used in both mathematical model and simulations to count for stray capacitances facing to the input node, such as capacitive effects due to pad, bonding wires, pin, etc. This value was indirectly estimated from measurements and parasitic extraction.

_{IN}as seen in Equation (10) and demonstrated by measurements shown in Figure 12c. This result confirms the need for small microfluidic device and integrated electronic readout placed as close as possible to the microfluidic chip. All the noise PSDs described above refer to measurements done in the optimum condition of deactivated OCL and constant voltage v

_{C}.

#### 3.3. Offset Compensation Loop and Subtractor

_{C}signal. Under this condition, a 400 pA (800 pApp) square wave current flows through the input node. The amplifier works at ±20 nA range and 7.5 kHz bandwidth. Figure 13b reports the estimated input current, computed referring the output of the FIR filter back to the input by means of the equivalent transresistance, when subtractor stage is either deactivated or activated. Following the analysis described in section II, the estimated input current is given by:

#### 3.4. Ion Channel Recording

#### 3.4.1. Gramicidin-A

#### 3.4.2. α-Haemolysin

#### 3.4.3. KcsA Potassium Channel

#### 3.5. State-of-the-Art Comparison

## 4. Conclusions

_{S}> f

_{R}disregarding the reset behavior. In this way the circuit achieves wide acquisition bandwidth and low noise performance even at low frequencies. The final result is a current-to-digital converter meeting all the applications requirements: (i) noise floor less than 10 fA/√Hz (i.e., 400 fA

_{rms}at 10 kHz and 1.9 pA

_{rms}at 100 kHz, both measured at ±200 pA range); (ii) 100 kHz bandwidth; (iii) transimpedance of 2.25 GΩ; (iv) power consumption of 41 mW per channel including the ADC. The proposed architecture is one of the faster transimpedance amplifiers in the literature and it offers state-of-the-art noise performance.

## Acknowledgments

## Author Contributions

## Conflicts of Interest

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**Figure 1.**(

**A**) Diagram showing the patch clamp technique where a glass pipette is used to pull a patch of cell membrane. A low-noise transimpedance amplifier measures channel currents; (

**B**) the planar bilayer membrane (BLM) technique where a suspended lipid bilayer contains an ion-channel. Again the current is read by a low-noise transimpedance amplifier. The picture also shows the electrical equivalent model of the BLM, consisting of a high value resistor (of the order of GΩ or greater) in parallel with a capacitance C

_{S}.

**Figure 2.**(

**a**) Photograph of the 12-channel parallel recording platform highlighting each element: three small PCBs with two CMOS current-to-digital amplifiers described in this paper, three 4-channel microfluidic devices [12], and a PCB with FPGA and USB interface which is housed in the metal box; (

**b**) Photograph of the platform showing board connections; (

**c**) Photograph of the final platform with the metal box used for shielding.

**Figure 3.**Block diagram of the system. A lipid bilayer is formed in a microfluidic chip, with integrated Ag/AgCl electrodes. Reference Electrode (RE) is tight to V

_{CM}while working electrode (WE) is connected to the input of the transimpedance amplifier. The CMOS transimpedance amplifier acquires the input current i

_{IN}and digitizes it into a 1-bit high-frequency delta-sigma modulated stream. It also compensates for electrode and opamp offset by means of a digital compensation loop that is activated at the beginning of every experiment. The ADC output is filtered and decimated by a digital FIR filter implemented on a FPGA. Data communication with PC is via a USB link. Virtual short circuit realized by the input LNA is used to apply a stimulus voltage v

_{STIM}to the BLM.

**Figure 4.**(

**a**) Diagram showing the microfluidic device. The counter electrode sets the potential of the top fluid chamber, which is common to every BLM. There are four separate microcavities each with individual bilayers and separate integrated Ag/AgCl electrodes; (

**b**) A photograph of the microfluidic device.

**Figure 5.**(

**a**) Block scheme of the proposed frontend. The signal direct path is composed of integrator, voltage amplifier, differentiator and active LPF; (

**b**) Full schematic diagram of the frontend, where a subtractor has been added to eliminate derivative component of stimulus signal from the final output. This subtractor stage can be activated/deactivated using the control signal Sub; (

**c**) Timing behavior of signals F1, F2 and F3.

**Figure 6.**Timing behavior of the system. The frontend resets every period T

_{R}= 102.4 μs. During the reset, the output voltage is held at a constant value. AD sampling frequency is n-times higher than the reset frequency.

**Figure 8.**Architecture of the offset compensation loop. The offset compensation voltage V

_{OFF}is generated comparing the output of the frontend v

_{OUT}with V

_{CM}and then incrementing a 8-bit counter. Stimulus signal v

_{STIM}comes from the FPGA and is summed to V

_{OFF}and fed to a DAC so as to create voltage v

_{C}A passive LPF filter at DAC output limits the noise.

**Figure 9.**(

**a**) Simplified block scheme of the proposed architecture. Noise analysis is based on this system simplification where sampling is decoupled from the Sallen-Key filter; (

**b**) Qualitative sketch of the noise PSD at node x; (

**c**) Qualitative sketch of noise autocorrelation function at node x.

**Figure 10.**Effect the reset period T on the input-referred r.m.s. noise. Comparison of the proposed mathematical model with SpectreRF

^{®}pss-noise analysis.

**Figure 12.**(

**a**) Open-input input-referred noise measured at two different ranges (20 nA and 200 pA). The noise is as low as 4 fA/√Hz in the best condition (i.e., range = 200 pA and digital filtering at 10 kHz with a sinc

^{3}LPF), while raises to 6 fA/√Hz at 200 pA range and digital filtering at 200 kHz. The highest noise floor, that is 40 fA/√Hz, is shown in the wider 20 nA range. Digital FIR filters with triangular windowing and 150 taps were used; (

**b**) Short-time trace recorded at bandwidth = 175 kHz showing periodic spikes every T

_{R}= 102.4 μs. This spikes are linked to the period reset activity; (

**c**) Relation between input-referred r.m.s. noise at 10 kHz and input capacitance C

_{in}, which takes into care microfluidic device together with BLM. Measured values are compared with simulations and theoretical estimation, validating Equation (19).

**Figure 13.**(

**a**) Functionality of the OCL. An offset in the nA range usually exists at the beginning of the experiment. The OCL changes the DC component of the applied stimulus v

_{C}until a zero current is recorded (i.e., V

_{OUT}= V

_{CM}); (

**b**) Functionality of the subtractor. A 10 pF capacitor is connected to the input while a 100 mVpp triangular wave at 200 Hz is applied as v

_{C}signal leading to a 800 pApp current square wave flowing through the input. The input current is overestimated when the subtractor is turned-off; (

**c**) Effect of the OCL on the input-referred noise. When the OCL is activated and a stimulus signal v

_{STIM}is applied, the noise rises from 4 fA/√Hz to 6 fA/√Hz due to noise sources in the OCL. Note that v

_{C}is filtered with an external 10 nF capacitance.

**Figure 14.**(

**a**) Data from gramicidin-A channels. Applied potential = 100 mV and the acquisition has been performed at 625 Hz; (

**b**) Current trace showing the insertion of two α-HL nanopores. Experiments performed with 2.5 μg/ml of α-HL protein in 1 M of KCl solution. Acquisition performed at 200 pA range with post-processing filtering at 1.25 kHz; (

**c**) KcsA recording at 125 mV with data filtered at 5 kHz and (

**d**) 10 kHz. The buffer was 150 mM KCl, pH 4.0.

**Figure 15.**Input-referred noise compared with benchmark instrument for biological current acquisition. The peaks shown in all the lines are due to spurious coupling from the 50 Hz powerline.

Component | C_{1} | C_{2} | C_{3} | C_{4} | R_{4} | R_{3} | T_{R} | τ_{R} |
---|---|---|---|---|---|---|---|---|

Value | 1 pF | 22 pF | 1 pF | 102.4 pF | 1 MΩ | 2.2 kΩ | 102.4 μs | 4.8 μs |

Theory (18) | Simulation | Measure | |
---|---|---|---|

RMS NOISE at 10 kHz | 380 fA | 400 fA | 420 fA |

Conditions | C_{IN} = C_{P} = 3 pF | C_{IN} = C_{P} = 3 pF | Open-input |

Paper | Noise floor @ Room Temperature | Embedded ADC | Analog Power Consumption | Digital Power Consumption | Input Capacitance for Characterization of Noise Floor | Operating Bandwidth [kHz] | Gain [GΩ] | Technology Node |
---|---|---|---|---|---|---|---|---|

[21] | 12 fA/√Hz | NO | - | - | - | 10.000 | <1 | CMOS 0.13 μm |

[20] | 2 fA/√Hz | NO | 3 μW | - | - | 6 | >1 | CMOS 0.13 μm |

[37] | 0.5 fA/√Hz | NO | - | - | 1 pF | 1000 | *^{1} | - |

[39] | 6 fA/√Hz | NO | 1.5 mW | - | 7 pF | 50 | - | CMOS 0.5 μm |

[38] | 4 fA/√Hz | NO | 45 mW | - | 800 fF | 10,000 | 0.06 | CMOS 0.35 μm |

[40] | 11.6 fA/√Hz | NO | 5.22 mW | - | - | 1400 | 0.01 | CMOS 0.18 μm |

[13] | 3 fA/√[email protected] = 625 Hz 12 fA/√Hz @B = 10 kHz | YES | 20 mW | 20 mW | 3 pF | 10 | 2.25 | CMOS 0.35 μm |

This work | 4 fA/√Hz*^{2} @B = 7.5 kHz6 fA/√Hz * ^{2} @B = 175 kHz | YES | 21 mW | 20 mW | 3 pF | 100 | 2.25 | CMOS 0.35 μm |

^{1}The output of this amplifier is a current; *

^{2}Noise floor measured at ±200 pA range.

© 2016 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC-BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Crescentini, M.; Bennati, M.; Saha, S.C.; Ivica, J.; De Planque, M.; Morgan, H.; Tartagni, M. A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording. *Sensors* **2016**, *16*, 709.
https://doi.org/10.3390/s16050709

**AMA Style**

Crescentini M, Bennati M, Saha SC, Ivica J, De Planque M, Morgan H, Tartagni M. A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording. *Sensors*. 2016; 16(5):709.
https://doi.org/10.3390/s16050709

**Chicago/Turabian Style**

Crescentini, Marco, Marco Bennati, Shimul Chandra Saha, Josip Ivica, Maurits De Planque, Hywel Morgan, and Marco Tartagni. 2016. "A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording" *Sensors* 16, no. 5: 709.
https://doi.org/10.3390/s16050709