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Search Results (3)

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Keywords = vertical double–diffused MOSFET (VDMOS)

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13 pages, 2878 KiB  
Article
A Novel Low On–State Resistance Si/4H–SiC Heterojunction VDMOS with Electron Tunneling Layer Based on a Discussion of the Hetero–Transfer Mechanism
by Hang Chen, Yourun Zhang, Rong Zhou, Zhi Wang, Chao Lu, Zehong Li and Bo Zhang
Crystals 2023, 13(5), 778; https://doi.org/10.3390/cryst13050778 - 7 May 2023
Cited by 2 | Viewed by 2355
Abstract
In this study, we propose a novel silicon (Si)/silicon carbide (4H–SiC) heterojunction vertical double–diffused MOSFET with an electron tunneling layer (ETL) (HT–VDMOS), which improves the specific on–state resistance (RON), and examine the hetero–transfer mechanism by simulation. In this structure, the high [...] Read more.
In this study, we propose a novel silicon (Si)/silicon carbide (4H–SiC) heterojunction vertical double–diffused MOSFET with an electron tunneling layer (ETL) (HT–VDMOS), which improves the specific on–state resistance (RON), and examine the hetero–transfer mechanism by simulation. In this structure, the high channel mobility and high breakdown voltage (BV) are obtained simultaneously with the Si channel and the SiC drift region. The heavy doping ETL on the 4H–SiC side of the heterointerface leads to a low heterointerface resistance (RH), while the RH in H–VDMOS is extremely high due to the high heterointerface barrier. The higher carrier concentration of the 4H–SiC surface can significantly reduce the width of the heterointerface barrier, which is demonstrated by the comparison of the conductor energy bands of the proposed HT–VDMOS and the general Si/SiC heterojunction VDMOS (H–VDMOS), and the electron tunneling effect is significantly enhanced, leading to a higher tunneling current. As a result, a significantly improved trade–off between RON and BV is achieved. With similar BV values (approximately 1525 V), the RON of the HT–VDMOS is 88% and 65.75% lower than that of H–VDMOS and the conventional SiC VDMOS, respectively. Full article
(This article belongs to the Special Issue Nano-Semiconductors: Devices and Technology)
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10 pages, 7054 KiB  
Article
Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure
by Yuan Wang, Tao Liu, Lingli Qian, Hao Wu, Yiren Yu, Jingyu Tao, Zijun Cheng and Shengdong Hu
Micromachines 2023, 14(3), 688; https://doi.org/10.3390/mi14030688 - 20 Mar 2023
Cited by 4 | Viewed by 2349
Abstract
Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region [...] Read more.
Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region has been damaged. The SEGR-hardened termination with multiple implantation regions is proposed and simulated using the Sentaurus TCAD. The multiple implantation regions are introduced, leading to an increase in the distance between the gate oxide and the hole accumulation region, as well as a decrease in the resistivity of the hole conductive path. This approach is effective in reducing the electric field of the gate oxide to below the calculated critical field, and results in a lower electric field than the conventional termination. Full article
(This article belongs to the Special Issue Power Semiconductor Devices and Applications)
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13 pages, 2340 KiB  
Article
Study of the Within-Batch TID Response Variability on Silicon-Based VDMOS Devices
by Xiao Li, Jiangwei Cui, Qiwen Zheng, Pengwei Li, Xu Cui, Yudong Li and Qi Guo
Electronics 2023, 12(6), 1403; https://doi.org/10.3390/electronics12061403 - 15 Mar 2023
Cited by 8 | Viewed by 1833
Abstract
Silicon-based vertical double-diffused MOSFET (VDMOS) devices are important components of the power system of spacecraft. However, VDMOS is sensitive to the total ionizing dose (TID) effect and may have TID response variability. The within-batch TID response variability on silicon-based VDMOS devices is studied [...] Read more.
Silicon-based vertical double-diffused MOSFET (VDMOS) devices are important components of the power system of spacecraft. However, VDMOS is sensitive to the total ionizing dose (TID) effect and may have TID response variability. The within-batch TID response variability on silicon-based VDMOS devices is studied by the 60Co gamma-ray irradiation experiment in this paper. The variations in device parameters after irradiation is obtained, and the damage mechanism is revealed. Experimental results show that the standard deviations of threshold voltage, subthreshold swing, output capacitance, and diode forward voltage increase, while the standard deviation of maximum transconductance decreases after irradiation. The standard deviation of on-state resistance is basically unchanged before and after irradiation. By separating the trapped charges generated by TID irradiation, it is found that the deviation of the oxide trapped charges and the interface traps increase with the increase in the total dose. The reasons for the variation in device parameters after irradiation are revealed by establishing the relationship between the trapped charges and the electrical parameters before and after irradiation. Full article
(This article belongs to the Special Issue Radiation Effects of Advanced Electronic Devices and Circuits)
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