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Keywords = timing-error prevention (TEP)

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12 pages, 829 KB  
Article
A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention
by Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Jani Mäkipää, Arto Rantala, Matti Sopanen and Mikko Kaltiokallio
J. Low Power Electron. Appl. 2015, 5(2), 57-68; https://doi.org/10.3390/jlpea5020057 - 17 Apr 2015
Viewed by 9013
Abstract
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two [...] Read more.
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. Full article
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
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