Search Results (1,106)

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor (SC) balancer, specifically designed for a 4-cell series-connected battery pack. This work also explored open circuit voltage (OCV)-driven adaptive pulse-frequency modulation (PFM) active balancing to achieve higher efficiency and better balancing speed based on different system requirements. Finally, this paper compares passive, active (SC-based), and adaptive duty-cycled hybrid balancing strategies in detail, including theoretical modeling of energy transfer and efficiency for each method. Simulation showed that the adaptive hybrid balancer speeds state-of-charge (SoC) equalization by 16.24% compared to active-only balancing while maintaining an efficiency of 97.71% with minimal thermal stress. The simulation result also showed that adaptive active balancing was able to achieve a high efficiency of 99.86% and provided an additional design degree of freedom for different applications. The results indicate that the adaptive hybrid balancer offered an excellent trade-off between balancing speed, efficiency, and implementation simplicity for 4-cell Li-ion packs, making it highly suitable for applications such as high-voltage portable chargers. Full article

This paper presents two classic analog oscillators: a relaxation oscillator and a Wien bridge one, where a memristor replaces a resistor. The circuits are simulated in TopSPICE 7.12 using a memristor emulation circuit and commercially available components to evaluate the memristor’s impact. In the case of the relaxation oscillator, which includes the memristor, a notable increase in oscillation frequency was observed compared to the classical circuit, with a nearly 10-fold increase from 790 Hz to 7.78 kHz while maintaining a constant amplitude. This confirms the influence of the memristor’s dynamic resistance on the circuit time constant. On the other hand, the Wien-bridge oscillator exhibits variations in specific parameters, such as peak voltage, amplitude, and frequency. In this case, the oscillation frequency decreased from 405 Hz to 146 Hz with the addition of the memristor, a characteristic introduced by the proposed memristive element’s nonlinear interactions. Experimental results confirm the feasibility of incorporating memristors into classical oscillator circuits, enabling frequency changes while maintaining stable oscillations, allowing reconfigurable and adaptable analog designs that leverage the properties of memristive devices. Full article

NO₂ is a toxic gas mainly generated by combustion processes, such as vehicle emissions and industrial activities. It is a key contributor to smog, acid rain, ground-level ozone, and particulate matter, all of which pose serious risks to human health and the environment. Conventional resistive gas sensors, typically based on metal oxide semiconductors, detect NO₂ by resistance modulation through surface interactions with the gas. However, they often suffer from low responsiveness and poor selectivity. This study investigates NO₂ detection using nanoporous zinc oxide thin films integrated into a resistor structure and floating-gate field-effect transistor (FGFET). Both Silvaco-Atlas simulations and experimental fabrication were employed to evaluate sensor behavior under NO₂ exposure. The results show that FGFET provides higher sensitivity, faster response times, and improved selectivity compared to resistor-based devices. In particular, FGFET achieves a detection limit as low as 89 ppb, with optimal performance around 400 °C, and maintains stability under varying humidity levels. The enhanced performance arises from quantum well effects at the floating-gate Schottky contact, combined with NO₂ adsorption on the ZnO surface. These interactions extend the depletion region and confine charge carriers, amplifying conductivity modulation in the channel. Overall, the findings demonstrate that FGFET is a promising platform for NO₂ sensors, with strong potential for environmental monitoring and industrial safety applications. Full article

This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and the isolation provided by resistors within the power divider, the interference between the transmitter (TX) and receiver (RX) is effectively suppressed. Additionally, thanks to the dual-amplifier architecture, no extra power amplification circuitry is required, thereby reducing the overall complexity and power consumption of the communication system. The detailed design procedure of the proposed quasi-circulator is presented. The measurement results show that, within the frequency range of 4.75 GHz to 6.11 GHz, the isolation between the TX and RX ports exceeds 20 dB, the return loss at each port is greater than 10 dB, and the transmission gains from the TX port to the antenna and from the antenna to the RX port are 3.1–8.7 dB and 2.7–4.0 dB, respectively, demonstrating a relative bandwidth of 25%. Full article

To further investigate the collision process and tectonic regime transition between the North China (NCB) and South China Block (SCB), two magnetotelluric profiles were arranged across the Dabie Orogeny Belt (DOB) and eastern SCB. We then obtain the lithospheric resistivity models. The prominent feature revealed by our new model is an extensive conductive arc from the lower crust to the upper mantle, across the Jiangnan orogenic belt (JNOB) and the eastern Cathaysia Block (CAB). In addition, a huge resistor beneath the conductive arc is revealed, which is separated by a conductive wedge. Combining the heat flow and seismic tomographic imaging results, the conductors are to contain a large amount of hot material that present as the detachment layers (belts) controlled by the two subduction slabs. Considering multi-phase magmatism in the study area, new models suggest an intracontinental tectonic event in eastern CAB. Therefore, we propose a reliable tectonic process that occurred in the study area, including five stages: (1) an eastward intracontinental subduction and orogen carried out in CAB before the collision between SCB and NCB; (2) an extensional structural developed in CAB, following the subduction slab wrecking/sinking; (3) after the collision with NCB, the SCB crust/lithosphere thickened following the westward subduction of the Paleo-Pacific plate; (4) following the westward Yangtze slab sinking, the regional extension developed with the asthenosphere upwelling beneath SCB; (5) afterwards, the SCB was welded into one continent in a setting of westward compression. Full article

The automation of concrete constructions through 3D printing (3DP) has been increasingly developed and adopted in civil engineering due to its promising advantages over traditional construction methods. However, widespread implementation is hindered by uncertainties in quality control, homogeneity, and interlayer bonding, as well as the uniqueness of each printed component. Building upon our prior work in developing 3D-printable self-sensing cementitious materials by incorporating graphite powder and carbon microfibers into a cementitious matrix to enhance its piezoresistive properties, this study aims at enabling condition assessment of cementitious 3DP by integrating the self-sensing materials as sensing nodes within conventional components. Three different 3D-printed strip patterns, consisting of one, two, and three strip lines that mimic the pattern used in fabricating foil strain gauges were investigated as conductive electrode designs to impart strain sensing capabilities, and characterized from a series of quasi-static and dynamic tests. Results demonstrate that the three-strip design yielded the highest sensitivity (${\lambda }_{\mathrm{stat}}$ of 669, ${\lambda }_{\mathrm{dyn}}$ of 630), whereas the two-strip design produced the highest signal quality (SNR_stat = 9.5 dB, SNR_dyn = 10.8 dB). These findings confirm the feasibility of integrating 3D-printed self-sensing cementitious materials through hybrid manufacturing, enabling monitoring of print quality, detection of load path changes, and identification of potential defects. Full article

A precision bandgap reference (BGR) is an essential building block in modern analog and mixed-signal systems, as it provides stable and predictable current and voltage references required for reliable operation across process, voltage, and temperature variations. However, one of the key challenges in conventional BGR circuits is their sensitivity to resistance variations, which directly impacts the accuracy of bias currents. Even small changes in resistance can lead to significant current mismatch between the core branches of the circuit, thereby degrading output stability and limiting the precision of the overall system. This degradation is particularly problematic in high-performance applications such as data converters, oscillators, and low-power biasing networks, where robust current matching is critical. To address this limitation, this work proposes a resistance-compensated BGR architecture that incorporates an auxiliary trimming network and a compensation branch. The trimming network senses variations in resistance and generates a control bias proportional to the deviation, while the compensation branch injects a corrective current into the output stage. By dynamically balancing the mismatch introduced by resistor spread, the proposed architecture effectively restores current stability across process corners. This method achieves reduction in the current variation across resistance corners from 21% to 3% in worst-case corners (±3%). This approach offers enhancement of current mismatches in analog systems in which robust current is essential. Full article

A bias-free antenna tuning technique that eliminates conventional DC biasing networks is presented. The tuning mechanism is based on a Light-Dependent Resistor (LDR) embedded within the antenna structure. Optical illumination is used to modulate the LDR’s resistance, thereby altering the antenna’s effective electrical length and enabling tuning of its resonant frequency and operating bands. By removing the need for bias lines, RF chokes, blocking capacitors, and control circuitry, the proposed approach minimizes parasitic effects, losses, biasing energy, and routing complexity. This makes it particularly suitable for compact and energy-constrained platforms, such as Internet of Things (IoT) devices. As proof of concept, an LDR is integrated into a ring monopole antenna, achieving tri-band operation in both high and low resistance states. In the high-resistance (OFF) state, the fabricated prototype operates across 2.1–3.1 GHz, 3.5–4 GHz, and 5–7 GHz. In the low-resistance (ON) state, the LDR bridges the two arcs of the monopole, extending the current path and shifting the lowest band to 1.36–2.35 GHz, with only minor changes to the mid and upper bands. The antenna maintains linear polarization across all bands and switching states, with measured gains reaching up to 5.3 dBi. Owing to its compact, bias-free, and low-cost architecture, the proposed design is well-suited for integration into portable wireless devices, low-power IoT nodes, and rapidly deployable communications systems where electrical biasing is impractical. Full article

This paper presents a new compact and efficient first-order all-pass filter in voltage mode based on a second-generation voltage conveyor, along with two resistors, and a capacitor. This circuit delivers an all-pass response from the low-impedance node and eliminates the need for a voltage buffer in cascading configurations. A thorough non-ideal analysis, accounting for parasitic impedances and the non-ideal gains of the active module, shows negligible effects on the filter performance. Furthermore, a sensitivity analysis with respect to both active and passive components further validates the robustness of the design. The proposed all-pass filter is validated by Cadence PSPICE simulations, utilizing 0.18 µm TSMC CMOS process parameter and ±0.9 V power supply, including Monte Carlo analysis and temperature variations. Additionally, experimental validation is carried out using commercially available IC AD844, showing great consistency between theoretical and experimental results. Resistor-less realization of the proposed filter provides tunability feature. A quadrature sinusoidal oscillator is presented to validate the proposed structure. The introduced circuit provides a simple and effective solution for low-power and compact analog signal processing applications. Full article

This paper offers a comprehensive methodology for the synthesis and analysis of active filters, including low-pass, high-pass, and band-pass configurations, utilizing operational amplifiers and multi-loop negative feedback systems. The approach involves deriving explicit analytical expressions for the design and optimization of eight distinct filter circuit solutions: one low-pass, one high-pass, and six band-pass filters with varying specifications. These derivations include the calculation of normalized and denormalized component values (resistors and capacitors), enabling precise tuning and practical implementation of the filters. Furthermore, the methodology encompasses the determination of key filter parameters such as passband gain, pole quality factor (Q-factor), and cut-off/center frequency, after selecting standard resistor and capacitor values suitable for the target application. The analytical framework facilitates a systematic approach to filter design, ensuring that the resulting circuits meet specific frequency response criteria while maintaining optimal stability and performance. The proposed methodology can be effectively applied in the development of various active filtering systems for signal processing, communication, and instrumentation, offering engineers a reliable foundation for designing high-performance, tailored filter solutions. Full article

Closing resistors in ultra-high-voltage (UHV) gas-insulated circuit breakers (GCBs) are critical components designed to suppress inrush currents and transient overvoltages during switching operations. However, in practical service, these resistors are subjected to repeated mechanical impacts and transient electrical stresses, leading to degradation of their electrical contact interfaces, fluctuating resistance values, and potential failure of the entire breaker assembly. Existing studies mostly simplify the closing resistor as a constant resistance element, neglecting the coupled electro-thermal–mechanical effects that occur during transient events. In this work, a comprehensive modeling framework is developed to investigate the dynamic electrical contact characteristics of a 750 kV GCB closing resistor under transient closing impacts. First, an electromagnetic transient model is built to calculate the combined inrush and power-frequency currents flowing through the resistor during its pre-insertion period. A full-scale mechanical test platform is then used to capture acceleration signals representing the mechanical shock imparted to the resistor stack. These measured signals are fed into a finite element model incorporating the Cooper–Mikic–Yovanovich (CMY) electrical contact correlation to simulate stress evolution, current density distribution, and temperature rise at the resistor interface. The simulation reveals pronounced skin effect and current crowding at resistor edges, leading to localized heating, while transient mechanical impacts cause contact pressure to fluctuate dynamically—resulting in a temporary decrease and subsequent recovery of contact resistance. These findings provide insight into the real-time behavior of closing resistors under operational conditions and offer a theoretical basis for design optimization and lifetime assessment of UHV GCBs. Full article

Raman thermometry is a powerful technique for sub-microscale thermal measurements on semiconductor-based devices, provided that the active region remains accessible and is not obscured by metallization. Since pure metals do not exhibit Raman scattering, traditional Raman thermometry becomes ineffective in such cases. To overcome this limitation, we propose the use of atomically thin Two-Dimensional materials as local temperature sensors. These materials generate Raman spectra at the nanoscale, enabling highly precise absolute surface temperature measurements. In this study, we investigate the feasibility and effectiveness of this approach by applying it to power devices, including a calibrated gold resistor and an SiC Junction Barrier Schottky (JBS) diode. We assess the processing challenges and measurement reliability of 2D materials for thermal characterization. To validate our findings, we complement Raman thermometry with thermoreflectance measurements, which are well suited for metallized surfaces. For example, on the serpentine resistor, Raman thermometry applied to the 2D material yielded a thermal resistance of 22.099 °C/W, while thermoreflectance on the metallic surface measured 21.898 °C/W. This close agreement suggests good thermal conductance at the metal/2D material interface. The results demonstrate the potential of integrating 2D materials as effective nanoscale temperature probes, offering new insights into thermal management strategies for advanced electronic components. Additionally, thermal simulations are conducted to further analyze the thermal response of these devices under operational conditions. Furthermore, we investigate two 2D material integration methods, transfer and direct growth, and evaluate them through measured thermal resistances for the SiC JBS diode, highlighting the influence of the deposition technique on thermal performance. Full article

This paper presents a novel technique for thermally compensating the power output of a DC-DC converter that supplies automotive lighting/signaling systems with multiple LED branches. The method ensures stable bias voltage for the current drivers controlling each branch, maintaining consistent power consumption across a wide temperature range. This issue has been minimally addressed in existing literature, providing few solutions which are too complex for industrial production. The approach proposed is simple and involves incorporating a temperature-sensitive thermistor into the DC-DC converter’s control loop, enabling the output voltage to adjust with ambient temperature. Different control loop configurations are explored, demonstrating that a simple resistor-thermistor network can approximate the desired voltage response under diverse thermal conditions. The power dissipated in the current drivers is kept within a controlled range, improving system efficiency and reducing heat loss. Additionally, it minimizes the need for additional current drivers, lowering the cost of these systems, improving battery life of the DC-DC converter, and decreasing CO₂ emissions. For the case studies analyzed, an optimized configuration with appropriate resistor values and thermistor models achieves a 75% relative reduction in power dissipation by the current driver and a 50% improvement in the relative efficiency of the LED branch system. Full article

This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure ($r_A,r_B$) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures. Full article

This paper presents a W-band high-efficiency and high-output-power power amplifier (PA) based on a 130 nm AlGaN/GaN-on-SiC HEMT process. The PA is designed to deliver optimal output power and gain performance across the entire W-band. A balanced architecture is adopted, combining two amplifier units through Lange couplers. High- and low-impedance microstrip lines are employed for input, output, and inter-stage matching. Each amplifier core adopts a three-stage configuration with gate width ratios of 1:2:4 to enhance gain. The bias network incorporates MIM capacitors and thin-film resistors to improve stability. Measured results indicate a small signal gain exceeding 17 dB under a gate voltage of −2.2 V and a drain voltage of +20 V. Within the 80–86 GHz frequency range, the PA achieves an output power above 34 dBm with a 22 dBm input power, corresponding to a power gain above 12 dB and a power-added efficiency (PAE) greater than 20%. The chip occupies a compact area of 2.65 mm × 3.75 mm. Compared with previously reported works, the proposed PA demonstrates the highest PAE within the 80–86 GHz band. Full article