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14 pages, 715 KiB

Open AccessArticle

High-Precision Digital-to-Time Converter with High Dynamic Range for 28 nm 7-Series Xilinx FPGA and SoC Devices

by Fabio Garzetti, Nicola Lusardi, Nicola Corna, Gabriele Fiumicelli, Federico Cattaneo, Gabriele Bonanno, Andrea Costa, Enrico Ronconi and Angelo Geraci

Electronics 2024, 13(23), 4825; https://doi.org/10.3390/electronics13234825 - 6 Dec 2024

Viewed by 1177

Abstract

Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise. Skew compensation and camera shutter operation represent just a few examples of such applications. The advantages of adopting a flexible and rapid time-to-market strategy focused on fast prototyping using programmable logic devices—such as field-programmable gate arrays (FPGAs) and system-on-chip (SoC)—have become increasingly evident. These benefits outweigh those of performance-focused yet expensive application-specific integrated circuits (ASICs). Despite the availability of various architectures, the high non-recurring engineering (NRE) costs make them unsuitable for low-volume production, especially in research or prototyping environments. To address this trend, we introduce an innovative DTC IP-Core with a resolution, also known as least significant bit (LSB), of 52 ps, compatible with all Xilinx 7-Series FPGAs and SoCs. Measurements have been performed on a low-end Artix-7 XC7A100TFTG256-2, guaranteeing a jitter lower than 50 ps r.m.s. and offering a high dynamic range up to 56 ms. With resource utilization below 1% and a dynamic power dissipation of 285 mW for our target FPGA, the design maintains excellent differential and integral nonlinearity errors (DNL/INL) of 1.19 LSB and 1.56 LSB, respectively. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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11 pages, 12391 KiB

Open AccessArticle

Phase Difference Measurement Method Based on Progressive Phase Shift

by Min Zhang, Hai Wang, Hongbo Qin, Wei Zhao and Yan Liu

Electronics 2018, 7(6), 86; https://doi.org/10.3390/electronics7060086 - 1 Jun 2018

Cited by 15 | Viewed by 7239

Abstract

This paper proposes a method for phase difference measurement based on the principle of progressive phase shift (PPS). A phase difference measurement system based on PPS and implemented in the FPGA chip is proposed and tested. In the realized system, a fully programmable delay line (PDL) is constructed, which provides accurate and stable delay, benefitting from the feed-back structure of the control module. The control module calibrates the delay according to process, voltage and temperature (PVT) variations. Furthermore, a modified method based on double PPS is incorporated to improve the resolution. The obtained resolution is 25 ps. Moreover, to improve the resolution, the proposed method is implemented on the 20 nm Xilinx Kintex Ultrascale platform, and test results indicate that the obtained measurement error and clock synchronization error is within the range of ±5 ps. Full article

(This article belongs to the Special Issue All-Digital Time-Mode Approaches for Mixed Analog-Digital Signal Processing)

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11 pages, 3937 KiB

Open AccessArticle

High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

by Hai Wang, Min Zhang and Yan Liu

Appl. Sci. 2017, 7(1), 52; https://doi.org/10.3390/app7010052 - 4 Jan 2017

Cited by 22 | Viewed by 8996

Abstract

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip. Full article

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