Search Results (5)

Analog design productivity remains a challenge in the digitally driven semiconductor chip design field. Knowledge-based and simulation-based analog automation approaches have not achieved widespread acceptance in the analog design community. Systematic analog design using precomputed lookup tables (LUTs) is a promising approach that can address the design productivity challenge. Although modern computing systems have powerful memory capabilities, which make the LUT approach viable, reducing the memory footprint of the LUTs remains a challenge. A memory-efficient design technique using LUTs is proposed by using an incomplete grid in the MOSFET degrees-of-freedom (DoFs) space. An efficient indexing technique for the incomplete grid is also proposed, using a precomputed offset array in various scenarios, such as two-sided constraints and three-dimensional LUTs. The results show that the proposed technique can achieve up to a 67% reduction in memory footprint, in addition to improving LUT generation time and query performance. Full article

Analog design is an inherently intricate process comprising many trade-offs; as a result, it is an iterative time-consuming operation. A low dropout voltage regulator (LDO) is an example of such analog blocks that involve a myriad of trade-offs. In this paper, we present an automated design procedure for LDOs using precomputed look-up tables (LUTs) and the $g_m/I_D$ methodology. Using a symbolic solver and the precomputed LUTs, a design database for an LDO that contains one million design points is generated in a few seconds. The database provides visualization of the design space and exploration of the trade-offs across different corners and load currents. A design example is provided to demonstrate the procedure using 40 nm technology and the results are verified using Cadence Spectre simulator. The approach is holistic in the sense that it uses an accurate symbolic solver to capture the small signal model complexities, incorporates LUTs for accurate calculation of the large signal solution and the small signal parameters, is fast because the simulator in the loop scenario is omitted, and almost all the specifications of LDOs are incorporated. Full article

In this paper, a machine learning-based approach for the automation of topology selection of integrated analog amplifier circuits is presented. A dataset of 480,000 circuits for 30 different amplifier topologies is generated for the prediction algorithm based on a precomputed lookup tables (LUTs) approach. A first approach based on neural networks is presented where the required specifications act as inputs to the networks, and the output of the network is the suitable topology for such a set of specifications. A modified cascaded neural network approach is examined to reduce the training time of the network while maintaining the prediction accuracy. Using the cascaded neural network approach, the network is trained in only one minute on a standard computer, and a 90.8% prediction accuracy is achieved. This allows on-the-fly changes in the input specifications, and consequently the neural network, to enable examining different design scenarios. Full article

Design optimization of RF low-noise amplifiers (LNAs) remains a time-consuming and complex process. Iterations are needed to adjust impedance matching, gain, and noise figure (NF) simultaneously. The process can involve more iterations to adjust the non-linear behavior of the circuit which can be represented by the input-referred third-order intercept (IIP3). In this work, we present a variation-aware automated design and optimization flow for a wide-band noise-canceling LNA. We include the circuit non-linearity in the optimization flow without using a simulator in the loop. By describing the transistors using precomputed lookup tables (LUTs), a design database that contains 200,000 design points is generated in 3 s only without non-linearity computation and 10 s when non-linearity is taken into account. Using a gm/ID-based correct-by-construction design procedure, the generated design points automatically satisfy proper biasing, input matching, and gain matching requirements. The generated database enables the designer to visualize the design space and explore the design trade-offs. Moreover, multi-objective optimization across corners for a given set of specifications is applied to find the Pareto-optimal fronts of the design figures-of-merit. We demonstrate the presented flow using two design examples in a 65 nm process and the results are verified using Cadence Spectre. Full article

Multiplication by a constant is a common operation for many signal, image, and video processing applications that are implemented in field-programmable gate arrays (FPGAs). Constant-coefficient multipliers (KCMs) are often implemented in the logic fabric using lookup tables (LUTs), reserving embedded hard multipliers for general-purpose multiplication. This paper describes a two-operand addition circuit from previous work and shows how it can be used to generate and add pre-computed partial products to implement KCMs. A novel method for pre-computing partial products for KCMs with a negative constant is also presented. These KCMs are then extended to have two to eight coefficients that may be selected by a control signal at runtime to implement time-multiplexed multiple-constant multiplication. Synthesis results show that proposed pipelined KCMs use 27.4% fewer LUTs on average and have a median LUT-delay product that is 12% lower than comparable LogiCORE IP KCMs. Proposed pipelined KCMs with two to eight selectable coefficients use 46% to 70% fewer LUTs than the best LogiCORE IP based alternative and most are faster than using a LogiCORE IP multiplier with a coefficient lookup function. They also outperform the state-of-the-art in the literature, using 22% to 57% fewer slices than the smallest pipelined adder graph (PAG) fusion designs and operate 7% to 30% faster than the fastest PAG fusion designs for the same operand size and number of selectable coefficients. For KCMs and KCMs with selectable coefficients of a given operand size, the placement and routing of LUTs remains the same for all positive and negative constant values, which is advantageous for runtime partial reconfiguration. Full article