Search Results (6)

The core–shell junctionless MOSFET (CS-JL FET) meets the process requirements of FD-SOI technology. The transistor body comprises a heavily doped ultrathin layer (core linking the source and the drain), located underneath an undoped layer (shell). Drain current, transconductance, and capacitance characteristics demonstrate striking performance improvement compared with conventional junctionless MOSFETs. The addition of the shell results in one order of magnitude higher mobility (peak value), transconductance, and drive current. The doping and thickness of the core can be engineered to achieve a positive threshold voltage for normally-off operation. The CS-JL FET is compatible with back-biasing and downscaling schemes. The physical mechanisms are revealed by emphasizing the roles of the main device parameters. Full article

Biologically sensitive field-effect transistors (BioFETs) have advanced the biosensing capabilities in various fields such as healthcare, security and environmental monitoring. Here, we propose a junctionless BioFET (JL-BioFET) for the high-sensitivity and low-cost detection of biomolecules and analyze it using detailed device simulations. In contrast to the conventional FET with junctions, the JL-BioFET simplifies fabrication by doping the source, channel and drain simultaneously with the same types of impurities, thereby reducing the fabrication effort and cost. Additionally, if the device is designed with optimal bias, it can operate with only the source and drain terminals, which reduces power consumption. Thus, cost reduction and reduced power consumption are strong motivations to pursue a new design. Therefore, we simulated two JL-BioFET structures (SOI JL, bulk JL) that operate without a gate electrode and compared their biosensing performances. The bulk JL-BioFET showed an average sensitivity three times higher than that of the SOI JL-BioFET across varying charge levels. Then, we optimized the sensing performance of the bulk JL-BioFET by adjusting three key parameters: the active layer thickness and the doping concentrations of the active layer and substrate. These encouraging results are expected to lead to future fabrication efforts to realize bulk JL-BioFETs for high-performance biosensing. Full article

In the ElectroMed project, we are interested in screening certain peptide sequences for their ability to selectively interact with antibodies or MHC proteins. This poses a combinatorial challenge that requires a highly multiplexed setup of label-free immunosensors. Label-free FET-based immunosensors are good candidates due to their high multiplexing capability and fast response time. Nanowire-based FET sensors have shown high sensitivity but are unreliable for clinical applications due to drift and gate stability issues. To address this, a label-free immuno-FET architecture based on planar junctionless FET devices is proposed. This geometry can improve the signal-to-noise ratio due to its larger planar structure, which is less prone to defects that cause noise and is better suited to the functionalization of different receptor molecules. Full article

Label-free field-effect transistor-based immunosensors are promising candidates for proteomics and peptidomics-based diagnostics and therapeutics due to their high multiplexing capability, fast response time, and ability to increase the sensor sensitivity due to the short length of peptides. In this work, planar junctionless field-effect transistor sensors (FETs) were fabricated and characterized for pH sensing. The device with SiO₂ gate oxide has shown voltage sensitivity of 41.8 ± 1.4, 39.9 ± 1.4, 39.0 ± 1.1, and 37.6 ± 1.0 mV/pH for constant drain currents of 5, 10, 20, and 50 nA, respectively, with a drain to source voltage of 0.05 V. The drift analysis shows a stability over time of −18 nA/h (pH 7.75), −3.5 nA/h (pH 6.84), −0.5 nA/h (pH 4.91), 0.5 nA/h (pH 3.43), corresponding to a pH drift of −0.45, −0.09, −0.01, and 0.01 per h. Theoretical modeling and simulation resulted in a mean value of the surface states of 3.8 × 10¹⁵/cm² with a standard deviation of 3.6 × 10¹⁵/cm². We have experimentally verified the number of surface sites due to APTES, peptide, and protein immobilization, which is in line with the theoretical calculations for FETs to be used for detecting peptide-protein interactions for future applications. Full article

Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as $I_{on}/I_{off}$ , $DIBL$ , and $SS$ , to highlight the advantages and disadvantages of each junctionless transistor category. Full article

In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to $90\%$ of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( $V_{th}$ ) or when it approaches the flat band voltage ( $V_{FB}$ ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than $1\%$ . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software. Full article