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Search Results (4)

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Keywords = on-chip spiral inductor

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11 pages, 7128 KiB  
Article
An On-Chip Balun Using Planar Spiral Inductors Based on Glass Wafer-Level IPD Technology
by Jiang Qian, Peng Wu, Haiyang Quan, Wei Wang, Yong Wang, Shanshan Sun and Jingchao Xia
Micromachines 2025, 16(4), 443; https://doi.org/10.3390/mi16040443 - 9 Apr 2025
Viewed by 2412
Abstract
As integrated electronic microsystems advance, their internal components demonstrate increasing miniaturization, higher-density integration, and, consequently, significantly enhanced performance. This paper presents an on-chip transformer balun. The balun has a combination of planar coupled inductors and filtering capacitors using integrated passive device (IPD) technology, [...] Read more.
As integrated electronic microsystems advance, their internal components demonstrate increasing miniaturization, higher-density integration, and, consequently, significantly enhanced performance. This paper presents an on-chip transformer balun. The balun has a combination of planar coupled inductors and filtering capacitors using integrated passive device (IPD) technology, giving it the advantages of a more compact circuit size and lower cost to achieve single-ended to differential function on glass substrates. Moreover, it can be integrated in systems by flip-chip. The die has a size of 1.81 mm × 1.36 mm with a −15 dB single-ended return loss bandwidth of 2.07 GHz to 4.30 GHz. Within this bandwidth, the maximum insertion loss is 2.56 dB, and the amplitude imbalance is less than 2.04 dB. The phase difference between the differential signals is 180 ± 14.02° and the common mode rejection ratio (CMRR) is above 19.08 dB. The balun has the potential of miniaturization for integration on package or through-glass interposers (TGIs). Full article
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13 pages, 3427 KiB  
Article
Modeling and Simulation of a Planar Permanent Magnet On-Chip Power Inductor
by Jaber A. Abu Qahouq and Mohammad K. Al-Smadi
Modelling 2024, 5(1), 339-351; https://doi.org/10.3390/modelling5010018 - 22 Feb 2024
Cited by 1 | Viewed by 1850
Abstract
The on-chip integration of a power inductor together with other power converter components of small sizes and high-saturation currents, while maintaining a desired or high inductance value, is here pursued. The use of soft magnetic cores increases inductance density but results in a [...] Read more.
The on-chip integration of a power inductor together with other power converter components of small sizes and high-saturation currents, while maintaining a desired or high inductance value, is here pursued. The use of soft magnetic cores increases inductance density but results in a reduced saturation current. This article presents a 3D physical model and a magnetic circuit model for an integrated on-chip power inductor (OPI) to double the saturation current using permanent magnet (PM) material. A ~50 nH, 7.5 A spiral permanent magnet on-chip power inductor (PMOI) is here designed, and a 3D physical model is then developed and simulated using the ANSYS®/Maxwell® software package (version 2017.1). The 3D physical model simulation results agree with the presented magnetic circuit model, and show that in the example PMOI design, the addition of the PM increases the saturation current of the OPI from 4 A to 7.5 A, while the size and inductance value remain unchanged. Full article
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12 pages, 4774 KiB  
Article
Electrical Modeling and Characterization of Graphene-Based On-Chip Spiral Inductors
by Da-Wei Wang, Meng-Jiao Yuan, Jia-Yun Dai and Wen-Sheng Zhao
Micromachines 2022, 13(11), 1829; https://doi.org/10.3390/mi13111829 - 26 Oct 2022
Cited by 5 | Viewed by 2867
Abstract
This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined [...] Read more.
This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined into the circuit model. It is demonstrated that the electrical characteristics of the on-chip square spiral inductor can be improved by replacing copper with graphene. Moreover, graphene exhibits more effectiveness in improving the inductance in tapered inductors than uniform ones. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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9 pages, 1469 KiB  
Article
Analytic Design of on-Chip Spiral Inductor with Variable Line Width
by Hao-Hui Chen and Yao-Wen Hsu
Electronics 2022, 11(13), 2029; https://doi.org/10.3390/electronics11132029 - 28 Jun 2022
Cited by 10 | Viewed by 6427
Abstract
On-chip spiral inductors with variable line width layouts are known for their high quality factor (Q-factor). In this paper, we present an analytical approach to facilitate the design of such inductors. Based on an analysis of ohmic and eddy-current losses, we first derive [...] Read more.
On-chip spiral inductors with variable line width layouts are known for their high quality factor (Q-factor). In this paper, we present an analytical approach to facilitate the design of such inductors. Based on an analysis of ohmic and eddy-current losses, we first derive an analytical formula for the metal resistance calculation of a spiral inductor. By minimizing the metal resistance, a simple design equation for finding the proper line width of each coil is then presented. Several 0.18 μm CMOS spiral inductors are investigated, via electromagnetic simulations and experimental studies, to test the proposed resistance calculation, as well as the variable line width design method. It is found that the developed resistance calculation can effectively model the metal-line resistance of a spiral inductor. Moreover, the inductor with a variable line width obtained using the proposed method can significantly improve the Q-factor with little compromise to inductance, which validates the capacity of the developed variable line width design technique. Since the proposed approach can be carried out using analytical calculations, it may be a more efficient design method than those previously reported in the literature. Full article
(This article belongs to the Special Issue Intelligent Signal Processing and Communication Systems)
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