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Search Results (3)

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Keywords = noise-reduced LDO regulator

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17 pages, 6368 KiB  
Article
A Low Phase Noise Crystal Oscillator with a Fast Start-Up Bandgap Reference for WLAN Applications
by Peng Wu, Peng Li, Xi Chen, Peng Cheng and Jian Zhu
Appl. Sci. 2023, 13(9), 5652; https://doi.org/10.3390/app13095652 - 4 May 2023
Cited by 1 | Viewed by 4380
Abstract
This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a [...] Read more.
This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a bandgap reference circuit that includes a start-up circuit and a low-voltage common-source common-gate current mirror, which ensures that the bandgap reference circuit is powered up effectively across all temperatures and process corners. A low-pass filter is also incorporated at the low dropout regulator (LDO) input to reduce the phase noise of the XO circuit. The experimental results demonstrate that the proposed design achieves a final phase noise of −164.36 dBc/Hz at 100 kHz offset frequency, with a power consumption of 0.444 mW. The test of start-up time is 0.718 ms and the compact chip area is 0.088 mm2. According to the simulation and test results, the final FOM value calculated in this paper is 209.93 dBc/Hz at 100 kHz offset. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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21 pages, 3016 KiB  
Review
Current Context and Research Trends in Linear DC–DC Converters
by Kosala Gunawardane, Nisitha Padmawansa, Nihal Kularatna, Kasun Subasinghage and Tek Tjing Lie
Appl. Sci. 2022, 12(9), 4594; https://doi.org/10.3390/app12094594 - 1 May 2022
Cited by 5 | Viewed by 3658
Abstract
With the introduction of switch-mode power supplies (SMPS) in the mid-1970s, the efficiency of DC–DC conversion rose from 60 to 80% and SMPS became a popular power supply solution. However, linear regulators have not become obsolete. The modern power management system in portable [...] Read more.
With the introduction of switch-mode power supplies (SMPS) in the mid-1970s, the efficiency of DC–DC conversion rose from 60 to 80% and SMPS became a popular power supply solution. However, linear regulators have not become obsolete. The modern power management system in portable devices supports a complex mix of DC–DC converters, combining switch-mode power supplies (SMPS), switched capacitor converters (SCCs), and linear regulators in the form of low-dropout regulators (LDOs). LDOs are used to supply low-voltage DC power rails with very low noise and high current slew rate capability, which are usually fed by the output rail of SMPS. This paper provides a comprehensive review of the evolution of the application scope of linear-type DC–DC converters in the power supply context and the present research trends. First, we review the context of linear DC–DC converters in detail, particularly in portable device power supplies. Then, the details of LDO regulators and their recent industry development and research trends are discussed. Then, the discussion focuses on supercapacitor-assisted low-dropout (SCALDO) regulator design and its scope in the portable device power management together with SCALDO-based dual output and reduced switch designs, and finally, the conclusions follow. Full article
(This article belongs to the Special Issue Research and Development on DC-DC Power Converters)
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13 pages, 3783 KiB  
Article
An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology
by Jian Chen, Wei Zhang, Qingqing Sun and Lizheng Liu
Electronics 2021, 10(14), 1686; https://doi.org/10.3390/electronics10141686 - 14 Jul 2021
Cited by 7 | Viewed by 5669
Abstract
This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure [...] Read more.
This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW. Full article
(This article belongs to the Section Circuit and Signal Processing)
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