Search Results (5)

According to the International Electrotechnical Commission, medium voltage ranges from 1 kV to 36 kV. In this voltage range, the field of power electronics has been focusing on developing power converters with high efficiency. Converters for such applications include solid-state transformers, energy storage systems for vehicle charging, electric aircraft, etc. Power ranges could reach tens to hundreds of kilowatts at relatively high frequency (10–50 kHz). Currently, there are no high-frequency power semiconductors capable of switching these voltage levels. Instead of using a single power switch, a string of power switches is used. The upper switches in the string require special attention because they need the highest isolation capabilities and a floating control signal and power supply for the gate driver. Many techniques have been proposed to accomplish this, but they commonly use separate circuits for the control signal and the power supply, increasing the cost, size, and complexity of the gate driver. This paper presents a gate driver for medium voltage with high-voltage isolation capabilities in a single structure for the control signal and the power supply. The proposed gate driver uses a resonant converter that transmits power within the gate driver information. A demodulator separates the gate driver information from the power signal, obtaining the power supply and the control signal for the switch. The paper includes simulation and experimental results that demonstrate the viability of the proposal. The experimental results show the principal features of the gate driver, achieving improvements in complexity, isolation capabilities, and both rise and fall times for large input capacitances of power semiconductor switches. The proposed gate driver presents a rise time of 44 ns and a fall time of 46 ns for the gate input capacitance of currently available SiC MOSFETs. The isolation barrier uses a 25 mm air gap, achieving an isolation capability of approximately 68.2 kV, which exceeds the requirements for MV applications. Full article

Multilevel inverters (MLIs) have recently attracted more attention in medium-voltage and high-power applications as they can provide an effective interface with photovoltaic (PV) systems. Conventional MLIs are used to generate higher voltage levels, which improve power quality and reduce the requirement for passive filters. However, recent research has focused on designing new MLI topologies using reduced switch counts and less voltage stress. This study, as such, proposes a new nine-level symmetric MLI for PV systems with a minimum number of switches. This decrease in the number of switches reduces the voltage stress across the switches and the number of driving circuits, which lowers the complexity of the control circuit and, as a result, lowers the cost and size of the system. This article compares the proposed MLI with other topologies based on the DC sources, switches count, gate driver circuits (N_gd), total standing voltage per unit (TSV_PU), cost function (CF), and components count per level (CC/L). The proposed topology is integrated with the PV system. MATLAB software is used to evaluate the performance of MLI at step change in irradiance and under variable load conditions. The total harmonic distortion (THD) of the proposed topology is reduced with the implementation of phase disposition pulse width modulation (PD-PWM). In addition, PD-PWM is compared with phase opposition disposition pulse width modulation (POD-PWM) and alternative phase opposition disposition pulse width (APOD-PWM) modulation techniques. The simulation results reveal the improved performance of the proposed topology at variable irradiance and under varying load conditions. The comparison results reveal minimum (TSV_PU), CC/L, CF, and switch count compared to existing topologies. Hence, the proposed topology of MLI is cost-effective and superior in all aspects compared to other topologies. In summary, it offers overall improved performance, and thus, it is feasible for the PV system. Full article

Single-ended resonant converters such as Class-E inverters have been widely considered as a potential topology for small- and medium-power wireless power transfer (WPT) applications, which feature compact circuits, low switching losses, and cost benefits, as they only use a low-side switch with a simple gate driver. However, there remains a practical challenge in the design of voltage stress, efficiency, and power density. In this paper, a single-ended resonant converter with a primary parallel resonant-matching network is investigated to absorb the bulky input-choke inductors of the Class-E inverters into the coil inductance. The analytical expressions for all the converter parameters are derived based on time-domain resonant waveforms, including: (1) analysis of critical zero-voltage switching (ZVS) conditions and (2) power transfer capabilities under the given maximum switch voltage stress. Furthermore, this paper elaborates on the design methodology of the proposed single-ended resonant converters, and an optimal operating point is chosen to ensure soft-switching operation and rated power. Finally, the accuracy of the proposed model is verified by simulation and experimental results. Full article

In recent years, multilevel inverters (MLIs) have emerged to be the most empowered power transformation technology for numerous operations such as renewable energy resources (RERs), flexible AC transmission systems (FACTS), electric motor drives, etc. MLI has gained popularity in medium- to high-power operations because of numerous merits such as minimum harmonic contents, less dissipation of power from power electronic switches, and less electromagnetic interference (EMI) at the receiving end. The MLI possesses many essential advantages in comparison to a conventional two-level inverter, such as voltage profile enhancement, increased efficiency of the overall system, the capability of high-quality output generation with the reduced switching frequency, decreased total harmonic distortions (THD) without reducing the power of the inverter and use of very low ratings of the device. Although classical MLIs find their use in various vital key areas, newer MLI configurations have an expanding concern to the limited count of power electronic devices, gate drivers, and isolated DC sources. In this review article, an attempt has been made to focus on various aspects of MLIs such as different configurations, modulation techniques, the concept of new reduced switch count MLI topologies, applications regarding interface with renewable energy, motor drives, and FACTS controller. Further, deep insights for future prospective towards hassle-free addition of MLI technology towards more enhanced application for various fields of the power system have also been discussed. This article is believed to be extremely helpful for academics, researchers, and industrialists working in the direction of MLI technology. Full article

This article discusses an active gate driver for a 1.7 kV/325 A SiC MOSFET module. The main purpose of the driver is to adjust the gate voltage in specified moments to speed up the turn-on cycle and reduce the amount of dissipated energy. Moreover, an adequate manipulation of the gate voltage is necessary as the gate current should be reduced during the rise of the drain current to avoid overshoots and oscillations. The gate voltage is switched at the right moments on the basis of the feedback signal provided from a measurement of the voltage across the parasitic source inductance of the module. This approach simplifies the circuit and provides no additional power losses in the measuring circuit. The paper contains the theoretical background and detailed description of the active gate driver design. The model of the parasitic-based active gate driver was verified using the double-pulse procedure both in Saber simulations and laboratory experiments. The active gate driver decreases the turn-on energy of a 1.7 kV/325 A SiC MOSFET by 7% comparing to a conventional gate driver (V_DS = 900 V, I_D = 270 A, R_G = 20 Ω). Furthermore, the proposed active gate driver lowered the turn-on cycle time from 478 to 390 ns without any serious oscillations in the main circuit. Full article