Search Results (3)

Metal-oxide-semiconductor (MOS)-based thin-film transistors (TFTs) are gaining significant attention in the field of flexible electronics due to their desirable electrical properties, such as high field-effect mobility (μ_FE), lower I_OFF, and excellent stability under bias stress. TFTs have widespread applications, such as printed electronics, flexible displays, smart cards, image sensors, virtual reality (VR) and augmented reality (AR), and the Internet of Things (IoT) devices. In this study, we approach using a low-temperature solution-processed hafnium zirconium oxide (HfZrOx) gate insulator (GI) to improve the performance of lanthanum zinc oxide (LaZnO) TFTs. For the optimization of HfZrO GI, HfZrO films were annealed at 200, 250, and 300 °C. The optimized HfZrO-250 °C GI-based LaZnO TFT shows the μ_FE of 19.06 cm²V⁻¹s⁻¹, threshold voltage (V_TH) of 1.98 V, hysteresis voltage (V_H) of 0 V, subthreshold swing (SS) of 256 mV/dec, and I_ON/I_OFF of ~10⁸. The flexible LaZnO TFT with HfZrO-250 °C GI exhibits negligible ΔV_TH of 0.25 V under positive-bias-temperature stress (PBTS). The flexible hysteresis-free LaZnO TFTs with HfZrO-250 °C can be widely used for flexible electronics. These enhancements were attributed to the smooth surface morphology and reduced defect density achieved with the HfZrO gate insulator. Therefore, the HfZrO/LaZnO approach holds great promise for next-generation MOS TFTs for flexible electronics. Full article

In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (V_t1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low V_t1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (V_h) and a low V_t1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies. Full article

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (V_t1), holding voltage (V_h) and secondary breakdown current (I_t2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the V_t1 and V_h values were closest to 21.85, and 9.27 V, respectively. The I_t2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low V_h characteristic. By removing the entire heavily doped drain-side N⁺ region, the equivalent series resistance in the drain region was increased, so that the I_t2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high V_h behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%. Full article