Search Results (6)

Electronic packaging can transform the chip to a device for assembly. Soldering and bonding are important procedures in the process of electronic packaging. The continuous development of packaging architecture has driven the emergence of improved soldering and bonding processes. At the same time, conventional soldering and bonding processes are still widely used in device packaging. This paper introduces two kinds of technologies in wafer bonding, direct and indirect, expounds on five kinds of die attachment processes, and also describes the process of ball bonding and wedge bonding in wire bonding in detail. Flip chip bonding and methods for making bumps are also described in depth. Bump bonding processes are vital for 3D-SiP packages, and the bonding technology of copper bumps is a research hotspot in the field of advanced packaging. The surface mount technology and sealing technology used in some electronic devices are also briefly introduced. This paper provides insights for researchers studying soldering and bonding in contemporary electronic device packaging. Full article

Flip Chip Ball Grid Array (FCBGA) packages, together with many other heterogeneous integration packages, are widely used in high I/O (Input/Output) density and high-performance computing applications. The thermal dissipation efficiency of such packages is often improved through the use of an external heat sink. However, the heat sink increases the solder joint inelastic strain energy density, and thus reduces the board-level thermal cycling test reliability. The present study constructs a three-dimensional (3D) numerical model to investigate the solder joint reliability of a lidless on-board FCBGA package with heat sink effects under thermal cycling testing, in accordance with JEDEC standard test condition G (a thermal range of −40 to 125 °C and a dwell/ramp time of 15/15 min). The validity of the numerical model is confirmed by comparing the predicted warpage of the FCBGA package with the experimental measurements obtained using a shadow moiré system. The effects of the heat sink and loading distance on the solder joint reliability performance are then examined. It is shown that the addition of the heat sink and a longer loading distance increase the solder ball creep strain energy density (CSED) and degrade the package reliability performance accordingly. Full article

Flip-chip bonding is a key packaging technology to achieve the smallest form factor possible. Using copper as a direct under-bump metal and performing bonding under little force and at a low temperature eliminates the processing step for the deposition of a suitable wetting metal and offers an economical solution for electronic chip packaging. In this paper, various samples with copper and nickel–gold surface finishes are used to apply an in-house solder bumping, flip-chip bonding and reflow process to exhibit the bump-bond feasibility. Native oxides are reduced using process gases, and copper surface protection and solder wetting are achieved using copper formate. Lead-free 40 µm solder balls were bumped on 80 µm copper pads and 120 µm copper pillars to demonstrate a full intermetallic Cu–Cu bond as a base study for stacking applications. Using a low-force bonding technique, various chips with different dimensions were bonded at 0.5–16 MPa, followed by a reflow step at a maximum temperature of 270 °C. Then, 30 µm solder balls are utilized to bump the samples with NiAu and Cu bond pads at 50 µm pitch. A mean shear strength of 44 MPa was obtained for the 30 µm Cu samples. To the best of our knowledge, 30 µm solder bumping directly on the copper pads by producing copper formate is a novel research contribution. Full article

Flip chip technology has been widely used in various fields. As the density of the solder balls in flip chip technology is increasing, the pitch among solder balls is narrowing, and the size effect is more significant. Therefore, the micro defects of the solder balls are more difficult to detect. In order to ensure the reliability of the flip chip, it is very important to detect and evaluate the micro defects of solder balls. High-frequency ultrasonic testing technology is an effective micro-defect detection method. In this paper, the interaction mechanism between high-frequency ultrasonic pulse and micro defects is analyzed by finite element simulation. A transient simulation model for the whole process of ultrasonic scanning of micro defects is established to simulate scanning in acoustic microscopy imaging. The acoustic propagation path map is obtained for analyzing acoustic energy transmission during detection, and the edge blurring effect in micro-defect imaging detection is clarified. The processing method of the time-domain signal and cross-section image signal of micro defects based on sparse reconstruction is studied, which can effectively improve the accuracy of detection and the signal-to-noise ratio. Full article

In this review, some major aspects of the current underfill technologies for flip-chip (FC) and fine-pitch-ball-grid-array (FPBGA), including chip-size packaging (CSP), are addressed, with an emphasis on applications, such as aerospace electronics, for which high reliability level is imperative. The following aspects of the FC and FPGGA technologies are considered: attributes of the FC and FPBGA structures and technologies; underfill-induced stresses; the roles of the glass transition temperature (T_g) of the underfill materials; some major attributes of the lead-free solder systems with underfill; reliability-related issues; thermal fatigue of the underfilled solder joints; warpage-related issues; attributes of accelerated life testing of solder joint interconnections with underfills; and predictive modeling, both finite-element-analysis (FEA)-based and analytical (“mathematical”). It is concluded particularly that the application of the quantitative assessments of the effect of the fabrication techniques on the reliability of solder materials, when high reliability is imperative, is critical and that all the three types of research tools that an aerospace reliability engineer has at his/her disposal, should be pursued, when appropriate and possible: experimental/testing, finite-element-analysis(FEA) simulations, and the “old-fashioned” analytical (“mathematical”) modeling. These two modeling techniques are based on different assumptions, and if the computed data obtained using these techniques result in the close output information, then there is a good reason to believe that this information is both accurate and trustworthy. This effort is particularly important for high-reliability FC and FPBGA applications, such as aerospace electronics, as the aerospace IC packages become more complex, and the requirements for their failure-free operations become more stringent. Full article

In order to solve tiny defect detection for solder balls in high-density flip-chip, this paper proposed feasibility study on the effect of detectability as well as classification based on eddy current pulsed thermography (ECPT). Specifically, numerical analysis of 3D finite element inductive heat model is generated to investigate disturbance on the temperature field for different kind of defects such as cracks, voids, etc. The temperature variation between defective and non-defective solder balls is monitored for defects identification and classification. Finally, experimental study is carried on the diameter 1mm tiny solder balls by using ECPT and verify the efficacy of the technique. Full article