Search Results (4)

A wet-etching technique based on a mixture of hydrochloric (HCl) and nitric (HNO₃) acids is introduced, demonstrating exceptional 42:1 selectivity for etching N-polar GaN over Al_0.24Ga_0.76N. In the absence of an AlGaN etch stop layer, the etchant primarily targets N-polar unintentionally doped (UID) GaN, indicating its potential as a suitable replacement for selective dry etches in the fabrication of GaN high-electron-mobility transistors (HEMTs). The efficacy and selectivity of this etchant were confirmed through its application to a gate recess module of a deep-recess HEMT, where, despite a 228% over-etch, the 2.6 nm AlGaN etch stop layer remained intact. We also evaluated the proposed method for the selective etching of the GaN cap in the n+ regrowth process, achieving a contact resistance matching that of a BCl₃/SF₆ ICP process. These findings underscore the applicability and versatility of the etchant in both the electronic and photonic domains and are particularly applicable to the development of N-polar deep-recess HEMTs. Full article

Reflectance anisotropy spectroscopy (RAS), which was originally invented to monitor epitaxial growth, can—as we have previously shown—also be used to monitor the reactive ion etching of III/V semiconductor samples in situ and in real time, as long as the etching rate is not too high and the abrasion at the etch front is not totally chaotic. Moreover, we have proven that—using RAS equipment and optical Fabry‒Perot oscillations due to the ever-shrinking thickness of the uppermost etched layer—the in situ etch-depth resolution can be as good as ±0.8 nm, employing a Vernier-scale type measurement and evaluation procedure. Nominally, this amounts to ±1.3 lattice constants in our exemplary material system, AlGaAsSb, on a GaAs or GaSb substrate. In this contribution, we show that resolutions of about ±5.6 nm can be reliably achieved without a Vernier scale protocol by employing thin doped layers or sharp interfaces between differently doped layers or quantum-dot (QD) layers as etch-stop indicators. These indicator layers can either be added to the device layer design on purpose or be part of it incidentally due to the functionality of the device. For typical etch rates in the range of 0.7 to 1.3 nm/s (that is, about 40 to 80 nm/min), the RAS spectrum will show a distinct change even for very thin indicator layers, which allows for the precise termination of the etch run. Full article

Heavily boron-doped silicon layers and boron etch-stop techniques have been widely used in the fabrication of microelectromechanical systems (MEMS). This paper provides an introduction to the fabrication process of nanoscale silicon thermoelectric devices. Low-dimensional structures such as silicon nanowire (SiNW) have been considered as a promising alternative for thermoelectric applications in order to achieve a higher thermoelectric figure of merit (ZT) than bulk silicon. Here, heavily boron-doped silicon layers and boron etch-stop processes for the fabrication of suspended SiNWs will be discussed in detail, including boron diffusion, electron beam lithography, inductively coupled plasma (ICP) etching and tetramethylammonium hydroxide (TMAH) etch-stop processes. A 7 μm long nanowire structure with a height of 280 nm and a width of 55 nm was achieved, indicating that the proposed technique is useful for nanoscale fabrication. Furthermore, a SiNW thermoelectric device has also been demonstrated, and its performance shows an obvious reduction in thermal conductivity. Full article

The channel fluorine implantation (CFI) process was integrated with the Si₃N₄ contact etch stop layer (SiN CESL) uniaxial-strained n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) with the hafnium oxide/silicon oxynitride (HfO₂/SiON) gate stack. The SiN CESL process clearly improves basic electrical performance, due to induced uniaxial tensile strain within the channel. However, further integrating of the CFI process with the SiN CESL-strained nMOSFET exhibits nearly identical transconductance, subthreshold swing, drain current, gate leakage and breakdown voltage, which indicates that the strain effect is not affected by the fluorine incorporation. Moreover, hydrogen will diffuse toward the interface during the SiN deposition, then passivate dangling bonds to form weak Si-H bonds, which is detrimental for channel hot electron stress (CHES). Before hydrogen diffusion, fluorine can be used to terminate oxygen vacancies and dangling bonds, which can create stronger Hf-F and Si-F bonds to resist consequent stress. Accordingly, the reliability of constant voltage stress (CVS) and CHES for the SiN CESL uniaxial-strained nMOSFET can be further improved by the fluorinated HfO₂/SiON using the CFI process. Nevertheless, the nMOSFET with either the SiN CESL or CFI process exhibits less charge detrapping, which means that a greater part of stress-induced charges would remain in the gate stack after nitrogen (SiN CESL) or fluorine (CFI) incorporation. Full article