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Keywords = double barrier/layer magnetic tunnel junction (DMTJ)

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13 pages, 2210 KiB  
Article
An Approach towards Designing Logic Locking Using Shape-Perpendicular Magnetic Anisotropy-Double Layer MTJ
by Divyanshu Divyanshu, Rajat Kumar, Danial Khan, Selma Amara and Yehia Massoud
Electronics 2023, 12(3), 479; https://doi.org/10.3390/electronics12030479 - 17 Jan 2023
Cited by 8 | Viewed by 1818
Abstract
In recent years, discovering various vulnerabilities in the IC supply chain has raised security concerns in electronic systems. Recent research has proposed numerous attack and defense mechanisms involving various nanoelectronic devices. Spintronic devices are a viable choice among various nanoelectronic devices because of [...] Read more.
In recent years, discovering various vulnerabilities in the IC supply chain has raised security concerns in electronic systems. Recent research has proposed numerous attack and defense mechanisms involving various nanoelectronic devices. Spintronic devices are a viable choice among various nanoelectronic devices because of their non-volatility, ease of fabrication with a silicon substrate, randomization in space and time, etc. This work uses a shape-perpendicular magnetic anisotropy-double oxide layer magnetic tunnel junction (s-PMA DMTJ) to construct a potential logic-locking (LL) defensive mechanism. s-PMA DMTJs can be used for more realistic novel solutions of secure hardware design due to their improved thermal stability and area efficiency compared to traditional MTJs. The LL system’s critical design range and viability are investigated in this work and compared with other two-terminal MTJ designs using various circuit analysis techniques, such as Monte Carlo simulations, eye diagram analysis, transient measurement, and parametric simulations. Hamming Distance of 25%, and output corruption coverage of 100% are achieved in the investigated test circuit. Full article
(This article belongs to the Section Semiconductor Devices)
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11 pages, 951 KiB  
Article
Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications
by Esteban Garzón, Marco Lanuzza, Ramiro Taco and Sebastiano Strangio
Electronics 2021, 10(15), 1756; https://doi.org/10.3390/electronics10151756 - 22 Jul 2021
Cited by 15 | Viewed by 4064
Abstract
Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for [...] Read more.
Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%. Full article
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