Search Results (6)

This paper analyses the parameterisation of protective relays in industrial power distribution stations, focusing on the quantitative relationship between network load and protection system response time. Laboratory simulations using a dedicated automation cabinet and varying network configurations (six streams at 80 samples/cycle and two to four streams at 256 samples/cycle) revealed a clear correlation: higher network loads lead to longer trip times. Under maximum load (four streams, 256 samples/cycle), response times reached up to 63.75 ms. These delays stemmed from network congestion rather than relay instability. The extended clearing times increased the short-circuit energy (I²t) by approximately 35% on average and over 55% in critical scenarios, requiring upsizing of PVC-insulated conductors from 16 mm² to 25 mm² to maintain short-circuit withstand capacity. The findings demonstrate the practical impact of network-induced delays on protection performance, thermal stress, and cable sizing, providing a basis for optimising relay settings and system configuration in modern digital power distribution networks. Full article

Zero-day attacks pose a persistent threat to computing infrastructure by exploiting previously unknown software vulnerabilities that evade traditional signature-based network intrusion detection systems (NIDSs). To address this limitation, machine learning (ML) techniques offer a promising approach for enhancing anomaly detection in network traffic. This study evaluates several ML models on a labeled network traffic dataset, with a focus on zero-day attack detection. Ensemble learning methods, particularly eXtreme gradient boosting (XGBoost), achieved perfect classification, identifying all 6231 zero-day instances without false positives and maintaining efficient training and prediction times. While classical support vector machines (SVMs) performed modestly at 64% accuracy, their performance improved to 98% with the use of the borderline synthetic minority oversampling technique (SMOTE) and SMOTE + edited nearest neighbours (SMOTEENN). To explore quantum-enhanced alternatives, a quantum SVM (QSVM) is implemented using three-qubit and four-qubit quantum circuits simulated on the aer_simulator_statevector. The QSVM achieved high accuracy (99.89%) and strong F1-scores (98.95%), indicating that nonlinear quantum feature maps (QFMs) can increase sensitivity to zero-day exploit patterns. Unlike prior work that applies standard quantum kernels, this study introduces a parameterised quantum feature encoding scheme, where each classical feature is mapped using a nonlinear function tuned by a set of learnable parameters. Additionally, a sparse entanglement topology is derived from mutual information between features, ensuring a compact and data-adaptive quantum circuit that aligns with the resource constraints of noisy intermediate-scale quantum (NISQ) devices. Our contribution lies in formalising a quantum circuit design that enables scalable, expressive, and generalisable quantum architectures tailored for zero-day attack detection. This extends beyond conventional usage of QSVMs by offering a principled approach to quantum circuit construction for cybersecurity. While these findings are obtained via noiseless simulation, they provide a theoretical proof of concept for the viability of quantum ML (QML) in network security. Future work should target real quantum hardware execution and adaptive sampling techniques to assess robustness under decoherence, gate errors, and dynamic threat environments. Full article

This work introduces a sophisticated impedance-based equivalent circuit model of the electrochemical processes inside a lithium-ion battery cell. The influence on the electrical voltage response is derived and merged into a mathematical calculation framework describing all fundamental phenomena inside a battery. The parameters, whose sole influences on the electric behaviour cannot be separated at the cell level, are summarised to derive a model with purely electrical quantities. We significantly reduce the model order compared to a physicochemical model while ensuring a minimal approximation error. Utilising the findings from the model derivation, we develop a parameterisation procedure to separate the individual processes occurring in the battery and to support a hypothesis of the assignment to positive and negative electrodes based on several indicia. For this purpose, electrochemical impedance spectroscopy and correlation analysis are used to calculate the distribution of the time constants. The final parameterised model has physics-based parameter variations, which ensures that the simulation over broad ranges of temperatures and states of charge results in a reasonable voltage response. The model’s physical basis enables extrapolation beyond the measured operation area, and the model verification shows less than a 10 mV root mean square error over a wide range of operations. Full article

As quantum computing technology continues to develop, the need for research into novel quantum algorithms is growing. However, such algorithms cannot yet be reliably tested on actual quantum hardware, which is still limited in several ways, including qubit coherence times, connectivity, and available qubits. To facilitate the development of novel algorithms despite this, simulators on classical computing systems are used to verify the correctness of an algorithm, and study its behaviour under different error models. In general, this involves operating on a memory space that grows exponentially with the number of qubits. In this work, we introduce quantum circuit transformations that allow for the construction of parameterised circuits for quantum algorithms. The parameterised circuits are in an ideal form to be processed by quantum compilation tools, such that the circuit can be partially evaluated prior to simulation, and a smaller specialised circuit can be constructed by eliminating fixed input qubits. We show significant reduction in the number of qubits for various quantum arithmetic circuits. Divide-by-n-bits quantum integer dividers are used as an example demonstration. It is shown that the complexity reduces from $4n+2$ to $3n+2$ qubits in the specialised versions. For quantum algorithms involving divide-by-8 arithmetic operations, a reduction by $2^8=256$ in required memory is achieved for classical simulation, reducing the memory required from 137 GB to 0.53 GB. Full article

Battery models are one of the most important tools for understanding the behaviour of batteries. This is particularly important for the fast-moving electrical vehicle industry, where new battery chemistries are continually being developed. The main limiting factor on how fast battery models can be developed is the experimental technique used for collection of data required for model parametrisation. Currently, this is a very time-consuming process. In this paper, a fast novel parametrisation testing technique is presented. A model is then parametrised using this testing technique and compared to a model parametrised using current common testing techniques. This comparison is conducted using a WLTP (worldwide harmonised light vehicle test procedure) drive cycle. As part of the validation, the experiments were conducted at different temperatures and repeated using two different temperature control methods: climate chamber and a Peltier element temperature control method. The new technique introduced in this paper, named AMPP (accelerated model parametrisation procedure), is as good as GITT (galvanostatic intermittent titration technique) for parametrisation of ECMs (equivalent circuit models); however, it is 90% faster. When using experimental data from a climate chamber, a model parametrised using GITT was marginally better than AMPP; however, when using experimental data using conductive control, such as the ICP (isothermal control platform), a model parametrised using AMPP performed as well as GITT at 25 °C and better than GITT at 10 °C. Full article

The protection of high voltage direct current (HVDC) grids is a challenge considering that the protection system must detect, locate, and interrupt large fault currents in a few milliseconds. Resistive type superconducting fault current limiters (R-SFCL) can help solve that difficult task, reducing the extremely demanding ratings of HVDC circuit breakers. This paper presents different approaches to model R-SFCLs in order to analyze their suitability for assessing the performance of HVDC grid protection, including the step model, the exponential model, the RQ model, and the magneto-thermal model. In the first instance, the R-SFCL models are evaluated in a test grid to analyze their parameterisation and select the most adequate model for the study of HVDC grids. The RQ model is finally chosen for its simplicity but closer behavior to the magneto thermal model in terms of fault resistance dependency and resistance evolution curve. Then, the performance of an RQ type R-SFCL model in conjunction with a mechanical circuit breaker is evaluated in a multiterminal HVDC grid with different fault cases. This way, fault currents are greatly decreased as well as circuit breaker requirements. Hence, the R-SFCL under study enables a reliable protection of the HVDC grid. Full article