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13 pages, 4553 KiB

Open AccessArticle

Obtaining Dissipative Kerr Solitons Deterministically Using Dual-Coupled Microresonators and a Simple Frequency Sweep

by Andrés F. Calvo-Salcedo, Neil Guerrero González and Jose A. Jaramillo-Villegas

Appl. Sci. 2024, 14(23), 10819; https://doi.org/10.3390/app142310819 - 22 Nov 2024

Viewed by 1036

The reliable generation of dissipative Kerr solitons (DKSs) enables applications in communications, metrology, optical clocks, and, more recently, artificial intelligence. We show how single DKS can be generated by Si₃N₄ dual-coupled microring resonators (DCMs). We modeled this coupled structure using the Lugiato–Lefever equation (LLE), including mode interactions in the dispersion profile. We also characterized the pump power and detuning parameter space for several mode interaction strengths and frequencies, and we found parameters for which a DKS could be deterministically obtained using a single, adiabatic frequency sweep with a constant pump power. We demonstrated deterministic single DKS generation for this path by simulating 200 times with different random noise inputs. This result paves the way for reliable, inexpensive, and deterministic single DKS generation in a simple setup. Full article

(This article belongs to the Section Optics and Lasers)

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17 pages, 1176 KiB

Open AccessArticle

EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices

by Zachary Kahleifeh and Himanshu Thapliyal

Sensors 2021, 21(22), 7651; https://doi.org/10.3390/s21227651 - 18 Nov 2021

Cited by 6 | Viewed by 2313

Abstract

Internet of Things (IoT) devices have strict energy constraints as they often operate on a battery supply. The cryptographic operations within IoT devices consume substantial energy and are vulnerable to a class of hardware attacks known as side-channel attacks. To reduce the energy consumption and defend against side-channel attacks, we propose combining adiabatic logic and Magnetic Tunnel Junctions to form our novel Energy Efficient-Adiabatic CMOS/MTJ Logic (EE-ACML). EE-ACML is shown to be both low energy and secure when compared to existing CMOS/MTJ architectures. EE-ACML reduces dynamic energy consumption with adiabatic logic, while MTJs reduce the leakage power of a circuit. To show practical functionality and energy savings, we designed one round of PRESENT-80 with the proposed EE-ACML integrated with an adiabatic clock generator. The proposed EE-ACML-based PRESENT-80 showed energy savings of 67.24% at 25 MHz and 86.5% at 100 MHz when compared with a previously proposed CMOS/MTJ circuit. Furthermore, we performed a CPA attack on our proposed design, and the key was kept secret. Full article

(This article belongs to the Special Issue Lightweight Security Integrity and Confidentiality for Internet of Things (IoT))

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15 pages, 4284 KiB

Open AccessArticle

Low-Power Two-Phase Clocking Adiabatic PUF Circuit

by Câncio Monteiro and Yasuhiro Takahashi

Electronics 2021, 10(11), 1258; https://doi.org/10.3390/electronics10111258 - 25 May 2021

Cited by 12 | Viewed by 3135

Abstract

Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C. Full article

(This article belongs to the Section Circuit and Signal Processing)

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