# Slew-Rate Enhancement Techniques for Switched-Capacitors Fast-Settling Amplifiers: A Review

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## Abstract

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## 1. Introduction

- High-linearity capacitors, ranging from few tens of femto-farads to hundreds of pico-farads, can be reliably realized in CMOS technologies, either as metal-insulator-metal (MIM) or metal-oxide-metal (MOM) structures.
- Versatile switches are realized with MOS transistors.
- The amplifiers involved in the SC circuits are loaded capacitively, hence simple Operational Transconductance Amplifier (OTA) structures are employed with respect to general-purpose Operational Amplifier (OpAmp) circuits.
- MOS devices at the input of the amplifiers do not draw DC bias currents, and hence charge transfer is precisely controlled over a wide range of clock frequencies.
- In contrast to traditional time-continuous operation, the SC approach offers discrete-time signal processing. The impact of non-linearity effects on the precision of the system is minimal, considering that system precision is evaluated at the end of discrete time phases, during which the amplifier output should be able to settle. The settling performance is often evaluated at the end of each phase, in terms of relative error with respect to an ideal response, determined by a capacitance ratio. Conversely, in continuous-time systems, non-linearity effects must be minimized throughout the entire transient duration. This distinction is crucial in making design choices for SC circuits, where non-linear circuit schemes are often adopted.

- Reduce charge injections resulting from transitions in the control signals that command the switches [8].
- Minimize noise introduced during signal processing in the charge domain [9]. At the same time, maximize the maximum input signal to improve the signal-to-distortion and noise ratio of the system.
- Settling speed is often traded with power consumption: numerous advanced circuital techniques have been proposed in the literature to obtain more beneficial balance.

## 2. Settling Time and Power Optimization

- (i)
- a small output voltage upset, denoted as ${V}_{o}^{\left(1\right)}\left(t\right)$;
- (ii)
- a large output voltage upset, denoted as ${V}_{o}^{\left(2\right)}\left(t\right)$.

- In the initial region, denoted by ${t}_{\mathrm{sr}}^{\left(2\right)}$, the output voltage (${V}_{o}^{\left(2\right)}\left(t\right)$) shows its maximum slope ($\frac{d{V}_{o}^{\left(2\right)}\left(t\right)}{dt}$), which in this phase is practically independent of the input signal.
- In the subsequent region, as ${V}_{o}^{\left(2\right)}\left(t\right)$ approaches its final value ${V}_{o}^{\left(2\right)}(+\infty )$, the behavior resembles that of scenario (i).

- The ${\alpha}_{rs}^{\left(2\right)}$ term reflects the residual voltage interval to be covered by the OTA after it ends the slewing phase. In this term, ${I}_{omax}{t}_{sr}^{\left(2\right)}/{C}_{LE}$ corresponds to the portion of the voltage upset related to the slewing phase, $\Delta {V}_{o,sr}^{\left(2\right)}$, also indicated in Figure 2. Intuitively, ${\alpha}_{sr}^{\left(2\right)}$ results in a decreasing function of ${V}_{id}$, since the residual voltage tends to very small values as $\Delta {V}_{o}(+\infty )$ is increased. However, ${\alpha}_{sr}^{\left(2\right)}$ will never be zero, since a certain amount of linear settling is always due. Notably, ${t}_{sr}^{\left(2\right)}$ results are inversely proportional to ${I}_{omax}$, and hence ${\alpha}_{sr}^{\left(2\right)}$ does not depend on the design choices related to ${I}_{omax}$.
- The most important term in (12) is represented by the exponential grow determined by the ${t}_{sr}/\tau $ ratio, causing distortion to rapidly grow with ${V}_{id}$, regardless of the partial compensation due to the ${\alpha}_{sr}^{\left(2\right)}$ term.

#### 2.1. Simplified Settling Model

- Abrupt transitions between the slew-rate and linear regions.
- Oversimplified modeling of ${G}_{m}$ and ${V}_{dmax}$.
- Inability to capture the effects of non-dominant singularities associated with OTA internal nodes (The presence of non-dominant singularities is typically addressed by introducing the phase margin parameter. In an ideal one-pole system, the phase margin assumes a value of 90 degrees. In practical designs, a phase margin degradation of up to 20 degrees is often tolerable without significantly affecting settling time. This aspect is discussed in Section 2.2 when two-stage architectures are introduced).

#### 2.2. Considerations on Single-Stage and Two-Stage OTA Architectures

#### 2.3. Figures of Merit (FoMs)

## 3. Advanced OTAs

#### 3.1. Cells and Methods for OTA Enhancement

#### 3.2. Flipped Voltage Follower (FVF) Cell

#### 3.3. Current Recycling and Mirror Nesting

#### 3.4. Non-Linear Current Mirrors

#### 3.5. Compound Body-Biased Mosfets

#### 3.6. Parallel-Type Slew-Rate Enhancer (PSRE)

## 4. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

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**Figure 1.**Schematic diagram of an inverting fully-differential SC integrator. Nominally ${C}_{1p}={C}_{1n}={C}_{1}$, ${C}_{2p}={C}_{2n}={C}_{2}$, ${C}_{3p}={C}_{3n}={C}_{3}$. Capacitors ${C}_{3p}$ and ${C}_{3n}$ represent the capacitive loads applied to the integrator. Phase ${\varphi}_{\mathrm{reset}}$ is used to establish the initial conditions of the integrator state variable. The differential input of the integrator is represented by ${V}_{ip}-{V}_{in}$, while the differential output is represented by ${V}_{op}-{V}_{on}$. For simplicity, the output and the input common mode voltages are identical and equal to ${V}_{cm}$. In this configuration, the output is valid at the end of ${\varphi}_{2}$.

**Figure 3.**Schematic diagram of a fully-differential SC integrator during the settling phase. The capacitor ${C}_{P}$ is associated to the OTA input device parasitic capacitance. The OTA has the idealized ${I}_{o}\left({V}_{i}\right)$ characteristic shown in the inset plot. ${I}_{o}$ represent the differential-mode current at the output of the OTA while ${V}_{i}$ represent the differential voltage at the input of the OTA. This idealized characteristic is fully described by the set of the following three parameters: ${G}_{m},{I}_{omax},{V}_{dmax}$. ${I}_{sup}$ indicates the current drawn from the supply voltage.

**Figure 4.**Numerical results for the settling-time model of Equation (16) with the following values: ${C}_{1}$ = 4 pF, ${C}_{2}$ = 32 pF, ${C}_{3}$ = 1 pF, ${C}_{P}$ = 0.2 pF, ${\u03f5}_{S}$ = 100 ppm, ${V}_{dmax}$ = 50 mV. Design case (A) features ${G}_{m}$ = 1.33 mS, ${I}_{omax}$ = 66.7 $\mathsf{\mu}$A, Design case (B) features ${G}_{m}$ = 1.33 mS, ${I}_{omax}$ = 266.7 $\mathsf{\mu}$A, Design case (C) features ${G}_{m}$ = 2.67 mS, ${I}_{omax}$ = 133.3 $\mathsf{\mu}$A. Subplot (

**a**) shows the ${t}_{S}$, ${t}_{lin}$ and ${t}_{sr}$ behavour as function of ${V}_{id}$. Subplot (

**b**) shows the maximum $|{V}_{id}|$ for ${t}_{S}\le {t}_{lin}^{\u2605}$ as a function of the slew-rate enhancing ratio ${I}_{omax}/\left({G}_{m}{V}_{dmax}\right)$, where ${t}_{lin}^{\u2605}$ is defined as ${t}_{lin}^{\u2605}={t}_{lin}({V}_{id}={V}_{dmax})$.

**Figure 5.**Schematic diagrams of (

**a**), a PMOS-input mirror OTA; (

**b**), a two-stage Miller-compensated PMOS-input OTA.

**Figure 6.**Simplified single-ended equivalent circuit of a two-stage amplifier with capacitive feedback.

**Figure 11.**Schematic diagrams of Flipped Voltage Follower employed as (

**a**) current buffer loop for class-AB current biasing, (

**b**) low-voltage current mirror.

**Figure 12.**Schematic diagrams of: (

**a**) transconductive core of the PMOS-input recycling folded cascode OTA, (

**b**) transconductive core of the PMOS-input nested-mirror OTA.

**Figure 13.**Schematic diagrams of non-linear current mirror configurations: (

**a**) gate-series ${V}_{C}\left({I}_{1}\right)$; (

**b**) same as previous but with constant ${V}_{G}$; (

**c**) source-series ${V}_{C}\left({I}_{1}\right)$; (

**d**) trivial implementation of the previous by the means of a resistor; (

**e**) body modulation at the input device.

**Figure 14.**Schematic diagrams of differential non-linear currents mirrors: (

**a**) structure based on local common-mode feedback circuit (LCMF) and (

**b**) structure based on the non-linear source degeneration.

**Figure 15.**Schematic diagrams of the compound body-biased MOSFET (CBBM): (

**a**) basic structure and (

**b**) small-signal circuits.

**Figure 16.**Schematic diagrams of (

**a**) OTA+PSRE configuration; (

**b**) Implementation of a PSRE based on current mirrors, enhanced by the boost capacitor ${C}_{B}$; (

**c**) Implementation of a class-B PSRE based on $RC$-bias ties.

Parameter | Expression | Meaning |
---|---|---|

${\u03f5}_{S}$ | Target settling error (%) [(8)] | |

${C}_{IE}$ | $({C}_{1}+{C}_{P})(1+{C}_{3}/{C}_{2})$ | Equiv. input capacitance |

${c}_{1}$ | $\left[{C}_{P}(1+{C}_{3}/{C}_{2})+{C}_{3}\right]/\left[{C}_{IE}+{C}_{3}\right]$ | Capacitive-network coeff. 1 |

${c}_{2}$ | $1+({C}_{2}+{C}_{P})/{C}_{1}$ | Capacitive-network coeff. 2 |

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## Share and Cite

**MDPI and ACS Style**

Dei, M.; Gagliardi, F.; Bruschi, P.
Slew-Rate Enhancement Techniques for Switched-Capacitors Fast-Settling Amplifiers: A Review. *Chips* **2024**, *3*, 98-128.
https://doi.org/10.3390/chips3020005

**AMA Style**

Dei M, Gagliardi F, Bruschi P.
Slew-Rate Enhancement Techniques for Switched-Capacitors Fast-Settling Amplifiers: A Review. *Chips*. 2024; 3(2):98-128.
https://doi.org/10.3390/chips3020005

**Chicago/Turabian Style**

Dei, Michele, Francesco Gagliardi, and Paolo Bruschi.
2024. "Slew-Rate Enhancement Techniques for Switched-Capacitors Fast-Settling Amplifiers: A Review" *Chips* 3, no. 2: 98-128.
https://doi.org/10.3390/chips3020005