Low-Cost Direct Digital Synthesis-Based On-Chip Waveform Generation for Analog/Mixed Signal BIST Applications^†

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The title describes a DDS for AMS BIST applications. However, the Abstract says that "This paper presents a hardware-synthesizable arbitrary waveform generator based on a DAC" and the use of "an all-digital on-chip test and calibration approach to nullify the effect of DAC nonlinearity", but the entire work describes only a DAC model with an extra bit of redundancy, already described in reference [27], with an INL estimation scheme and segmented analysis already presented in [26]. Besides the picture of the DAC layout, what is the real contribution of this work?

A few points that should be clarified:

i) What are the values ​​of Rx, Ry and Rz, to generate the redundancy bit of the proposed DAC, with respect to R (171)?

ii) What is the bit ratio between MSB, ISB and LSB used in the ADC and DAC (222)?

iii) It is assumed that there is an on-chip ADC, common in many SoCs (183), but whose configuration must be of the SAR type (191), and cannot be of the flash type (190). Many SoCs may come with Sigma-Delta ADCs. Would this make the design unfeasible? Shouldn't the ADC be implemented together with the DAC and other test and calibration circuits (7)?

iv) In line (197) it is said that "an ADC transition voltage, Ti, also has a corresponding transition output code from ci to ci+1". Does this Ti correspond to Tci in formula (3) or to a difference between Tci and Tci+1?

v) Is the variable M in expression (11) the same as M in lines (143) and (284)?

vi) What is the expression for Tci? Are Ci (uppercase) and ci (lowercase) the same variables or are they different?

vii) Is there no consideration of noise error?

viii) What is the value of Wr?

ix) Where is the low-pass filter (291) placed in the schematic in Figure 1?

x) How was the 'true' value of DAC and ADC INL (295) obtained?

xi) Equation (15) is meaningless.

xii) What are "100 random sine wave iterations" (325)?

xiii) In line 343 it is said that it "achieves 14-bit linearity using only 0.013% of the area". What area? How was it calculated?

xiv) In line (359) it is said that the results lead to "area and cost reductions". This relationship with Table 1 is not clear.

xv) Although the conclusions indicate that it "presented a novel and cost-effective approach to generating low-distortion waveforms without the need for high-precision instrumentation", the real contribution is not clear, as noted in i). The area reduction is also not clear. The abstract says that "a low-cost DAC and an all-digital on-chip test and calibration approach" were used, but the on-chip test and calibration were not explained. If they are based on calibration codes stored in memory, what is the real cost of this implementation?

Author Response

Word file attached. 

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The research topic of this article is to design an on-chip waveform generator suitable for analog/mixed signal (AMS) built-in self-test (BIST) applications based on low-cost direct digital synthesis (DDS) technology. The author proposes a hardware synthesis method for generating arbitrary waveforms based on low-cost DAC and ADC, and eliminates the impact of DAC nonlinearity on waveforms through digital calibration. The research has verified that this method can generate high linearity, high-precision waveforms with minimal hardware cost, achieving 12 bit effective resolution (ENOB) and SFDR and THD exceeding 100dB. The robustness of the architecture under process, voltage, and temperature (PVT) variations was demonstrated through simulation results. The research provides a low-cost solution for high-precision waveform generation in resource constrained systems, and the overall content of the article has high academic value. Several opinions for reference:

(1) The logical structure of the research is clear, the experimental design is reasonable, and the testing scheme estimates the nonlinear error through the joint measurement algorithm of DAC and ADC. Then, digital pre distortion is used for calibration, achieving waveform generation with high linearity. However, some key details of the experiment are not clearly explained in the article. For example, in the linearity estimation process of DAC and ADC, the impact of sampling points and testing conditions (such as signal frequency and sampling rate) on estimation errors has not been fully explained.

(2) The charts in the article are clear and intuitive, such as INL estimation error, FFT spectrogram, etc., which can effectively support the text content. Some tables and images lack sufficient annotations, and readers need to rely on the main text to fully understand them. Some parameters in Figures 6 and 7 that are not clearly labeled can be explained appropriately.

(3) The main contribution of this article is to propose a low-cost and high linear waveform generation method, and significantly reduce the matching requirements of DAC by introducing redundant bits and digital calibration techniques. The research results have important application value in resource constrained systems, and performance indicators such as SFDR and THD are superior to existing methods. However, the innovative explanation of the article is not sufficient, especially in the comparison with existing methods, which does not fully reflect the advantages of this study in terms of hardware implementation complexity and cost.

(4) The methodology section of the article provides a clear explanation, with detailed descriptions of the design architecture, calibration algorithm, and waveform generation process of the DAC. The simulation results also indicate that the method has good performance and robustness. The limitations of the research have not been fully discussed, such as the dependence of the method on hardware implementation and potential process limitations.

(5) The conclusion section summarizes the main findings of the study and proposes future work plans (such as hardware fabrication and experimental verification), providing direction for subsequent research. The specific plans for future work are relatively vague and lack detailed explanations.

(6) The article cites a large number of early literature to explain the research background and existing methods, but most of the cited studies are focused on a time frame of more than three years, lacking a comprehensive review and citation of the latest research results in related fields in the past three years. In recent years, multiple high-level studies have been published in related fields such as low-cost DAC design. These studies may have similarities or comparability with the method proposed in this paper, but they have not been mentioned or compared in the article.

Author Response

Word file attached. 

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

All questions were answered and the paper was corrected satisfactorily.

Reviewer 2 Report

Comments and Suggestions for Authors

The author has made appropriate revisions and is now ready for publication.